gem5  v21.1.0.2
Classes | Public Member Functions | Protected Attributes | Private Member Functions | Private Attributes | List of all members
gem5::SimpleCache Class Reference

A very simple cache object. More...

#include <simple_cache.hh>

Inheritance diagram for gem5::SimpleCache:
gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Classes

class  CPUSidePort
 Port on the CPU-side that receives requests. More...
 
class  MemSidePort
 Port on the memory-side that receives responses. More...
 
struct  SimpleCacheStats
 Cache statistics. More...
 

Public Member Functions

 SimpleCache (const SimpleCacheParams &params)
 constructor More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port with a given name and index. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void init ()
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbePoints ()
 Register probe points for this object. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
virtual void startup ()
 startup() is the final initialization call before simulation. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Protected Attributes

gem5::SimpleCache::SimpleCacheStats stats
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Private Member Functions

bool handleRequest (PacketPtr pkt, int port_id)
 Handle the request from the CPU side. More...
 
bool handleResponse (PacketPtr pkt)
 Handle the respone from the memory side. More...
 
void sendResponse (PacketPtr pkt)
 Send the packet to the CPU side. More...
 
void handleFunctional (PacketPtr pkt)
 Handle a packet functionally. More...
 
void accessTiming (PacketPtr pkt)
 Access the cache for a timing access. More...
 
bool accessFunctional (PacketPtr pkt)
 This is where we actually update / read from the cache. More...
 
void insert (PacketPtr pkt)
 Insert a block into the cache. More...
 
AddrRangeList getAddrRanges () const
 Return the address ranges this cache is responsible for. More...
 
void sendRangeChange () const
 Tell the CPU side to ask for our memory ranges. More...
 

Private Attributes

const Cycles latency
 Latency to check the cache. Number of cycles for both hit and miss. More...
 
const unsigned blockSize
 The block size for the cache. More...
 
const unsigned capacity
 Number of blocks in the cache (size of cache / block size) More...
 
std::vector< CPUSidePortcpuPorts
 Instantiation of the CPU-side port. More...
 
MemSidePort memPort
 Instantiation of the memory-side port. More...
 
bool blocked
 True if this cache is currently blocked waiting for a response. More...
 
PacketPtr originalPacket
 Packet that we are currently handling. More...
 
int waitingPortId
 The port to send the response when we recieve it back. More...
 
Tick missTime
 For tracking the miss latency. More...
 
std::unordered_map< Addr, uint8_t * > cacheStore
 An incredibly simple cache storage. Maps block addresses to data. More...
 

Additional Inherited Members

- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Detailed Description

A very simple cache object.

Has a fully-associative data store with random replacement. This cache is fully blocking (not non-blocking). Only a single request can be outstanding at a time. This cache is a writeback cache.

Definition at line 49 of file simple_cache.hh.

Constructor & Destructor Documentation

◆ SimpleCache()

gem5::SimpleCache::SimpleCache ( const SimpleCacheParams &  params)

constructor

Definition at line 39 of file simple_cache.cc.

References cpuPorts, gem5::csprintf(), gem5::ArmISA::i, gem5::Named::name(), and gem5::SimObject::params().

Member Function Documentation

◆ accessFunctional()

bool gem5::SimpleCache::accessFunctional ( PacketPtr  pkt)
private

This is where we actually update / read from the cache.

This function is executed on both timing and functional accesses.

Returns
true if a hit, false otherwise

Definition at line 342 of file simple_cache.cc.

References blockSize, cacheStore, gem5::Packet::getBlockAddr(), gem5::Packet::isRead(), gem5::Packet::isWrite(), panic, gem5::Packet::setDataFromBlock(), and gem5::Packet::writeDataToBlock().

Referenced by accessTiming(), handleFunctional(), and handleResponse().

◆ accessTiming()

void gem5::SimpleCache::accessTiming ( PacketPtr  pkt)
private

◆ getAddrRanges()

AddrRangeList gem5::SimpleCache::getAddrRanges ( ) const
private

Return the address ranges this cache is responsible for.

Just use the same as the next upper level of the hierarchy.

Returns
the address ranges this cache is responsible for

Definition at line 413 of file simple_cache.cc.

References DPRINTF, gem5::RequestPort::getAddrRanges(), and memPort.

◆ getPort()

Port & gem5::SimpleCache::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 
)
overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

Parameters
if_namePort name
idxIndex in the case of a VectorPort
Returns
A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 57 of file simple_cache.cc.

References cpuPorts, gem5::SimObject::getPort(), gem5::InvalidPortID, memPort, and panic_if.

◆ handleFunctional()

void gem5::SimpleCache::handleFunctional ( PacketPtr  pkt)
private

Handle a packet functionally.

Update the data on a write and get the data on a read. Called from CPU port on a recv functional.

Parameters
packetto functionally handle

Definition at line 274 of file simple_cache.cc.

References accessFunctional(), gem5::Packet::makeResponse(), memPort, and gem5::RequestPort::sendFunctional().

◆ handleRequest()

bool gem5::SimpleCache::handleRequest ( PacketPtr  pkt,
int  port_id 
)
private

Handle the request from the CPU side.

Called from the CPU port on a timing request.

Parameters
requestingpacket
idof the port to send the response
Returns
true if we can handle the request this cycle, false if the requestor needs to retry later

Definition at line 194 of file simple_cache.cc.

References accessTiming(), blocked, gem5::Clocked::clockEdge(), DPRINTF, gem5::Packet::getAddr(), latency, gem5::Named::name(), gem5::EventManager::schedule(), and waitingPortId.

◆ handleResponse()

bool gem5::SimpleCache::handleResponse ( PacketPtr  pkt)
private

Handle the respone from the memory side.

Called from the memory port on a timing response.

Parameters
respondingpacket
Returns
true if we can handle the response this cycle, false if the responder needs to retry later

Definition at line 219 of file simple_cache.cc.

References accessFunctional(), blocked, gem5::curTick(), DPRINTF, gem5::Packet::getAddr(), insert(), gem5::Packet::makeResponse(), gem5::SimpleCache::SimpleCacheStats::missLatency, missTime, originalPacket, panic_if, gem5::statistics::DistBase< Derived, Stor >::sample(), sendResponse(), and stats.

◆ insert()

void gem5::SimpleCache::insert ( PacketPtr  pkt)
private

Insert a block into the cache.

If there is no room left in the cache, then this function evicts a random entry t make room for the new block.

Parameters
packetwith the data (and address) to insert into the cache

Definition at line 362 of file simple_cache.cc.

References blockSize, cacheStore, capacity, data, gem5::Packet::dataDynamic(), DDUMP, DPRINTF, gem5::Packet::getAddr(), gem5::Packet::getBlockAddr(), gem5::Packet::getConstPtr(), gem5::Packet::isResponse(), memPort, gem5::Packet::print(), gem5::Random::random(), gem5::random_mt, gem5::SimpleCache::MemSidePort::sendPacket(), gem5::MemCmd::WritebackDirty, and gem5::Packet::writeDataToBlock().

Referenced by handleResponse().

◆ sendRangeChange()

void gem5::SimpleCache::sendRangeChange ( ) const
private

Tell the CPU side to ask for our memory ranges.

Definition at line 421 of file simple_cache.cc.

References cpuPorts.

◆ sendResponse()

void gem5::SimpleCache::sendResponse ( PacketPtr  pkt)
private

Send the packet to the CPU side.

This function assumes the pkt is already a response packet and forwards it to the correct port. This function also unblocks this object and cleans up the whole request.

Parameters
thepacket to send to the cpu side

Definition at line 249 of file simple_cache.cc.

References blocked, cpuPorts, DPRINTF, gem5::Packet::getAddr(), and waitingPortId.

Referenced by accessTiming(), and handleResponse().

Member Data Documentation

◆ blocked

bool gem5::SimpleCache::blocked
private

True if this cache is currently blocked waiting for a response.

Definition at line 282 of file simple_cache.hh.

Referenced by handleRequest(), handleResponse(), and sendResponse().

◆ blockSize

const unsigned gem5::SimpleCache::blockSize
private

The block size for the cache.

Definition at line 270 of file simple_cache.hh.

Referenced by accessFunctional(), accessTiming(), and insert().

◆ cacheStore

std::unordered_map<Addr, uint8_t*> gem5::SimpleCache::cacheStore
private

An incredibly simple cache storage. Maps block addresses to data.

Definition at line 295 of file simple_cache.hh.

Referenced by accessFunctional(), and insert().

◆ capacity

const unsigned gem5::SimpleCache::capacity
private

Number of blocks in the cache (size of cache / block size)

Definition at line 273 of file simple_cache.hh.

Referenced by insert().

◆ cpuPorts

std::vector<CPUSidePort> gem5::SimpleCache::cpuPorts
private

Instantiation of the CPU-side port.

Definition at line 276 of file simple_cache.hh.

Referenced by getPort(), sendRangeChange(), sendResponse(), and SimpleCache().

◆ latency

const Cycles gem5::SimpleCache::latency
private

Latency to check the cache. Number of cycles for both hit and miss.

Definition at line 267 of file simple_cache.hh.

Referenced by handleRequest().

◆ memPort

MemSidePort gem5::SimpleCache::memPort
private

Instantiation of the memory-side port.

Definition at line 279 of file simple_cache.hh.

Referenced by accessTiming(), getAddrRanges(), getPort(), handleFunctional(), and insert().

◆ missTime

Tick gem5::SimpleCache::missTime
private

For tracking the miss latency.

Definition at line 292 of file simple_cache.hh.

Referenced by accessTiming(), and handleResponse().

◆ originalPacket

PacketPtr gem5::SimpleCache::originalPacket
private

Packet that we are currently handling.

Used for upgrading to larger cache line sizes

Definition at line 286 of file simple_cache.hh.

Referenced by accessTiming(), and handleResponse().

◆ stats

gem5::SimpleCache::SimpleCacheStats gem5::SimpleCache::stats
protected

Referenced by accessTiming(), and handleResponse().

◆ waitingPortId

int gem5::SimpleCache::waitingPortId
private

The port to send the response when we recieve it back.

Definition at line 289 of file simple_cache.hh.

Referenced by handleRequest(), and sendResponse().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:28:10 for gem5 by doxygen 1.8.17