gem5  v21.2.0.0
simple_memobj.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2017 Jason Lowe-Power
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #ifndef __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
30 #define __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
31 
32 #include "mem/port.hh"
33 #include "params/SimpleMemobj.hh"
34 #include "sim/sim_object.hh"
35 
36 namespace gem5
37 {
38 
45 class SimpleMemobj : public SimObject
46 {
47  private:
48 
54  class CPUSidePort : public ResponsePort
55  {
56  private:
59 
61  bool needRetry;
62 
65 
66  public:
70  CPUSidePort(const std::string& name, SimpleMemobj *owner) :
72  blockedPacket(nullptr)
73  { }
74 
81  void sendPacket(PacketPtr pkt);
82 
90  AddrRangeList getAddrRanges() const override;
91 
96  void trySendRetry();
97 
98  protected:
103  Tick recvAtomic(PacketPtr pkt) override
104  { panic("recvAtomic unimpl."); }
105 
112  void recvFunctional(PacketPtr pkt) override;
113 
122  bool recvTimingReq(PacketPtr pkt) override;
123 
129  void recvRespRetry() override;
130  };
131 
136  class MemSidePort : public RequestPort
137  {
138  private:
141 
144 
145  public:
149  MemSidePort(const std::string& name, SimpleMemobj *owner) :
151  { }
152 
159  void sendPacket(PacketPtr pkt);
160 
161  protected:
165  bool recvTimingResp(PacketPtr pkt) override;
166 
172  void recvReqRetry() override;
173 
181  void recvRangeChange() override;
182  };
183 
191  bool handleRequest(PacketPtr pkt);
192 
200  bool handleResponse(PacketPtr pkt);
201 
208  void handleFunctional(PacketPtr pkt);
209 
217 
221  void sendRangeChange();
222 
226 
229 
231  bool blocked;
232 
233  public:
234 
237  SimpleMemobj(const SimpleMemobjParams &params);
238 
249  Port &getPort(const std::string &if_name,
250  PortID idx=InvalidPortID) override;
251 };
252 
253 } // namespace gem5
254 
255 #endif // __LEARNING_GEM5_PART2_SIMPLE_MEMOBJ_HH__
gem5::SimpleMemobj::CPUSidePort::CPUSidePort
CPUSidePort(const std::string &name, SimpleMemobj *owner)
Constructor.
Definition: simple_memobj.hh:70
gem5::SimpleMemobj::MemSidePort::owner
SimpleMemobj * owner
The object that owns this object (SimpleMemobj)
Definition: simple_memobj.hh:140
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SimpleMemobj::CPUSidePort::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the request port.
Definition: simple_memobj.hh:103
gem5::SimpleMemobj::CPUSidePort::recvTimingReq
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the request port.
Definition: simple_memobj.cc:102
gem5::SimpleMemobj::sendRangeChange
void sendRangeChange()
Tell the CPU side to ask for our memory ranges.
Definition: simple_memobj.cc:229
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::SimpleMemobj::SimpleMemobj
SimpleMemobj(const SimpleMemobjParams &params)
constructor
Definition: simple_memobj.cc:37
gem5::SimpleMemobj::MemSidePort::blockedPacket
PacketPtr blockedPacket
If we tried to send a packet and it was blocked, store it here.
Definition: simple_memobj.hh:143
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::SimpleMemobj::CPUSidePort::blockedPacket
PacketPtr blockedPacket
If we tried to send a packet and it was blocked, store it here.
Definition: simple_memobj.hh:64
gem5::SimpleMemobj::CPUSidePort::getAddrRanges
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: simple_memobj.cc:78
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::SimpleMemobj::CPUSidePort::sendPacket
void sendPacket(PacketPtr pkt)
Send a packet across this port.
Definition: simple_memobj.cc:65
gem5::SimpleMemobj::handleResponse
bool handleResponse(PacketPtr pkt)
Handle the respone from the memory side.
Definition: simple_memobj.cc:187
gem5::SimpleMemobj::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: simple_memobj.cc:47
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::SimpleMemobj::MemSidePort::recvRangeChange
void recvRangeChange() override
Called to receive an address range change from the peer responder port.
Definition: simple_memobj.cc:162
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SimpleMemobj::memPort
MemSidePort memPort
Instantiation of the memory-side port.
Definition: simple_memobj.hh:228
gem5::SimpleMemobj::MemSidePort::sendPacket
void sendPacket(PacketPtr pkt)
Send a packet across this port.
Definition: simple_memobj.cc:128
port.hh
gem5::SimpleMemobj::CPUSidePort::needRetry
bool needRetry
True if the port needs to send a retry req.
Definition: simple_memobj.hh:61
gem5::SimpleMemobj::MemSidePort
Port on the memory-side that receives responses.
Definition: simple_memobj.hh:136
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::SimpleMemobj::CPUSidePort
Port on the CPU-side that receives requests.
Definition: simple_memobj.hh:54
gem5::SimpleMemobj::handleRequest
bool handleRequest(PacketPtr pkt)
Handle the request from the CPU side.
Definition: simple_memobj.cc:168
gem5::SimpleMemobj::handleFunctional
void handleFunctional(PacketPtr pkt)
Handle a packet functionally.
Definition: simple_memobj.cc:214
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::SimpleMemobj::MemSidePort::recvReqRetry
void recvReqRetry() override
Called by the response port if sendTimingReq was called on this request port (causing recvTimingReq t...
Definition: simple_memobj.cc:148
gem5::SimpleMemobj::getAddrRanges
AddrRangeList getAddrRanges() const
Return the address ranges this memobj is responsible for.
Definition: simple_memobj.cc:221
gem5::SimpleMemobj::blocked
bool blocked
True if this is currently blocked waiting for a response.
Definition: simple_memobj.hh:231
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::SimpleMemobj::CPUSidePort::recvFunctional
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the request port.
Definition: simple_memobj.cc:95
gem5::SimpleMemobj::CPUSidePort::trySendRetry
void trySendRetry()
Send a retry to the peer port only if it is needed.
Definition: simple_memobj.cc:84
gem5::SimpleMemobj::MemSidePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the response port.
Definition: simple_memobj.cc:141
gem5::SimpleMemobj::instPort
CPUSidePort instPort
Instantiation of the CPU-side ports.
Definition: simple_memobj.hh:224
std::list< AddrRange >
gem5::SimpleMemobj::CPUSidePort::owner
SimpleMemobj * owner
The object that owns this object (SimpleMemobj)
Definition: simple_memobj.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::SimpleMemobj::dataPort
CPUSidePort dataPort
Definition: simple_memobj.hh:225
gem5::SimpleMemobj
A very simple memory object.
Definition: simple_memobj.hh:45
gem5::SimpleMemobj::CPUSidePort::recvRespRetry
void recvRespRetry() override
Called by the request port if sendTimingResp was called on this response port (causing recvTimingResp...
Definition: simple_memobj.cc:114
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::SimpleMemobj::MemSidePort::MemSidePort
MemSidePort(const std::string &name, SimpleMemobj *owner)
Constructor.
Definition: simple_memobj.hh:149

Generated on Tue Dec 21 2021 11:34:31 for gem5 by doxygen 1.8.17