smmu_v3.hh File Reference

This is an implementation of the SMMUv3 architecture. More...

#include <list>
#include <map>
#include <queue>
#include <string>
#include <vector>
#include "base/statistics.hh"
#include "dev/arm/smmu_v3_caches.hh"
#include "dev/arm/smmu_v3_cmdexec.hh"
#include "dev/arm/smmu_v3_defs.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "mem/packet.hh"
#include "params/SMMUv3.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"

Go to the source code of this file.

Classes
class	gem5::SMMUv3
struct	gem5::SMMUv3::SMMUv3Stats

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

Detailed Description

This is an implementation of the SMMUv3 architecture.

What can it do?

• Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add.
• Large pages are supported.
• Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId

What it can't do?

• Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported
• Invalidations take zero time. This wouldn't be hard to fix.
• Checkpointing is not supported
• Stall/resume for faulting transactions is not supported

Definition in file smmu_v3.hh.