gem5 v24.0.0.0
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smmu_v3.hh File Reference

This is an implementation of the SMMUv3 architecture. More...

#include <list>
#include <map>
#include <queue>
#include <string>
#include <vector>
#include "base/statistics.hh"
#include "dev/arm/smmu_v3_caches.hh"
#include "dev/arm/smmu_v3_cmdexec.hh"
#include "dev/arm/smmu_v3_defs.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "mem/packet.hh"
#include "params/SMMUv3.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"

Go to the source code of this file.


class  gem5::SMMUv3
struct  gem5::SMMUv3::SMMUv3Stats


namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

Detailed Description

This is an implementation of the SMMUv3 architecture.

What can it do?

  • Single-stage and nested translation with 4k or 64k granule. 16k would be straightforward to add.
  • Large pages are supported.
  • Works with any gem5 device as long as it is issuing packets with a valid (Sub)StreamId

What it can't do?

  • Fragment stage 1 page when the underlying stage 2 page is smaller. S1 page size > S2 page size is not supported
  • Invalidations take zero time. This wouldn't be hard to fix.
  • Checkpointing is not supported
  • Stall/resume for faulting transactions is not supported

Definition in file smmu_v3.hh.

Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0