gem5  v21.1.0.2
smmu_v3_deviceifc.hh
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37 
38 #ifndef __DEV_ARM_SMMU_V3_DEVICEIFC_HH__
39 #define __DEV_ARM_SMMU_V3_DEVICEIFC_HH__
40 
41 #include <list>
42 
44 #include "dev/arm/smmu_v3_defs.hh"
46 #include "dev/arm/smmu_v3_ports.hh"
47 #include "dev/arm/smmu_v3_proc.hh"
48 #include "params/SMMUv3DeviceInterface.hh"
49 #include "sim/clocked_object.hh"
50 
51 namespace gem5
52 {
53 
54 class SMMUTranslationProcess;
55 class SMMUv3;
56 class SMMUDevicePort;
57 
59 {
60  protected:
61  friend class SMMUTranslationProcess;
62 
63  public:
67 
68  const bool microTLBEnable;
69  const bool mainTLBEnable;
70 
74 
77 
81 
82  // in bytes
83  const unsigned portWidth;
84 
88 
89  const bool prefetchEnable;
91 
94 
98 
99  // Receiving translation requests from the requestor device
101  bool recvTimingReq(PacketPtr pkt);
102  void schedTimingResp(PacketPtr pkt);
103 
105  bool atsRecvTimingReq(PacketPtr pkt);
106  bool atsRecvTimingResp(PacketPtr pkt);
107  void schedAtsTimingResp(PacketPtr pkt);
108 
109  void scheduleDeviceRetry();
110  void sendDeviceRetry();
111  void atsSendDeviceRetry();
112 
115 
117  EventWrapper<
120 
121  Port& getPort(const std::string &name, PortID id) override;
122 
123  public:
126 
128  {
129  delete microTLB;
130  delete mainTLB;
131  }
132 
133  DrainState drain() override;
134 
135  void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
136  void sendRange();
137 };
138 
139 } // namespace gem5
140 
141 #endif /* __DEV_ARM_SMMU_V3_DEVICEIFC_HH__ */
gem5::SMMUv3DeviceInterface::recvTimingReq
bool recvTimingReq(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:144
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SMMUv3DeviceInterface::microTLBEnable
const bool microTLBEnable
Definition: smmu_v3_deviceifc.hh:68
gem5::EventWrapper
Definition: eventq.hh:1084
gem5::SMMUv3DeviceInterface::mainTLBLat
const Cycles mainTLBLat
Definition: smmu_v3_deviceifc.hh:76
gem5::SMMUATSMemoryPort
Definition: smmu_v3_ports.hh:112
gem5::SMMUv3DeviceInterface::deviceNeedsRetry
bool deviceNeedsRetry
Definition: smmu_v3_deviceifc.hh:113
gem5::SMMUv3DeviceInterface::microTLB
SMMUTLB * microTLB
Definition: smmu_v3_deviceifc.hh:65
gem5::SMMUv3DeviceInterface::schedTimingResp
void schedTimingResp(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:111
gem5::SMMUv3DeviceInterface::devicePortSem
SMMUSemaphore devicePortSem
Definition: smmu_v3_deviceifc.hh:71
gem5::SMMUv3DeviceInterface::atsMemPort
SMMUATSMemoryPort atsMemPort
Definition: smmu_v3_deviceifc.hh:80
gem5::SMMUv3DeviceInterface::prefetchEnable
const bool prefetchEnable
Definition: smmu_v3_deviceifc.hh:89
smmu_v3_events.hh
gem5::SMMUv3DeviceInterface::mainTLBEnable
const bool mainTLBEnable
Definition: smmu_v3_deviceifc.hh:69
gem5::SMMUv3DeviceInterface::sendDeviceRetryEvent
SMMUDeviceRetryEvent sendDeviceRetryEvent
Definition: smmu_v3_deviceifc.hh:116
gem5::SMMUv3DeviceInterface::sendRange
void sendRange()
Definition: smmu_v3_deviceifc.cc:85
gem5::SMMUv3DeviceInterface::atsSendDeviceRetryEvent
EventWrapper< SMMUv3DeviceInterface, &SMMUv3DeviceInterface::atsSendDeviceRetry > atsSendDeviceRetryEvent
Definition: smmu_v3_deviceifc.hh:119
gem5::SMMUv3
Definition: smmu_v3.hh:85
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::SMMUv3DeviceInterface::atsRecvAtomic
Tick atsRecvAtomic(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:176
gem5::SMMUv3DeviceInterface::mainTLBSem
SMMUSemaphore mainTLBSem
Definition: smmu_v3_deviceifc.hh:73
gem5::SMMUv3DeviceInterface::dependentReads
std::list< SMMUTranslationProcess * > dependentReads[SMMU_MAX_TRANS_ID]
Definition: smmu_v3_deviceifc.hh:95
gem5::SMMUTLB
Definition: smmu_v3_caches.hh:99
gem5::SMMUv3DeviceInterface::portWidth
const unsigned portWidth
Definition: smmu_v3_deviceifc.hh:83
gem5::SMMUv3DeviceInterface::atsRecvTimingReq
bool atsRecvTimingReq(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:194
gem5::SMMUv3DeviceInterface::schedAtsTimingResp
void schedAtsTimingResp(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:117
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::SMMUSignal
Definition: smmu_v3_proc.hh:92
gem5::SMMUATSDevicePort
Definition: smmu_v3_ports.hh:126
gem5::SMMUv3DeviceInterface::devicePort
SMMUDevicePort * devicePort
Definition: smmu_v3_deviceifc.hh:78
smmu_v3_ports.hh
gem5::SMMUv3DeviceInterface::atsSendDeviceRetry
void atsSendDeviceRetry()
Definition: smmu_v3_deviceifc.cc:242
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::SMMUSemaphore
Definition: smmu_v3_proc.hh:81
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::SMMUv3DeviceInterface::dependentReqRemoved
SMMUSignal dependentReqRemoved
Definition: smmu_v3_deviceifc.hh:97
gem5::SMMUv3DeviceInterface::SMMUv3DeviceInterface
SMMUv3DeviceInterface(const Params &p)
Definition: smmu_v3_deviceifc.cc:48
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SMMUv3DeviceInterface::atsDevicePort
SMMUATSDevicePort atsDevicePort
Definition: smmu_v3_deviceifc.hh:79
gem5::SMMUDevicePort
Definition: smmu_v3_ports.hh:77
gem5::SMMU_MAX_TRANS_ID
@ SMMU_MAX_TRANS_ID
Definition: smmu_v3_defs.hh:410
gem5::SMMUv3DeviceInterface::sendDeviceRetry
void sendDeviceRetry()
Definition: smmu_v3_deviceifc.cc:236
gem5::SMMUv3DeviceInterface::dependentWrites
std::list< SMMUTranslationProcess * > dependentWrites[SMMU_MAX_TRANS_ID]
Definition: smmu_v3_deviceifc.hh:96
gem5::SMMUv3DeviceInterface::microTLBSem
SMMUSemaphore microTLBSem
Definition: smmu_v3_deviceifc.hh:72
gem5::SMMUv3DeviceInterface::pendingMemAccesses
unsigned pendingMemAccesses
Definition: smmu_v3_deviceifc.hh:87
gem5::SMMUv3DeviceInterface
Definition: smmu_v3_deviceifc.hh:58
gem5::SMMUv3DeviceInterface::duplicateReqRemoved
SMMUSignal duplicateReqRemoved
Definition: smmu_v3_deviceifc.hh:93
gem5::SMMUv3DeviceInterface::smmu
SMMUv3 * smmu
Definition: smmu_v3_deviceifc.hh:64
gem5::SMMUv3DeviceInterface::PARAMS
PARAMS(SMMUv3DeviceInterface)
gem5::SMMUv3DeviceInterface::prefetchReserveLastWay
const bool prefetchReserveLastWay
Definition: smmu_v3_deviceifc.hh:90
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::SMMUv3DeviceInterface::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: smmu_v3_deviceifc.cc:259
gem5::SMMUv3DeviceInterface::scheduleDeviceRetry
void scheduleDeviceRetry()
Definition: smmu_v3_deviceifc.cc:249
smmu_v3_proc.hh
gem5::SMMUv3DeviceInterface::mainTLB
SMMUTLB * mainTLB
Definition: smmu_v3_deviceifc.hh:66
smmu_v3_caches.hh
gem5::SMMUv3DeviceInterface::xlateSlotsRemaining
unsigned xlateSlotsRemaining
Definition: smmu_v3_deviceifc.hh:86
gem5::SMMUv3DeviceInterface::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:128
gem5::SMMUv3DeviceInterface::duplicateReqs
std::list< SMMUTranslationProcess * > duplicateReqs
Definition: smmu_v3_deviceifc.hh:92
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
clocked_object.hh
gem5::SMMUv3DeviceInterface::~SMMUv3DeviceInterface
~SMMUv3DeviceInterface()
Definition: smmu_v3_deviceifc.hh:127
gem5::SMMUv3DeviceInterface::atsDeviceNeedsRetry
bool atsDeviceNeedsRetry
Definition: smmu_v3_deviceifc.hh:114
gem5::SMMUv3DeviceInterface::microTLBLat
const Cycles microTLBLat
Definition: smmu_v3_deviceifc.hh:75
gem5::ClockedObject::Params
ClockedObjectParams Params
Parameters of ClockedObject.
Definition: clocked_object.hh:240
gem5::SMMUv3DeviceInterface::wrBufSlotsRemaining
unsigned wrBufSlotsRemaining
Definition: smmu_v3_deviceifc.hh:85
gem5::SMMUv3DeviceInterface::setSMMU
void setSMMU(SMMUv3 *_smmu)
Definition: smmu_v3_deviceifc.hh:135
std::list
STL list class.
Definition: stl.hh:51
smmu_v3_defs.hh
gem5::SMMUDeviceRetryEvent
Definition: smmu_v3_events.hh:49
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SMMUv3DeviceInterface::atsRecvTimingResp
bool atsRecvTimingResp(PacketPtr pkt)
Definition: smmu_v3_deviceifc.cc:219
gem5::SMMUv3DeviceInterface::getPort
Port & getPort(const std::string &name, PortID id) override
Get a port with a given name and index.
Definition: smmu_v3_deviceifc.cc:97
gem5::SMMUTranslationProcess
Definition: smmu_v3_transl.hh:66

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