gem5 v24.0.0.0
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smmu_v3_caches.hh
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1/*
2 * Copyright (c) 2014, 2018-2019, 2021 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DEV_ARM_SMMU_V3_CACHES_HH__
39#define __DEV_ARM_SMMU_V3_CACHES_HH__
40
41#include <stdint.h>
42
43#include <array>
44#include <cstddef>
45#include <string>
46#include <vector>
47
48#include "base/random.hh"
49#include "base/statistics.hh"
50#include "base/types.hh"
51
52#define WALK_CACHE_LEVELS 4
53
54namespace gem5
55{
56
57enum
58{
62};
63
98
100{
101 public:
108
109 struct Entry
110 {
111 bool valid;
113 mutable uint32_t lastUsed;
114
115 // TAGS
116 uint32_t sid;
117 uint32_t ssid;
120
121 // EXTRA TAGS
122 uint16_t asid;
123 uint16_t vmid;
124
125 // OUTPUTS
127 uint8_t permissions;
128 };
129
130 SMMUTLB(unsigned numEntries, unsigned _associativity,
131 const std::string &policy, statistics::Group *parent,
132 const std::string &name);
133 SMMUTLB(const SMMUTLB& tlb) = delete;
134 virtual ~SMMUTLB() {}
135
136 const Entry *lookup(uint32_t sid, uint32_t ssid, Addr va,
137 bool updStats=true);
138 const Entry *lookupAnyVA(uint32_t sid, uint32_t ssid,
139 bool updStats=true);
140 void store(const Entry &incoming, AllocPolicy alloc);
141
142 void invalidateSSID(uint32_t sid, uint32_t ssid);
143 void invalidateSID(uint32_t sid);
144 void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
145 void invalidateVAA(Addr va, uint16_t vmid);
146 void invalidateASID(uint16_t asid, uint16_t vmid);
147 void invalidateVMID(uint16_t vmid);
148 void invalidateAll();
149
150 private:
153
155
156 size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
157 size_t pickSetIdx(Addr va) const;
158 size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc);
159};
160
162{
163 public:
164 struct Entry
165 {
166 bool valid;
167 mutable uint32_t lastUsed;
168
169 // TAGS
172 uint16_t asid;
173 uint16_t vmid;
174
175 // OUTPUTS
177 uint8_t permissions;
178 };
179
180 ARMArchTLB(unsigned numEntries, unsigned _associativity,
181 const std::string &policy, statistics::Group *parent);
182 virtual ~ARMArchTLB() {}
183
184 const Entry *lookup(Addr va, uint16_t asid, uint16_t vmid,
185 bool updStats=true);
186
187 void store(const Entry &incoming);
188
189 void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
190 void invalidateVAA(Addr va, uint16_t vmid);
191 void invalidateASID(uint16_t asid, uint16_t vmid);
192 void invalidateVMID(uint16_t vmid);
193 void invalidateAll();
194
195 private:
198
200
201 size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const;
202 size_t pickEntryIdxToReplace(const Set &set);
203};
204
206{
207 public:
208 struct Entry
209 {
210 bool valid;
211 mutable uint32_t lastUsed;
212
213 // TAGS
216 uint16_t vmid;
217
218 // OUTPUTS
220 uint8_t permissions;
221 };
222
223 IPACache(unsigned numEntries, unsigned _associativity,
224 const std::string &policy, statistics::Group *parent);
225 virtual ~IPACache() {}
226
227 const Entry *lookup(Addr ipa, uint16_t vmid, bool updStats=true);
228 void store(const Entry &incoming);
229
230 void invalidateIPA(Addr ipa, uint16_t vmid);
231 void invalidateIPAA(Addr ipa);
232 void invalidateVMID(uint16_t vmid);
233 void invalidateAll();
234
235 private:
238
240
241 size_t pickSetIdx(Addr ipa, uint16_t vmid) const;
242 size_t pickEntryIdxToReplace(const Set &set);
243};
244
246{
247 public:
248 struct Entry
249 {
250 bool valid;
251 mutable uint32_t lastUsed;
252
253 // TAGS
254 uint32_t sid;
255 uint32_t ssid;
256
257 // OUTPUTS
263 uint16_t asid;
264 uint16_t vmid;
265 uint8_t stage1_tg;
266 uint8_t stage2_tg;
267 uint8_t t0sz;
268 uint8_t s2t0sz;
269 };
270
271 ConfigCache(unsigned numEntries, unsigned _associativity,
272 const std::string &policy, statistics::Group *parent);
273 virtual ~ConfigCache() {}
274
275 const Entry *lookup(uint32_t sid, uint32_t ssid, bool updStats=true);
276 void store(const Entry &incoming);
277
278 void invalidateSSID(uint32_t sid, uint32_t ssid);
279 void invalidateSID(uint32_t sid);
280 void invalidateAll();
281
282 private:
285
287
288 size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
289 size_t pickEntryIdxToReplace(const Set &set);
290};
291
293{
294 public:
295 struct Entry
296 {
297 bool valid;
298 mutable uint32_t lastUsed;
299
300 // TAGS
303 uint16_t asid;
304 uint16_t vmid;
305 unsigned stage;
306 unsigned level;
307
308 // OUTPUTS
309 bool leaf;
311 uint8_t permissions;
312 };
313
314 WalkCache(const std::array<unsigned, 2*WALK_CACHE_LEVELS> &_sizes,
315 unsigned _associativity, const std::string &policy,
316 statistics::Group *parent);
317 virtual ~WalkCache() {}
318
319 const Entry *lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid,
320 unsigned stage, unsigned level, bool updStats=true);
321 void store(const Entry &incoming);
322
323 void invalidateVA(Addr va, uint16_t asid, uint16_t vmid,
324 const bool leaf_only);
325 void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only);
326 void invalidateASID(uint16_t asid, uint16_t vmid);
327 void invalidateVMID(uint16_t vmid);
328 void invalidateAll();
329
330 protected:
349 private:
352
354 std::array<unsigned, 2*WALK_CACHE_LEVELS> sizes;
355 std::array<unsigned, 2*WALK_CACHE_LEVELS> offsets;
356
357 size_t pickSetIdx(Addr va, Addr vaMask,
358 unsigned stage, unsigned level) const;
359
360 size_t pickEntryIdxToReplace(const Set &set,
361 unsigned stage, unsigned level);
362};
363
364} // namespace gem5
365
366#endif /* __DEV_ARM_SMMU_V3_CACHES_HH__ */
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
void invalidateVAA(Addr va, uint16_t vmid)
size_t pickEntryIdxToReplace(const Set &set)
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
void store(const Entry &incoming)
std::vector< Entry > Set
std::vector< Set > sets
size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const
ARMArchTLB(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent)
void invalidateVMID(uint16_t vmid)
void invalidateASID(uint16_t asid, uint16_t vmid)
const Entry * lookup(Addr va, uint16_t asid, uint16_t vmid, bool updStats=true)
size_t pickSetIdx(uint32_t sid, uint32_t ssid) const
void invalidateSID(uint32_t sid)
const Entry * lookup(uint32_t sid, uint32_t ssid, bool updStats=true)
ConfigCache(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent)
void store(const Entry &incoming)
void invalidateSSID(uint32_t sid, uint32_t ssid)
std::vector< Set > sets
size_t pickEntryIdxToReplace(const Set &set)
std::vector< Entry > Set
void store(const Entry &incoming)
const Entry * lookup(Addr ipa, uint16_t vmid, bool updStats=true)
void invalidateIPAA(Addr ipa)
IPACache(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent)
size_t pickSetIdx(Addr ipa, uint16_t vmid) const
size_t pickEntryIdxToReplace(const Set &set)
std::vector< Set > sets
void invalidateVMID(uint16_t vmid)
std::vector< Entry > Set
void invalidateIPA(Addr ipa, uint16_t vmid)
void invalidateSID(uint32_t sid)
std::vector< Set > sets
SMMUTLB(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent, const std::string &name)
const Entry * lookupAnyVA(uint32_t sid, uint32_t ssid, bool updStats=true)
void invalidateVAA(Addr va, uint16_t vmid)
void invalidateASID(uint16_t asid, uint16_t vmid)
void store(const Entry &incoming, AllocPolicy alloc)
const Entry * lookup(uint32_t sid, uint32_t ssid, Addr va, bool updStats=true)
size_t pickSetIdx(uint32_t sid, uint32_t ssid) const
void invalidateVMID(uint16_t vmid)
SMMUTLB(const SMMUTLB &tlb)=delete
std::vector< Entry > Set
size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc)
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
void invalidateSSID(uint32_t sid, uint32_t ssid)
static int decodePolicyName(const std::string &policy_name)
SMMUv3BaseCache(const std::string &policy_name, uint32_t seed, statistics::Group *parent, const std::string &name)
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats baseCacheStats
void store(const Entry &incoming)
const Entry * lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats=true)
void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only)
size_t pickEntryIdxToReplace(const Set &set, unsigned stage, unsigned level)
void invalidateVMID(uint16_t vmid)
void invalidateASID(uint16_t asid, uint16_t vmid)
std::vector< Entry > Set
size_t pickSetIdx(Addr va, Addr vaMask, unsigned stage, unsigned level) const
std::array< unsigned, 2 *WALK_CACHE_LEVELS > sizes
gem5::WalkCache::WalkCacheStats walkCacheStats
std::array< unsigned, 2 *WALK_CACHE_LEVELS > offsets
std::vector< Set > sets
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid, const bool leaf_only)
WalkCache(const std::array< unsigned, 2 *WALK_CACHE_LEVELS > &_sizes, unsigned _associativity, const std::string &policy, statistics::Group *parent)
A formula for statistics that is calculated when printed.
Statistics container.
Definition group.hh:93
This is a simple scalar statistic, like a counter.
A 2-Dimensional vecto of scalar stats.
STL vector class.
Definition stl.hh:37
Bitfield< 12, 11 > set
Bitfield< 8 > va
Bitfield< 59, 56 > tlb
Bitfield< 20 > level
Definition intmessage.hh:51
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
@ SMMU_CACHE_REPL_LRU
@ SMMU_CACHE_REPL_RANDOM
@ SMMU_CACHE_REPL_ROUND_ROBIN
Declaration of Statistics objects.
SMMUv3BaseCacheStats(statistics::Group *parent, const std::string &name)
statistics::Vector2d totalLookupsByStageLevel
statistics::Vector2d totalMissesByStageLevel
WalkCacheStats(statistics::Group *parent)
std::vector< statistics::Formula * > averageMissesByStageLevel
statistics::Vector2d insertionsByStageLevel
std::vector< statistics::Formula * > averageHitRateByStageLevel
std::vector< statistics::Formula * > averageUpdatesByStageLevel
std::vector< statistics::Formula * > averageLookupsByStageLevel
statistics::Vector2d totalUpdatesByStageLevel
const std::string & name()
Definition trace.cc:48

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