gem5  v21.1.0.2
smmu_v3_caches.hh
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37 
38 #ifndef __DEV_ARM_SMMU_V3_CACHES_HH__
39 #define __DEV_ARM_SMMU_V3_CACHES_HH__
40 
41 #include <stdint.h>
42 
43 #include <array>
44 #include <cstddef>
45 #include <string>
46 #include <vector>
47 
48 #include "base/random.hh"
49 #include "base/statistics.hh"
50 #include "base/types.hh"
51 
52 #define WALK_CACHE_LEVELS 4
53 
54 namespace gem5
55 {
56 
57 enum
58 {
62 };
63 
65 {
66  protected:
68  size_t nextToReplace;
70  uint32_t useStamp;
71 
73  {
75  const std::string &name);
76 
79 
82 
85 
87 
90 
91  static int decodePolicyName(const std::string &policy_name);
92 
93  public:
94  SMMUv3BaseCache(const std::string &policy_name, uint32_t seed,
95  statistics::Group *parent, const std::string &name);
96  virtual ~SMMUv3BaseCache() {}
97 };
98 
99 class SMMUTLB : public SMMUv3BaseCache
100 {
101  public:
103  {
107  };
108 
109  struct Entry
110  {
111  bool valid;
113  mutable uint32_t lastUsed;
114 
115  // TAGS
116  uint32_t sid;
117  uint32_t ssid;
120 
121  // EXTRA TAGS
122  uint16_t asid;
123  uint16_t vmid;
124 
125  // OUTPUTS
127  uint8_t permissions;
128  };
129 
130  SMMUTLB(unsigned numEntries, unsigned _associativity,
131  const std::string &policy, statistics::Group *parent,
132  const std::string &name);
133  SMMUTLB(const SMMUTLB& tlb) = delete;
134  virtual ~SMMUTLB() {}
135 
136  const Entry *lookup(uint32_t sid, uint32_t ssid, Addr va,
137  bool updStats=true);
138  const Entry *lookupAnyVA(uint32_t sid, uint32_t ssid,
139  bool updStats=true);
140  void store(const Entry &incoming, AllocPolicy alloc);
141 
142  void invalidateSSID(uint32_t sid, uint32_t ssid);
143  void invalidateSID(uint32_t sid);
144  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
145  void invalidateVAA(Addr va, uint16_t vmid);
146  void invalidateASID(uint16_t asid, uint16_t vmid);
147  void invalidateVMID(uint16_t vmid);
148  void invalidateAll();
149 
150  private:
153 
155 
156  size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
157  size_t pickSetIdx(Addr va) const;
158  size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc);
159 };
160 
162 {
163  public:
164  struct Entry
165  {
166  bool valid;
167  mutable uint32_t lastUsed;
168 
169  // TAGS
172  uint16_t asid;
173  uint16_t vmid;
174 
175  // OUTPUTS
177  uint8_t permissions;
178  };
179 
180  ARMArchTLB(unsigned numEntries, unsigned _associativity,
181  const std::string &policy, statistics::Group *parent);
182  virtual ~ARMArchTLB() {}
183 
184  const Entry *lookup(Addr va, uint16_t asid, uint16_t vmid,
185  bool updStats=true);
186 
187  void store(const Entry &incoming);
188 
189  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
190  void invalidateVAA(Addr va, uint16_t vmid);
191  void invalidateASID(uint16_t asid, uint16_t vmid);
192  void invalidateVMID(uint16_t vmid);
193  void invalidateAll();
194 
195  private:
198 
200 
201  size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const;
202  size_t pickEntryIdxToReplace(const Set &set);
203 };
204 
205 class IPACache : public SMMUv3BaseCache
206 {
207  public:
208  struct Entry
209  {
210  bool valid;
211  mutable uint32_t lastUsed;
212 
213  // TAGS
216  uint16_t vmid;
217 
218  // OUTPUTS
220  uint8_t permissions;
221  };
222 
223  IPACache(unsigned numEntries, unsigned _associativity,
224  const std::string &policy, statistics::Group *parent);
225  virtual ~IPACache() {}
226 
227  const Entry *lookup(Addr ipa, uint16_t vmid, bool updStats=true);
228  void store(const Entry &incoming);
229 
230  void invalidateIPA(Addr ipa, uint16_t vmid);
231  void invalidateIPAA(Addr ipa);
232  void invalidateVMID(uint16_t vmid);
233  void invalidateAll();
234 
235  private:
238 
240 
241  size_t pickSetIdx(Addr ipa, uint16_t vmid) const;
242  size_t pickEntryIdxToReplace(const Set &set);
243 };
244 
246 {
247  public:
248  struct Entry
249  {
250  bool valid;
251  mutable uint32_t lastUsed;
252 
253  // TAGS
254  uint32_t sid;
255  uint32_t ssid;
256 
257  // OUTPUTS
258  bool stage1_en;
259  bool stage2_en;
263  uint16_t asid;
264  uint16_t vmid;
265  uint8_t stage1_tg;
266  uint8_t stage2_tg;
267  uint8_t t0sz;
268  uint8_t s2t0sz;
269  };
270 
271  ConfigCache(unsigned numEntries, unsigned _associativity,
272  const std::string &policy, statistics::Group *parent);
273  virtual ~ConfigCache() {}
274 
275  const Entry *lookup(uint32_t sid, uint32_t ssid, bool updStats=true);
276  void store(const Entry &incoming);
277 
278  void invalidateSSID(uint32_t sid, uint32_t ssid);
279  void invalidateSID(uint32_t sid);
280  void invalidateAll();
281 
282  private:
285 
287 
288  size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
289  size_t pickEntryIdxToReplace(const Set &set);
290 };
291 
293 {
294  public:
295  struct Entry
296  {
297  bool valid;
298  mutable uint32_t lastUsed;
299 
300  // TAGS
303  uint16_t asid;
304  uint16_t vmid;
305  unsigned stage;
306  unsigned level;
307 
308  // OUTPUTS
309  bool leaf;
311  uint8_t permissions;
312  };
313 
314  WalkCache(const std::array<unsigned, 2*WALK_CACHE_LEVELS> &_sizes,
315  unsigned _associativity, const std::string &policy,
316  statistics::Group *parent);
317  virtual ~WalkCache() {}
318 
319  const Entry *lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid,
320  unsigned stage, unsigned level, bool updStats=true);
321  void store(const Entry &incoming);
322 
323  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid,
324  const bool leaf_only);
325  void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only);
326  void invalidateASID(uint16_t asid, uint16_t vmid);
327  void invalidateVMID(uint16_t vmid);
328  void invalidateAll();
329 
330  protected:
332  {
334  ~WalkCacheStats();
335 
338 
341 
344 
346 
348  } walkCacheStats;
349  private:
352 
354  std::array<unsigned, 2*WALK_CACHE_LEVELS> sizes;
355  std::array<unsigned, 2*WALK_CACHE_LEVELS> offsets;
356 
357  size_t pickSetIdx(Addr va, Addr vaMask,
358  unsigned stage, unsigned level) const;
359 
360  size_t pickEntryIdxToReplace(const Set &set,
361  unsigned stage, unsigned level);
362 };
363 
364 } // namespace gem5
365 
366 #endif /* __DEV_ARM_SMMU_V3_CACHES_HH__ */
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:51
gem5::WalkCache::WalkCacheStats::WalkCacheStats
WalkCacheStats(statistics::Group *parent)
Definition: smmu_v3_caches.cc:1232
gem5::ConfigCache::lookup
const Entry * lookup(uint32_t sid, uint32_t ssid, bool updStats=true)
Definition: smmu_v3_caches.cc:843
gem5::ARMArchTLB::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:173
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::averageMisses
statistics::Formula averageMisses
Definition: smmu_v3_caches.hh:80
gem5::SMMUTLB::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:338
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::SMMUv3BaseCacheStats
SMMUv3BaseCacheStats(statistics::Group *parent, const std::string &name)
Definition: smmu_v3_caches.cc:88
gem5::SMMUTLB::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:111
gem5::ConfigCache::Entry::ttb0
Addr ttb0
Definition: smmu_v3_caches.hh:260
gem5::WalkCache::lookup
const Entry * lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats=true)
Definition: smmu_v3_caches.cc:1021
gem5::ArmISA::tlb
Bitfield< 59, 56 > tlb
Definition: misc_types.hh:91
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::averageUpdates
statistics::Formula averageUpdates
Definition: smmu_v3_caches.hh:83
gem5::SMMUTLB::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:353
gem5::SMMUv3BaseCache::~SMMUv3BaseCache
virtual ~SMMUv3BaseCache()
Definition: smmu_v3_caches.hh:96
gem5::IPACache::IPACache
IPACache(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent)
Definition: smmu_v3_caches.cc:633
gem5::WalkCache::offsets
std::array< unsigned, 2 *WALK_CACHE_LEVELS > offsets
Definition: smmu_v3_caches.hh:355
gem5::SMMUTLB::AllocPolicy
AllocPolicy
Definition: smmu_v3_caches.hh:102
gem5::WalkCache::Entry::leaf
bool leaf
Definition: smmu_v3_caches.hh:309
gem5::ConfigCache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:264
gem5::SMMUTLB::Entry::sid
uint32_t sid
Definition: smmu_v3_caches.hh:116
gem5::SMMUTLB::associativity
size_t associativity
Definition: smmu_v3_caches.hh:154
gem5::ARMArchTLB::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:497
gem5::ConfigCache::Entry::stage1_en
bool stage1_en
Definition: smmu_v3_caches.hh:258
gem5::ConfigCache::pickSetIdx
size_t pickSetIdx(uint32_t sid, uint32_t ssid) const
Definition: smmu_v3_caches.cc:934
gem5::WalkCache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:1158
gem5::ARMArchTLB::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:171
gem5::ConfigCache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:875
gem5::WalkCache::WalkCacheStats::totalMissesByStageLevel
statistics::Vector2d totalMissesByStageLevel
Definition: smmu_v3_caches.hh:340
gem5::SMMUTLB::invalidateSID
void invalidateSID(uint32_t sid)
Definition: smmu_v3_caches.cc:279
gem5::SMMUv3BaseCache::SMMUv3BaseCache
SMMUv3BaseCache(const std::string &policy_name, uint32_t seed, statistics::Group *parent, const std::string &name)
Definition: smmu_v3_caches.cc:64
gem5::WalkCache::WalkCache
WalkCache(const std::array< unsigned, 2 *WALK_CACHE_LEVELS > &_sizes, unsigned _associativity, const std::string &policy, statistics::Group *parent)
Definition: smmu_v3_caches.cc:977
gem5::ARMArchTLB::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:197
gem5::SMMU_CACHE_REPL_RANDOM
@ SMMU_CACHE_REPL_RANDOM
Definition: smmu_v3_caches.hh:60
gem5::IPACache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:216
gem5::ConfigCache::Entry::t0sz
uint8_t t0sz
Definition: smmu_v3_caches.hh:267
gem5::ConfigCache::Entry::stage1_tg
uint8_t stage1_tg
Definition: smmu_v3_caches.hh:265
gem5::SMMUTLB::Entry::pa
Addr pa
Definition: smmu_v3_caches.hh:126
gem5::ARMArchTLB::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:167
gem5::SMMUTLB::Entry::ssid
uint32_t ssid
Definition: smmu_v3_caches.hh:117
gem5::ConfigCache::Entry::ssid
uint32_t ssid
Definition: smmu_v3_caches.hh:255
gem5::WalkCache::WalkCacheStats::averageLookupsByStageLevel
std::vector< statistics::Formula * > averageLookupsByStageLevel
Definition: smmu_v3_caches.hh:336
gem5::IPACache::invalidateIPA
void invalidateIPA(Addr ipa, uint16_t vmid)
Definition: smmu_v3_caches.cc:716
gem5::ArmISA::asid
asid
Definition: misc_types.hh:617
gem5::WalkCache::Entry
Definition: smmu_v3_caches.hh:295
gem5::SMMUv3BaseCache::nextToReplace
size_t nextToReplace
Definition: smmu_v3_caches.hh:68
gem5::IPACache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:239
gem5::ConfigCache::Entry::ttb1
Addr ttb1
Definition: smmu_v3_caches.hh:261
gem5::ConfigCache::ConfigCache
ConfigCache(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent)
Definition: smmu_v3_caches.cc:813
gem5::IPACache::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:220
gem5::WalkCache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:304
random.hh
gem5::SMMUv3BaseCache::baseCacheStats
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats baseCacheStats
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::averageHitRate
statistics::Formula averageHitRate
Definition: smmu_v3_caches.hh:86
gem5::statistics::Vector2d
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2055
gem5::ConfigCache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:923
gem5::ARMArchTLB::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:564
gem5::SMMUTLB::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:127
gem5::WalkCache::pickSetIdx
size_t pickSetIdx(Addr va, Addr vaMask, unsigned stage, unsigned level) const
Definition: smmu_v3_caches.cc:1169
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector< Entry >
gem5::SMMUTLB::SMMUTLB
SMMUTLB(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent, const std::string &name)
Definition: smmu_v3_caches.cc:153
gem5::ARMArchTLB::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:166
gem5::ConfigCache::Entry
Definition: smmu_v3_caches.hh:248
gem5::WalkCache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:298
gem5::WalkCache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:350
gem5::ConfigCache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:286
gem5::IPACache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:211
gem5::ConfigCache::Entry::sid
uint32_t sid
Definition: smmu_v3_caches.hh:254
gem5::SMMUTLB::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc)
Definition: smmu_v3_caches.cc:376
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::totalLookups
statistics::Scalar totalLookups
Definition: smmu_v3_caches.hh:78
gem5::SMMUTLB::lookup
const Entry * lookup(uint32_t sid, uint32_t ssid, Addr va, bool updStats=true)
Definition: smmu_v3_caches.cc:184
gem5::SMMUTLB::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:119
gem5::SMMUv3BaseCache
Definition: smmu_v3_caches.hh:64
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::averageLookups
statistics::Formula averageLookups
Definition: smmu_v3_caches.hh:77
gem5::IPACache::invalidateIPAA
void invalidateIPAA(Addr ipa)
Definition: smmu_v3_caches.cc:729
gem5::WalkCache::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:302
gem5::ConfigCache::Entry::stage2_tg
uint8_t stage2_tg
Definition: smmu_v3_caches.hh:266
gem5::SMMUTLB::~SMMUTLB
virtual ~SMMUTLB()
Definition: smmu_v3_caches.hh:134
gem5::ARMArchTLB::pickSetIdx
size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const
Definition: smmu_v3_caches.cc:590
gem5::SMMUTLB
Definition: smmu_v3_caches.hh:99
gem5::ARMArchTLB::ARMArchTLB
ARMArchTLB(unsigned numEntries, unsigned _associativity, const std::string &policy, statistics::Group *parent)
Definition: smmu_v3_caches.cc:434
gem5::IPACache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:759
gem5::IPACache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:237
gem5::WalkCache::WalkCacheStats::insertionsByStageLevel
statistics::Vector2d insertionsByStageLevel
Definition: smmu_v3_caches.hh:347
gem5::ARMArchTLB::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:196
gem5::ARMArchTLB::Entry
Definition: smmu_v3_caches.hh:164
gem5::SMMUTLB::invalidateVA
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:294
gem5::ConfigCache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:284
gem5::ARMArchTLB::Entry::va
Addr va
Definition: smmu_v3_caches.hh:170
gem5::WalkCache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:351
gem5::IPACache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:210
gem5::SMMUTLB::pickSetIdx
size_t pickSetIdx(uint32_t sid, uint32_t ssid) const
Definition: smmu_v3_caches.cc:370
gem5::WalkCache::WalkCacheStats::averageHitRateByStageLevel
std::vector< statistics::Formula * > averageHitRateByStageLevel
Definition: smmu_v3_caches.hh:345
gem5::ConfigCache::Entry::s2t0sz
uint8_t s2t0sz
Definition: smmu_v3_caches.hh:268
gem5::IPACache::~IPACache
virtual ~IPACache()
Definition: smmu_v3_caches.hh:225
gem5::ARMArchTLB::lookup
const Entry * lookup(Addr va, uint16_t asid, uint16_t vmid, bool updStats=true)
Definition: smmu_v3_caches.cc:464
gem5::SMMUTLB::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:113
gem5::IPACache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:776
statistics.hh
gem5::ConfigCache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:251
gem5::IPACache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:696
gem5::SMMUTLB::store
void store(const Entry &incoming, AllocPolicy alloc)
Definition: smmu_v3_caches.cc:245
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats
Definition: smmu_v3_caches.hh:72
gem5::SMMUTLB::Entry::va
Addr va
Definition: smmu_v3_caches.hh:118
gem5::IPACache
Definition: smmu_v3_caches.hh:205
gem5::WalkCache::WalkCacheStats::totalUpdatesByStageLevel
statistics::Vector2d totalUpdatesByStageLevel
Definition: smmu_v3_caches.hh:343
gem5::IPACache::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:744
gem5::ARMArchTLB::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:579
gem5::ConfigCache::~ConfigCache
virtual ~ConfigCache()
Definition: smmu_v3_caches.hh:273
gem5::WalkCache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set, unsigned stage, unsigned level)
Definition: smmu_v3_caches.cc:1197
gem5::SMMUTLB::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:123
gem5::SMMUTLB::Entry::prefetched
bool prefetched
Definition: smmu_v3_caches.hh:112
gem5::ConfigCache::Entry::httb
Addr httb
Definition: smmu_v3_caches.hh:262
gem5::WalkCache::invalidateVA
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid, const bool leaf_only)
Definition: smmu_v3_caches.cc:1091
gem5::WalkCache::WalkCacheStats
Definition: smmu_v3_caches.hh:331
gem5::SMMUv3BaseCache::replacementPolicy
int replacementPolicy
Definition: smmu_v3_caches.hh:67
gem5::WalkCache::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:1128
gem5::SMMUv3BaseCache::useStamp
uint32_t useStamp
Definition: smmu_v3_caches.hh:70
gem5::ARMArchTLB::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:177
gem5::WalkCache::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:311
gem5::auxv::Entry
@ Entry
Definition: aux_vector.hh:78
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::WalkCache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:353
gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::totalUpdates
statistics::Scalar totalUpdates
Definition: smmu_v3_caches.hh:84
gem5::ARMArchTLB::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
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Definition: smmu_v3_caches.cc:895
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Definition: smmu_v3_caches.hh:297
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Definition: smmu_v3_caches.cc:1322
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Definition: smmu_v3_caches.hh:182
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Definition: smmu_v3_caches.hh:250
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Definition: smmu_v3_caches.hh:59
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Definition: smmu_v3_caches.cc:310

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