gem5  v21.1.0.2
smmu_v3.hh
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37 
38 #ifndef __DEV_ARM_SMMU_V3_HH__
39 #define __DEV_ARM_SMMU_V3_HH__
40 
41 #include <list>
42 #include <map>
43 #include <queue>
44 #include <string>
45 #include <vector>
46 
47 #include "base/statistics.hh"
50 #include "dev/arm/smmu_v3_defs.hh"
53 #include "dev/arm/smmu_v3_ports.hh"
54 #include "dev/arm/smmu_v3_proc.hh"
55 #include "dev/arm/smmu_v3_ptops.hh"
56 #include "mem/packet.hh"
57 #include "params/SMMUv3.hh"
58 #include "sim/clocked_object.hh"
59 #include "sim/eventq.hh"
60 
80 namespace gem5
81 {
82 
83 class SMMUTranslationProcess;
84 
85 class SMMUv3 : public ClockedObject
86 {
87  protected:
88 
89  friend class SMMUProcess;
90  friend class SMMUTranslationProcess;
91  friend class SMMUCommandExecProcess;
92  friend class SMMUv3DeviceInterface;
93 
94  const System &system;
96 
100 
101  const bool irqInterfaceEnable;
102 
107 
108  const bool tlbEnable;
109  const bool configCacheEnable;
110  const bool ipaCacheEnable;
111  const bool walkCacheEnable;
113 
115  const unsigned walkCacheS1Levels;
116  const unsigned walkCacheS2Levels;
117  const unsigned requestPortWidth; // in bytes
118 
126 
127  SMMUSemaphore transSem; // max N transactions in SMMU
128  SMMUSemaphore ptwSem; // max N concurrent PTWs
129  SMMUSemaphore cycleSem; // max 1 table walk per cycle
130 
131  // Timing parameters
132  const Cycles tlbLat;
136  const Cycles ipaLat;
138 
139  // Stats
141  {
149  } stats;
150 
152 
154 
157 
158  bool inSecureBlock(uint32_t offs) const;
159 
160  std::queue<SMMUAction> packetsToRetry;
161  std::queue<SMMUAction> packetsTableWalkToRetry;
162 
163 
164  void scheduleDeviceRetries();
165 
169 
170  void processCommands();
172 
173  void processCommand(const SMMUCommand &cmd);
174 
175  const PageTableOps *getPageTableOps(uint8_t trans_granule);
176 
177  public:
178  SMMUv3(const SMMUv3Params &p);
179  virtual ~SMMUv3() {}
180 
181  virtual void init() override;
182 
183  Tick recvAtomic(PacketPtr pkt, PortID id);
184  bool recvTimingReq(PacketPtr pkt, PortID id);
185  bool recvTimingResp(PacketPtr pkt);
186  void recvReqRetry();
187 
189  void tableWalkRecvReqRetry();
190 
193 
194  DrainState drain() override;
195  void serialize(CheckpointOut &cp) const override;
196  void unserialize(CheckpointIn &cp) override;
197 
198  virtual Port &getPort(const std::string &name,
199  PortID id = InvalidPortID) override;
200 };
201 
202 } // namespace gem5
203 
204 #endif /* __DEV_ARM_SMMU_V3_HH__ */
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::SMMUv3::packetsToRetry
std::queue< SMMUAction > packetsToRetry
Definition: smmu_v3.hh:160
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::SMMUv3::walkCache
WalkCache walkCache
Definition: smmu_v3.hh:106
gem5::SMMUv3::ifcSmmuSem
SMMUSemaphore ifcSmmuSem
Definition: smmu_v3.hh:120
gem5::SMMURegs
Definition: smmu_v3_defs.hh:109
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2081
gem5::SMMUv3::getPageTableOps
const PageTableOps * getPageTableOps(uint8_t trans_granule)
Definition: smmu_v3.cc:571
gem5::EventWrapper
Definition: eventq.hh:1084
gem5::SMMUProcess
Definition: smmu_v3_proc.hh:97
gem5::SMMUv3::requestPortWidth
const unsigned requestPortWidth
Definition: smmu_v3.hh:117
gem5::SMMUv3::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: smmu_v3.cc:786
gem5::SMMUv3::transSem
SMMUSemaphore transSem
Definition: smmu_v3.hh:127
gem5::SMMUv3::runProcessTiming
SMMUAction runProcessTiming(SMMUProcess *proc, PacketPtr pkt)
Definition: smmu_v3.cc:286
gem5::SMMUv3::regs
SMMURegs regs
Definition: smmu_v3.hh:156
gem5::SMMUAction
Definition: smmu_v3_proc.hh:70
gem5::SMMUv3::controlPort
SMMUControlPort controlPort
Definition: smmu_v3.hh:99
gem5::SMMUv3::requestorId
const RequestorID requestorId
Definition: smmu_v3.hh:95
gem5::SMMUv3::ipaCacheEnable
const bool ipaCacheEnable
Definition: smmu_v3.hh:110
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SMMUv3::SMMUv3Stats::ptwTimeDist
statistics::Distribution ptwTimeDist
Definition: smmu_v3.hh:148
gem5::SMMUv3::tlbLat
const Cycles tlbLat
Definition: smmu_v3.hh:132
gem5::SMMUv3::walkCacheS1Levels
const unsigned walkCacheS1Levels
Definition: smmu_v3.hh:115
gem5::SMMUv3::ifcSmmuLat
const Cycles ifcSmmuLat
Definition: smmu_v3.hh:133
smmu_v3_cmdexec.hh
gem5::SMMUv3::SMMUv3Stats::cdFetches
statistics::Scalar cdFetches
Definition: smmu_v3.hh:146
gem5::SMMUv3::processCommands
void processCommands()
Definition: smmu_v3.cc:373
std::vector
STL vector class.
Definition: stl.hh:37
gem5::SMMUv3::SMMUv3Stats::steFetches
statistics::Scalar steFetches
Definition: smmu_v3.hh:144
gem5::SMMUv3::writeControl
Tick writeControl(PacketPtr pkt)
Definition: smmu_v3.cc:620
gem5::SMMUv3::recvAtomic
Tick recvAtomic(PacketPtr pkt, PortID id)
smmu_v3_events.hh
gem5::SMMUv3::configSem
SMMUSemaphore configSem
Definition: smmu_v3.hh:122
gem5::SMMUv3::SMMUv3Stats::steL1Fetches
statistics::Scalar steL1Fetches
Definition: smmu_v3.hh:143
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::SMMUv3::requestPort
SMMURequestPort requestPort
Definition: smmu_v3.hh:97
gem5::SMMUv3::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: smmu_v3.cc:804
gem5::SMMUv3::walkCacheEnable
const bool walkCacheEnable
Definition: smmu_v3.hh:111
gem5::SMMUv3::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: smmu_v3.cc:133
gem5::SMMUv3::runProcessAtomic
SMMUAction runProcessAtomic(SMMUProcess *proc, PacketPtr pkt)
Definition: smmu_v3.cc:237
gem5::SMMUv3::SMMUv3
SMMUv3(const SMMUv3Params &p)
Definition: smmu_v3.cc:58
gem5::SMMUv3::walkCacheNonfinalEnable
const bool walkCacheNonfinalEnable
Definition: smmu_v3.hh:114
gem5::SMMUv3::SMMUv3Stats::translationTimeDist
statistics::Distribution translationTimeDist
Definition: smmu_v3.hh:147
gem5::SMMUv3
Definition: smmu_v3.hh:85
packet.hh
gem5::SMMUv3::configCache
ConfigCache configCache
Definition: smmu_v3.hh:104
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::SMMUv3::~SMMUv3
virtual ~SMMUv3()
Definition: smmu_v3.hh:179
gem5::SMMUv3::recvReqRetry
void recvReqRetry()
Definition: smmu_v3.cc:150
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::SMMUv3::regsMap
const AddrRange regsMap
Definition: smmu_v3.hh:155
gem5::System
Definition: system.hh:77
gem5::SMMUv3::cycleSem
SMMUSemaphore cycleSem
Definition: smmu_v3.hh:129
smmu_v3_ports.hh
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::SMMUv3::irqInterfaceEnable
const bool irqInterfaceEnable
Definition: smmu_v3.hh:101
gem5::SMMUv3::tableWalkRecvReqRetry
void tableWalkRecvReqRetry()
Definition: smmu_v3.cc:196
gem5::SMMUv3::requestPortSem
SMMUSemaphore requestPortSem
Definition: smmu_v3.hh:125
gem5::SMMUSemaphore
Definition: smmu_v3_proc.hh:81
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::SMMUv3::ptwSem
SMMUSemaphore ptwSem
Definition: smmu_v3.hh:128
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::SMMUv3::readControl
Tick readControl(PacketPtr pkt)
Definition: smmu_v3.cc:587
gem5::SMMUv3::getPort
virtual Port & getPort(const std::string &name, PortID id=InvalidPortID) override
Get a port with a given name and index.
Definition: smmu_v3.cc:812
gem5::SMMUv3::inSecureBlock
bool inSecureBlock(uint32_t offs) const
Definition: smmu_v3.cc:722
gem5::SMMUv3::processCommand
void processCommand(const SMMUCommand &cmd)
Definition: smmu_v3.cc:389
gem5::SMMUv3::init
virtual void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: smmu_v3.cc:731
smmu_v3_ptops.hh
gem5::SMMUv3::tlbSem
SMMUSemaphore tlbSem
Definition: smmu_v3.hh:119
gem5::SMMUv3::ipaLat
const Cycles ipaLat
Definition: smmu_v3.hh:136
gem5::SMMUv3::walkLat
const Cycles walkLat
Definition: smmu_v3.hh:137
gem5::IPACache
Definition: smmu_v3_caches.hh:205
gem5::SMMUv3::tlbEnable
const bool tlbEnable
Definition: smmu_v3.hh:108
gem5::SMMUv3::smmuIfcSem
SMMUSemaphore smmuIfcSem
Definition: smmu_v3.hh:121
gem5::SMMUControlPort
Definition: smmu_v3_ports.hh:97
gem5::SMMUv3::ipaCache
IPACache ipaCache
Definition: smmu_v3.hh:105
gem5::SMMUv3DeviceInterface
Definition: smmu_v3_deviceifc.hh:58
gem5::SMMUv3::SMMUv3Stats::SMMUv3Stats
SMMUv3Stats(statistics::Group *parent)
Definition: smmu_v3.cc:751
gem5::SMMUv3::tableWalkRecvTimingResp
bool tableWalkRecvTimingResp(PacketPtr pkt)
Definition: smmu_v3.cc:179
smmu_v3_deviceifc.hh
gem5::SMMUv3::smmuIfcLat
const Cycles smmuIfcLat
Definition: smmu_v3.hh:134
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::SMMUv3::SMMUv3Stats
Definition: smmu_v3.hh:140
gem5::SMMUTableWalkPort
Definition: smmu_v3_ports.hh:64
gem5::SMMUv3::processCommandsEvent
EventWrapper< SMMUv3, &SMMUv3::processCommands > processCommandsEvent
Definition: smmu_v3.hh:171
gem5::SMMUv3::system
const System & system
Definition: smmu_v3.hh:94
gem5::SMMUv3::walkCacheS2Levels
const unsigned walkCacheS2Levels
Definition: smmu_v3.hh:116
gem5::SMMUv3::packetsTableWalkToRetry
std::queue< SMMUAction > packetsTableWalkToRetry
Definition: smmu_v3.hh:161
gem5::ConfigCache
Definition: smmu_v3_caches.hh:245
smmu_v3_proc.hh
smmu_v3_caches.hh
gem5::SMMUv3::tableWalkPort
SMMUTableWalkPort tableWalkPort
Definition: smmu_v3.hh:98
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::SMMUv3::ipaSem
SMMUSemaphore ipaSem
Definition: smmu_v3.hh:123
clocked_object.hh
gem5::SMMUCommand
Definition: smmu_v3_defs.hh:359
gem5::WalkCache
Definition: smmu_v3_caches.hh:292
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::SMMUv3::configCacheEnable
const bool configCacheEnable
Definition: smmu_v3.hh:109
gem5::SMMUv3::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: smmu_v3.cc:796
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::SMMUv3::tlb
ARMArchTLB tlb
Definition: smmu_v3.hh:103
gem5::SMMUv3::deviceInterfaces
std::vector< SMMUv3DeviceInterface * > deviceInterfaces
Definition: smmu_v3.hh:151
gem5::SMMUv3::configLat
const Cycles configLat
Definition: smmu_v3.hh:135
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
smmu_v3_defs.hh
gem5::SMMUCommandExecProcess
Definition: smmu_v3_cmdexec.hh:49
gem5::SMMUv3::stats
gem5::SMMUv3::SMMUv3Stats stats
gem5::SMMUv3::recvTimingReq
bool recvTimingReq(PacketPtr pkt, PortID id)
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SMMUv3::scheduleDeviceRetries
void scheduleDeviceRetries()
Definition: smmu_v3.cc:217
gem5::ARMArchTLB
Definition: smmu_v3_caches.hh:161
gem5::SMMUv3::runProcess
SMMUAction runProcess(SMMUProcess *proc, PacketPtr pkt)
Definition: smmu_v3.cc:225
gem5::SMMUv3::tableWalkPortEnable
bool tableWalkPortEnable
Definition: smmu_v3.hh:112
gem5::SMMUv3::SMMUv3Stats::cdL1Fetches
statistics::Scalar cdL1Fetches
Definition: smmu_v3.hh:145
gem5::PageTableOps
Definition: smmu_v3_ptops.hh:48
gem5::SMMUv3::commandExecutor
SMMUCommandExecProcess commandExecutor
Definition: smmu_v3.hh:153
gem5::SMMUv3::walkSem
SMMUSemaphore walkSem
Definition: smmu_v3.hh:124
gem5::SMMUTranslationProcess
Definition: smmu_v3_transl.hh:66
gem5::SMMURequestPort
Definition: smmu_v3_ports.hh:50
eventq.hh

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