gem5  v22.0.0.2
vec_reg.test.cc
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37 
38 #include <gtest/gtest.h>
39 
40 #include "arch/generic/vec_reg.hh"
41 
42 using namespace gem5;
43 
44 TEST(VecReg, Size)
45 {
46  {
47  // Minimum size
49  ASSERT_EQ(1, vec.size());
50  }
51 
52  {
53  // Medium size
54  constexpr size_t size = MaxVecRegLenInBytes / 2;
56  ASSERT_EQ(size, vec.size());
57  }
58 
59  {
60  // Maximum size
62  ASSERT_EQ(MaxVecRegLenInBytes, vec.size());
63  }
64 }
65 
66 TEST(VecReg, Zero)
67 {
68  constexpr size_t size = 16;
70  auto *vec_ptr = vec.as<uint8_t>();
71 
72  // Initializing with non-zero value
73  for (auto idx = 0; idx < size; idx++) {
74  vec_ptr[idx] = 0xAA;
75  }
76 
77  // zeroing the vector
78  vec.zero();
79 
80  // checking if every vector element is set to zero
81  for (auto idx = 0; idx < size; idx++) {
82  ASSERT_EQ(vec_ptr[idx], 0);
83  }
84 }
85 
86 class TwoDifferentVecRegs : public testing::Test
87 {
88  protected:
91  uint8_t *vec1_ptr;
92  uint8_t *vec2_ptr;
93 
94  void
95  SetUp() override
96  {
97  vec1_ptr = vec1.as<uint8_t>();
98  vec2_ptr = vec2.as<uint8_t>();
99 
100  // Initializing with non-zero value vector1
101  for (auto idx = 0; idx < vec1.size(); idx++) {
102  vec1_ptr[idx] = 0xAA;
103  }
104 
105  // Initializing with zero value vector2
106  for (auto idx = 0; idx < vec2.size(); idx++) {
107  vec2_ptr[idx] = 0;
108  }
109  }
110 };
111 
112 // Testing operator=
114 {
115  // Copying the vector
116  vec2 = vec1;
117 
118  // Checking if vector2 elements are 0xAA
119  for (auto idx = 0; idx < vec2.size(); idx++) {
120  ASSERT_EQ(vec2_ptr[idx], 0xAA);
121  }
122 }
123 
124 // Testing operator==
126 {
127  // Equality check
128  ASSERT_TRUE(vec1 == vec1);
129  ASSERT_TRUE(vec2 == vec2);
130  ASSERT_FALSE(vec1 == vec2);
131 }
132 
133 // Testing operator!=
135 {
136  // Inequality check
137  ASSERT_FALSE(vec1 != vec1);
138  ASSERT_FALSE(vec2 != vec2);
139  ASSERT_TRUE(vec1 != vec2);
140 }
141 
142 // Testing operator<<
144 {
145  {
146  std::ostringstream stream;
147  stream << vec1;
148  ASSERT_EQ(stream.str(), "[aaaaaaaa_aaaaaaaa_aaaaaaaa_aaaaaaaa]");
149  }
150 
151  {
152  std::ostringstream stream;
153  stream << vec2;
154  ASSERT_EQ(stream.str(), "[00000000_00000000_00000000_00000000]");
155  }
156 }
157 
158 // Testing ParseParam
160 {
161  ParseParam<decltype(vec1)> parser;
162 
163  parser.parse("bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb", vec1);
164  parser.parse("cccccccccccccccccccccccccccccccc", vec2);
165 
166  for (auto idx = 0; idx < 2; idx++) {
167  ASSERT_EQ(vec1_ptr[idx], 0xbb);
168  ASSERT_EQ(vec2_ptr[idx], 0xcc);
169  }
170 }
171 
172 // Testing ShowParam
174 {
175  ShowParam<decltype(vec1)> parser;
176 
177  {
178  std::stringstream ss;
179  parser.show(ss, vec1);
180  ASSERT_EQ(ss.str(), "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa");
181  }
182 
183  {
184  std::stringstream ss;
185  parser.show(ss, vec2);
186  ASSERT_EQ(ss.str(), "00000000000000000000000000000000");
187  }
188 }
TwoDifferentVecRegs
Definition: vec_reg.test.cc:86
gem5::ShowParam::show
static void show(std::ostream &os, const T &value)
Definition: serialize_handlers.hh:127
gem5::VecRegContainer::size
static constexpr size_t size()
Definition: vec_reg.hh:131
TEST
TEST(VecReg, Size)
Definition: vec_reg.test.cc:44
gem5::ShowParam
Definition: serialize_handlers.hh:125
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::VecRegContainer::as
VecElem * as()
View interposers.
Definition: vec_reg.hh:189
TEST_F
TEST_F(TwoDifferentVecRegs, Assignment)
Definition: vec_reg.test.cc:113
gem5::MaxVecRegLenInBytes
constexpr unsigned MaxVecRegLenInBytes
Definition: vec_reg.hh:113
TwoDifferentVecRegs::vec1_ptr
uint8_t * vec1_ptr
Definition: vec_reg.test.cc:91
ss
std::stringstream ss
Definition: trace.test.cc:45
TwoDifferentVecRegs::vec2
VecRegContainer< 16 > vec2
Definition: vec_reg.test.cc:90
TwoDifferentVecRegs::vec2_ptr
uint8_t * vec2_ptr
Definition: vec_reg.test.cc:92
vec_reg.hh
TwoDifferentVecRegs::SetUp
void SetUp() override
Definition: vec_reg.test.cc:95
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition: misc.hh:108
gem5::ParseParam
Definition: serialize_handlers.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::cc_reg::Zero
constexpr RegId Zero(CCRegClass, _ZeroIdx)
TwoDifferentVecRegs::vec1
VecRegContainer< 16 > vec1
Definition: vec_reg.test.cc:89

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