gem5
v21.2.1.1
arch
power
regs
misc.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2009 The University of Edinburgh
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* Copyright (c) 2021 IBM Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_POWER_MISCREGS_HH__
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#define __ARCH_POWER_MISCREGS_HH__
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#include "
base/bitunion.hh
"
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namespace
gem5
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{
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namespace
PowerISA
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{
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enum
MiscRegIndex
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{
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NUM_MISCREGS
= 0
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};
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const
char
*
const
miscRegName
[
NUM_MISCREGS
] = {
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};
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BitUnion32
(Cr)
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SubBitUnion
(cr0, 31, 28)
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Bitfield<31>
lt
;
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Bitfield<30>
gt
;
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Bitfield<29>
eq
;
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Bitfield<28>
so
;
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EndSubBitUnion
(cr0)
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Bitfield<27,24>
cr1
;
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EndBitUnion
(Cr)
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BitUnion32
(Xer)
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Bitfield<31>
so
;
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Bitfield<30>
ov
;
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Bitfield<29>
ca
;
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Bitfield<19>
ov32
;
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Bitfield<18>
ca32
;
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EndBitUnion
(Xer)
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BitUnion32
(Fpscr)
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Bitfield<31> fx;
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Bitfield<30>
fex
;
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Bitfield<29>
vx
;
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Bitfield<28>
ox
;
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Bitfield<27>
ux
;
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Bitfield<26>
zx
;
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Bitfield<25>
xx
;
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Bitfield<24>
vxsnan
;
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Bitfield<23>
vxisi
;
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Bitfield<22>
vxidi
;
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Bitfield<21>
vxzdz
;
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Bitfield<20>
vximz
;
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Bitfield<19>
vxvc
;
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Bitfield<18>
fr
;
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Bitfield<17>
fi
;
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SubBitUnion
(fprf, 16, 12)
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Bitfield<16>
c
;
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SubBitUnion
(fpcc, 15, 12)
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Bitfield<15> fl;
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Bitfield<14>
fg
;
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Bitfield<13>
fe
;
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Bitfield<12>
fu
;
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EndSubBitUnion
(fpcc)
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EndSubBitUnion
(fprf)
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Bitfield<10> vxsqrt;
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Bitfield<9>
vxcvi
;
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Bitfield<8>
ve
;
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Bitfield<7>
oe
;
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Bitfield<6>
ue
;
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Bitfield<5>
ze
;
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Bitfield<4>
xe
;
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Bitfield<3>
ni
;
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Bitfield<2,1>
rn
;
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EndBitUnion
(Fpscr)
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BitUnion64
(Msr)
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Bitfield<63>
sf
;
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Bitfield<60>
hv
;
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Bitfield<34, 33>
ts
;
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Bitfield<32>
tm
;
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Bitfield<25>
vec
;
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Bitfield<23>
vsx
;
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Bitfield<15>
ee
;
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Bitfield<14>
pr
;
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Bitfield<13>
fp
;
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Bitfield<12>
me
;
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Bitfield<11>
fe0
;
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Bitfield<10, 9>
te
;
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Bitfield<8>
fe1
;
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Bitfield<5>
ir
;
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Bitfield<4>
dr
;
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Bitfield<2>
pmm
;
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Bitfield<1>
ri
;
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Bitfield<0>
le
;
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EndBitUnion
(Msr)
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}
// namespace PowerISA
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}
// namespace gem5
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#endif // __ARCH_POWER_MISCREGS_HH__
gem5::PowerISA::vxidi
Bitfield< 22 > vxidi
Definition:
misc.hh:77
gem5::PowerISA::EndSubBitUnion
EndSubBitUnion(cr0) Bitfield< 27
gem5::PowerISA::xe
Bitfield< 4 > xe
Definition:
misc.hh:98
gem5::PowerISA::xx
Bitfield< 25 > xx
Definition:
misc.hh:74
gem5::PowerISA::vxvc
Bitfield< 19 > vxvc
Definition:
misc.hh:80
gem5::PowerISA::vsx
Bitfield< 23 > vsx
Definition:
misc.hh:109
gem5::PowerISA::ca
Bitfield< 29 > ca
Definition:
misc.hh:62
gem5::PowerISA::ov
Bitfield< 30 > ov
Definition:
misc.hh:61
gem5::PowerISA::fe
Bitfield< 13 > fe
Definition:
misc.hh:88
gem5::PowerISA::pmm
Bitfield< 2 > pmm
Definition:
misc.hh:119
gem5::PowerISA::fg
Bitfield< 14 > fg
Definition:
misc.hh:87
gem5::PowerISA::vxisi
Bitfield< 23 > vxisi
Definition:
misc.hh:76
gem5::PowerISA::vx
Bitfield< 29 > vx
Definition:
misc.hh:70
gem5::PowerISA::rn
Bitfield< 2, 1 > rn
Definition:
misc.hh:100
gem5::PowerISA::vxzdz
Bitfield< 21 > vxzdz
Definition:
misc.hh:78
gem5::PowerISA::me
Bitfield< 12 > me
Definition:
misc.hh:113
gem5::PowerISA::le
Bitfield< 0 > le
Definition:
misc.hh:121
gem5::PowerISA::ca32
Bitfield< 18 > ca32
Definition:
misc.hh:64
gem5::X86ISA::c
Bitfield< 42 > c
Definition:
misc.hh:939
gem5::PowerISA::vxsnan
Bitfield< 24 > vxsnan
Definition:
misc.hh:75
BitUnion64
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
Definition:
bitunion.hh:494
gem5::PowerISA::fu
Bitfield< 12 > fu
Definition:
misc.hh:89
gem5::PowerISA::fr
Bitfield< 18 > fr
Definition:
misc.hh:81
gem5::PowerISA::ri
Bitfield< 1 > ri
Definition:
misc.hh:120
gem5::PowerISA::ze
Bitfield< 5 > ze
Definition:
misc.hh:97
gem5::PowerISA::fp
Bitfield< 13 > fp
Definition:
misc.hh:112
gem5::PowerISA::oe
Bitfield< 7 > oe
Definition:
misc.hh:95
gem5::PowerISA::ov32
Bitfield< 19 > ov32
Definition:
misc.hh:63
bitunion.hh
gem5::PowerISA::ts
Bitfield< 34, 33 > ts
Definition:
misc.hh:106
gem5::PowerISA::ue
Bitfield< 6 > ue
Definition:
misc.hh:96
gem5::PowerISA::zx
Bitfield< 26 > zx
Definition:
misc.hh:73
gem5::PowerISA::MiscRegIndex
MiscRegIndex
Definition:
misc.hh:41
gem5::PowerISA::tm
Bitfield< 32 > tm
Definition:
misc.hh:107
gem5::PowerISA::ni
Bitfield< 3 > ni
Definition:
misc.hh:99
gem5::PowerISA::vximz
Bitfield< 20 > vximz
Definition:
misc.hh:79
gem5::PowerISA::so
Bitfield< 28 > so
Definition:
misc.hh:54
gem5::PowerISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition:
misc.hh:43
gem5::PowerISA::ve
Bitfield< 8 > ve
Definition:
misc.hh:94
gem5::PowerISA::cr1
cr1
Definition:
misc.hh:56
gem5::PowerISA::ir
Bitfield< 5 > ir
Definition:
misc.hh:117
gem5::PowerISA::gt
Bitfield< 30 > gt
Definition:
misc.hh:52
gem5::PowerISA::SubBitUnion
SubBitUnion(fprf, 16, 12) Bitfield< 16 > c
gem5::PowerISA::fe1
Bitfield< 8 > fe1
Definition:
misc.hh:116
gem5::PowerISA::fe0
Bitfield< 11 > fe0
Definition:
misc.hh:114
gem5::PowerISA::eq
Bitfield< 29 > eq
Definition:
misc.hh:53
gem5::PowerISA::hv
Bitfield< 60 > hv
Definition:
misc.hh:105
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition:
misc.hh:108
gem5::PowerISA::EndBitUnion
EndBitUnion(Cr) BitUnion32(Xer) Bitfield< 31 > so
gem5::PowerISA::lt
Bitfield< 31 > lt
Definition:
misc.hh:50
gem5::PowerISA::fex
Bitfield< 30 > fex
Definition:
misc.hh:69
gem5::PowerISA::te
Bitfield< 10, 9 > te
Definition:
misc.hh:115
gem5::PowerISA::dr
Bitfield< 4 > dr
Definition:
misc.hh:118
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
tlb.cc:60
gem5::PowerISA::BitUnion32
BitUnion32(Cr) SubBitUnion(cr0
gem5::PowerISA::ox
Bitfield< 28 > ox
Definition:
misc.hh:71
gem5::X86ISA::sf
Bitfield< 7 > sf
Definition:
misc.hh:551
gem5::PowerISA::pr
Bitfield< 14 > pr
Definition:
misc.hh:111
gem5::PowerISA::vxcvi
Bitfield< 9 > vxcvi
Definition:
misc.hh:93
gem5::PowerISA::ux
Bitfield< 27 > ux
Definition:
misc.hh:72
gem5::PowerISA::fi
Bitfield< 17 > fi
Definition:
misc.hh:82
gem5::PowerISA::ee
Bitfield< 15 > ee
Definition:
misc.hh:110
gem5::PowerISA::miscRegName
const char *const miscRegName[NUM_MISCREGS]
Definition:
misc.hh:46
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