gem5  v21.1.0.2
misc.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2009 The University of Edinburgh
3  * Copyright (c) 2021 IBM Corporation
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_POWER_MISCREGS_HH__
31 #define __ARCH_POWER_MISCREGS_HH__
32 
33 #include "base/bitunion.hh"
34 
35 namespace gem5
36 {
37 
38 namespace PowerISA
39 {
40 
42 {
44 };
45 
46 const char * const miscRegName[NUM_MISCREGS] = {
47 };
48 
49 BitUnion32(Cr)
50  SubBitUnion(cr0, 31, 28)
51  Bitfield<31> lt;
52  Bitfield<30> gt;
53  Bitfield<29> eq;
54  Bitfield<28> so;
55  EndSubBitUnion(cr0)
56  Bitfield<27,24> cr1;
57 EndBitUnion(Cr)
58 
59 BitUnion32(Xer)
60  Bitfield<31> so;
61  Bitfield<30> ov;
62  Bitfield<29> ca;
63  Bitfield<19> ov32;
64  Bitfield<18> ca32;
65 EndBitUnion(Xer)
66 
67 BitUnion32(Fpscr)
68  Bitfield<31> fx;
69  Bitfield<30> fex;
70  Bitfield<29> vx;
71  Bitfield<28> ox;
72  Bitfield<27> ux;
73  Bitfield<26> zx;
74  Bitfield<25> xx;
75  Bitfield<24> vxsnan;
76  Bitfield<23> vxisi;
77  Bitfield<22> vxidi;
78  Bitfield<21> vxzdz;
79  Bitfield<20> vximz;
80  Bitfield<19> vxvc;
81  Bitfield<18> fr;
82  Bitfield<17> fi;
83  SubBitUnion(fprf, 16, 12)
84  Bitfield<16> c;
85  SubBitUnion(fpcc, 15, 12)
86  Bitfield<15> fl;
87  Bitfield<14> fg;
88  Bitfield<13> fe;
89  Bitfield<12> fu;
90  EndSubBitUnion(fpcc)
91  EndSubBitUnion(fprf)
92  Bitfield<10> vxsqrt;
93  Bitfield<9> vxcvi;
94  Bitfield<8> ve;
95  Bitfield<7> oe;
96  Bitfield<6> ue;
97  Bitfield<5> ze;
98  Bitfield<4> xe;
99  Bitfield<3> ni;
100  Bitfield<2,1> rn;
101 EndBitUnion(Fpscr)
102 
103 BitUnion64(Msr)
104  Bitfield<63> sf;
105  Bitfield<60> hv;
106  Bitfield<34, 33> ts;
107  Bitfield<32> tm;
108  Bitfield<25> vec;
109  Bitfield<23> vsx;
110  Bitfield<15> ee;
111  Bitfield<14> pr;
112  Bitfield<13> fp;
113  Bitfield<12> me;
114  Bitfield<11> fe0;
115  Bitfield<10, 9> te;
116  Bitfield<8> fe1;
117  Bitfield<5> ir;
118  Bitfield<4> dr;
119  Bitfield<2> pmm;
120  Bitfield<1> ri;
121  Bitfield<0> le;
122 EndBitUnion(Msr)
123 
124 } // namespace PowerISA
125 } // namespace gem5
126 
127 #endif // __ARCH_POWER_MISCREGS_HH__
gem5::PowerISA::vxidi
Bitfield< 22 > vxidi
Definition: misc.hh:77
gem5::PowerISA::EndSubBitUnion
EndSubBitUnion(cr0) Bitfield< 27
gem5::PowerISA::xe
Bitfield< 4 > xe
Definition: misc.hh:98
gem5::PowerISA::xx
Bitfield< 25 > xx
Definition: misc.hh:74
gem5::PowerISA::vxvc
Bitfield< 19 > vxvc
Definition: misc.hh:80
gem5::PowerISA::vsx
Bitfield< 23 > vsx
Definition: misc.hh:109
gem5::PowerISA::ca
Bitfield< 29 > ca
Definition: misc.hh:62
gem5::PowerISA::ov
Bitfield< 30 > ov
Definition: misc.hh:61
gem5::PowerISA::fe
Bitfield< 13 > fe
Definition: misc.hh:88
gem5::PowerISA::pmm
Bitfield< 2 > pmm
Definition: misc.hh:119
gem5::PowerISA::fg
Bitfield< 14 > fg
Definition: misc.hh:87
gem5::PowerISA::vxisi
Bitfield< 23 > vxisi
Definition: misc.hh:76
gem5::PowerISA::vx
Bitfield< 29 > vx
Definition: misc.hh:70
gem5::PowerISA::rn
Bitfield< 2, 1 > rn
Definition: misc.hh:100
gem5::PowerISA::vxzdz
Bitfield< 21 > vxzdz
Definition: misc.hh:78
gem5::PowerISA::me
Bitfield< 12 > me
Definition: misc.hh:113
gem5::PowerISA::le
Bitfield< 0 > le
Definition: misc.hh:121
gem5::PowerISA::ca32
Bitfield< 18 > ca32
Definition: misc.hh:64
gem5::X86ISA::c
Bitfield< 42 > c
Definition: misc.hh:939
gem5::PowerISA::vxsnan
Bitfield< 24 > vxsnan
Definition: misc.hh:75
BitUnion64
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
Definition: bitunion.hh:495
gem5::PowerISA::fu
Bitfield< 12 > fu
Definition: misc.hh:89
gem5::PowerISA::fr
Bitfield< 18 > fr
Definition: misc.hh:81
gem5::PowerISA::ri
Bitfield< 1 > ri
Definition: misc.hh:120
gem5::PowerISA::ze
Bitfield< 5 > ze
Definition: misc.hh:97
gem5::PowerISA::fp
Bitfield< 13 > fp
Definition: misc.hh:112
gem5::PowerISA::oe
Bitfield< 7 > oe
Definition: misc.hh:95
gem5::PowerISA::ov32
Bitfield< 19 > ov32
Definition: misc.hh:63
bitunion.hh
gem5::PowerISA::ts
Bitfield< 34, 33 > ts
Definition: misc.hh:106
gem5::PowerISA::ue
Bitfield< 6 > ue
Definition: misc.hh:96
gem5::PowerISA::zx
Bitfield< 26 > zx
Definition: misc.hh:73
gem5::PowerISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:41
gem5::PowerISA::tm
Bitfield< 32 > tm
Definition: misc.hh:107
gem5::PowerISA::ni
Bitfield< 3 > ni
Definition: misc.hh:99
gem5::PowerISA::vximz
Bitfield< 20 > vximz
Definition: misc.hh:79
gem5::PowerISA::so
Bitfield< 28 > so
Definition: misc.hh:54
gem5::PowerISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:43
gem5::PowerISA::ve
Bitfield< 8 > ve
Definition: misc.hh:94
gem5::PowerISA::cr1
cr1
Definition: misc.hh:56
gem5::PowerISA::ir
Bitfield< 5 > ir
Definition: misc.hh:117
gem5::PowerISA::gt
Bitfield< 30 > gt
Definition: misc.hh:52
gem5::PowerISA::SubBitUnion
SubBitUnion(fprf, 16, 12) Bitfield< 16 > c
gem5::PowerISA::fe1
Bitfield< 8 > fe1
Definition: misc.hh:116
gem5::PowerISA::fe0
Bitfield< 11 > fe0
Definition: misc.hh:114
gem5::PowerISA::eq
Bitfield< 29 > eq
Definition: misc.hh:53
gem5::PowerISA::hv
Bitfield< 60 > hv
Definition: misc.hh:105
gem5::PowerISA::vec
Bitfield< 25 > vec
Definition: misc.hh:108
gem5::PowerISA::EndBitUnion
EndBitUnion(Cr) BitUnion32(Xer) Bitfield< 31 > so
gem5::PowerISA::lt
Bitfield< 31 > lt
Definition: misc.hh:50
gem5::PowerISA::fex
Bitfield< 30 > fex
Definition: misc.hh:69
gem5::PowerISA::te
Bitfield< 10, 9 > te
Definition: misc.hh:115
gem5::PowerISA::dr
Bitfield< 4 > dr
Definition: misc.hh:118
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::BitUnion32
BitUnion32(Cr) SubBitUnion(cr0
gem5::PowerISA::ox
Bitfield< 28 > ox
Definition: misc.hh:71
gem5::X86ISA::sf
Bitfield< 7 > sf
Definition: misc.hh:551
gem5::PowerISA::pr
Bitfield< 14 > pr
Definition: misc.hh:111
gem5::PowerISA::vxcvi
Bitfield< 9 > vxcvi
Definition: misc.hh:93
gem5::PowerISA::ux
Bitfield< 27 > ux
Definition: misc.hh:72
gem5::PowerISA::fi
Bitfield< 17 > fi
Definition: misc.hh:82
gem5::PowerISA::ee
Bitfield< 15 > ee
Definition: misc.hh:110
gem5::PowerISA::miscRegName
const char *const miscRegName[NUM_MISCREGS]
Definition: misc.hh:46

Generated on Tue Sep 21 2021 12:24:35 for gem5 by doxygen 1.8.17