gem5  v22.1.0.0
misc.hh
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29 
30 #ifndef __ARCH_POWER_MISCREGS_HH__
31 #define __ARCH_POWER_MISCREGS_HH__
32 
33 #include "base/bitunion.hh"
34 #include "cpu/reg_class.hh"
35 #include "debug/MiscRegs.hh"
36 
37 namespace gem5
38 {
39 
40 namespace PowerISA
41 {
42 
44 {
45  NUM_MISCREGS = 0
46 };
47 
48 const char * const miscRegName[NUM_MISCREGS] = {
49 };
50 
52  NUM_MISCREGS, debug::MiscRegs);
53 
55  SubBitUnion(cr0, 31, 28)
56  Bitfield<31> lt;
57  Bitfield<30> gt;
58  Bitfield<29> eq;
59  Bitfield<28> so;
61  Bitfield<27,24> cr1;
63 
65  Bitfield<31> so;
66  Bitfield<30> ov;
67  Bitfield<29> ca;
68  Bitfield<19> ov32;
69  Bitfield<18> ca32;
71 
73  Bitfield<31> fx;
74  Bitfield<30> fex;
75  Bitfield<29> vx;
76  Bitfield<28> ox;
77  Bitfield<27> ux;
78  Bitfield<26> zx;
79  Bitfield<25> xx;
80  Bitfield<24> vxsnan;
81  Bitfield<23> vxisi;
82  Bitfield<22> vxidi;
83  Bitfield<21> vxzdz;
84  Bitfield<20> vximz;
85  Bitfield<19> vxvc;
86  Bitfield<18> fr;
87  Bitfield<17> fi;
88  SubBitUnion(fprf, 16, 12)
89  Bitfield<16> c;
90  SubBitUnion(fpcc, 15, 12)
91  Bitfield<15> fl;
92  Bitfield<14> fg;
93  Bitfield<13> fe;
94  Bitfield<12> fu;
96  EndSubBitUnion(fprf)
97  Bitfield<10> vxsqrt;
98  Bitfield<9> vxcvi;
99  Bitfield<8> ve;
100  Bitfield<7> oe;
101  Bitfield<6> ue;
102  Bitfield<5> ze;
103  Bitfield<4> xe;
104  Bitfield<3> ni;
105  Bitfield<2,1> rn;
107 
109  Bitfield<63> sf;
110  Bitfield<60> hv;
111  Bitfield<34, 33> ts;
112  Bitfield<32> tm;
113  Bitfield<25> vec;
114  Bitfield<23> vsx;
115  Bitfield<15> ee;
116  Bitfield<14> pr;
117  Bitfield<13> fp;
118  Bitfield<12> me;
119  Bitfield<11> fe0;
120  Bitfield<10, 9> te;
121  Bitfield<8> fe1;
122  Bitfield<5> ir;
123  Bitfield<4> dr;
124  Bitfield<2> pmm;
125  Bitfield<1> ri;
126  Bitfield<0> le;
128 
129 } // namespace PowerISA
130 } // namespace gem5
131 
132 #endif // __ARCH_POWER_MISCREGS_HH__
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
Definition: bitunion.hh:494
constexpr RegId Msr
Definition: int.hh:144
constexpr RegId Xer
Definition: int.hh:139
constexpr RegId Cr
Definition: int.hh:138
constexpr RegId Fpscr
Definition: int.hh:143
Bitfield< 34, 33 > ts
Definition: misc.hh:111
Bitfield< 5 > ze
Definition: misc.hh:102
Bitfield< 18 > ca32
Definition: misc.hh:69
Bitfield< 29 > ca
Definition: misc.hh:67
Bitfield< 13 > fp
Definition: misc.hh:117
Bitfield< 6 > ue
Definition: misc.hh:101
Bitfield< 27 > ux
Definition: misc.hh:77
Bitfield< 14 > fg
Definition: misc.hh:92
Bitfield< 28 > so
Definition: misc.hh:59
const char *const miscRegName[NUM_MISCREGS]
Definition: misc.hh:48
Bitfield< 10, 9 > te
Definition: misc.hh:120
Bitfield< 3 > ni
Definition: misc.hh:104
Bitfield< 11 > fe0
Definition: misc.hh:119
Bitfield< 13 > fe
Definition: misc.hh:93
Bitfield< 8 > ve
Definition: misc.hh:99
Bitfield< 12 > fu
Definition: misc.hh:94
Bitfield< 26 > zx
Definition: misc.hh:78
BitUnion32(Cr) SubBitUnion(cr0
@ NUM_MISCREGS
Definition: misc.hh:45
Bitfield< 4 > dr
Definition: misc.hh:123
Bitfield< 30 > gt
Definition: misc.hh:57
Bitfield< 7 > oe
Definition: misc.hh:100
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs)
Bitfield< 0 > le
Definition: misc.hh:126
SubBitUnion(fprf, 16, 12) Bitfield< 16 > c
Bitfield< 5 > ir
Definition: misc.hh:122
Bitfield< 14 > pr
Definition: misc.hh:116
Bitfield< 18 > fr
Definition: misc.hh:86
Bitfield< 24 > vxsnan
Definition: misc.hh:80
Bitfield< 17 > fi
Definition: misc.hh:87
Bitfield< 30 > ov
Definition: misc.hh:66
Bitfield< 29 > vx
Definition: misc.hh:75
Bitfield< 19 > vxvc
Definition: misc.hh:85
Bitfield< 21 > vxzdz
Definition: misc.hh:83
Bitfield< 30 > fex
Definition: misc.hh:74
Bitfield< 4 > xe
Definition: misc.hh:103
EndBitUnion(Cr) BitUnion32(Xer) Bitfield< 31 > so
Bitfield< 1 > ri
Definition: misc.hh:125
Bitfield< 2 > pmm
Definition: misc.hh:124
Bitfield< 22 > vxidi
Definition: misc.hh:82
EndSubBitUnion(cr0) Bitfield< 27
Bitfield< 60 > hv
Definition: misc.hh:110
Bitfield< 15 > ee
Definition: misc.hh:115
Bitfield< 25 > xx
Definition: misc.hh:79
Bitfield< 25 > vec
Definition: misc.hh:113
Bitfield< 2, 1 > rn
Definition: misc.hh:105
Bitfield< 23 > vsx
Definition: misc.hh:114
Bitfield< 29 > eq
Definition: misc.hh:58
Bitfield< 19 > ov32
Definition: misc.hh:68
Bitfield< 28 > ox
Definition: misc.hh:76
Bitfield< 9 > vxcvi
Definition: misc.hh:98
Bitfield< 31 > lt
Definition: misc.hh:55
Bitfield< 20 > vximz
Definition: misc.hh:84
Bitfield< 23 > vxisi
Definition: misc.hh:81
Bitfield< 32 > tm
Definition: misc.hh:112
Bitfield< 8 > fe1
Definition: misc.hh:121
Bitfield< 12 > me
Definition: misc.hh:118
Bitfield< 7 > sf
Definition: misc.hh:550
Bitfield< 42 > c
Definition: misc.hh:940
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
constexpr char MiscRegClassName[]
Definition: reg_class.hh:79
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:68

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