gem5  v21.1.0.2
registers.cc
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33 
35 
36 namespace gem5
37 {
38 
39 namespace VegaISA
40 {
41  std::string
42  opSelectorToRegSym(int idx, int numRegs)
43  {
44  std::string reg_sym;
45 
46  // we have an SGPR
47  if (idx <= REG_SGPR_MAX) {
48  if (numRegs > 1)
49  reg_sym = "s[" + std::to_string(idx) + ":" +
50  std::to_string(idx + numRegs - 1) + "]";
51  else
52  reg_sym = "s" + std::to_string(idx);
53  return reg_sym;
54  } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
55  if (numRegs > 1)
56  reg_sym = "v[" + std::to_string(idx - REG_VGPR_MIN) + ":" +
57  std::to_string(idx - REG_VGPR_MIN + numRegs - 1) + "]";
58  else
59  reg_sym = "v" + std::to_string(idx - REG_VGPR_MIN);
60  return reg_sym;
61  } else if (idx >= REG_INT_CONST_POS_MIN &&
62  idx <= REG_INT_CONST_POS_MAX) {
63  reg_sym = std::to_string(idx - REG_INT_CONST_POS_MIN + 1);
64  return reg_sym;
65  } else if (idx >= REG_INT_CONST_NEG_MIN &&
66  idx <= REG_INT_CONST_NEG_MAX) {
67  int inline_val = -1 - (idx - REG_INT_CONST_NEG_MIN);
68  reg_sym = std::to_string(inline_val);
69  return reg_sym;
70  }
71 
72  switch (idx) {
74  reg_sym = "flat_scratch_lo";
75  break;
77  reg_sym = "flat_scratch_hi";
78  break;
79  case REG_VCC_LO:
80  reg_sym = "vcc";
81  break;
82  case REG_M0:
83  reg_sym = "m0";
84  break;
85  case REG_EXEC_LO:
86  reg_sym = "exec";
87  break;
88  case REG_ZERO:
89  reg_sym = "0";
90  break;
91  case REG_POS_HALF:
92  reg_sym = "0.5";
93  break;
94  case REG_NEG_HALF:
95  reg_sym = "-0.5";
96  break;
97  case REG_POS_ONE:
98  reg_sym = "1";
99  break;
100  case REG_NEG_ONE:
101  reg_sym = "-1";
102  break;
103  case REG_POS_TWO:
104  reg_sym = "2";
105  break;
106  case REG_NEG_TWO:
107  reg_sym = "-2";
108  break;
109  case REG_POS_FOUR:
110  reg_sym = "4";
111  break;
112  case REG_NEG_FOUR:
113  reg_sym = "-4";
114  break;
115  default:
116  fatal("VEGA ISA instruction has unknown register index %u\n", idx);
117  break;
118  }
119 
120  return reg_sym;
121  }
122 
123  int
124  opSelectorToRegIdx(int idx, int numScalarRegs)
125  {
126  int regIdx = -1;
127 
128  if (idx <= REG_SGPR_MAX) {
129  regIdx = idx;
130  } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
131  regIdx = idx - REG_VGPR_MIN;
132  } else if (idx == REG_VCC_LO) {
144  regIdx = numScalarRegs - 2;
145  } else if (idx == REG_VCC_HI) {
146  regIdx = numScalarRegs - 1;
147  } else if (idx == REG_FLAT_SCRATCH_LO) {
160  regIdx = numScalarRegs - 4;
161  } else if (idx == REG_FLAT_SCRATCH_HI) {
162  regIdx = numScalarRegs - 3;
163  } else if (idx == REG_EXEC_LO || idx == REG_EXEC_HI) {
171  return idx;
172  }
173 
174  return regIdx;
175  }
176 
177  bool
178  isPosConstVal(int opIdx)
179  {
180  bool is_pos_const_val = (opIdx >= REG_INT_CONST_POS_MIN
181  && opIdx <= REG_INT_CONST_POS_MAX);
182 
183  return is_pos_const_val;
184  }
185 
186  bool
187  isNegConstVal(int opIdx)
188  {
189  bool is_neg_const_val = (opIdx >= REG_INT_CONST_NEG_MIN
190  && opIdx <= REG_INT_CONST_NEG_MAX);
191 
192  return is_neg_const_val;
193  }
194 
195  bool
196  isConstVal(int opIdx)
197  {
198  bool is_const_val = isPosConstVal(opIdx) || isNegConstVal(opIdx);
199  return is_const_val;
200  }
201 
202  bool
203  isLiteral(int opIdx)
204  {
205  return opIdx == REG_SRC_LITERAL;
206  }
207 
208  bool
209  isExecMask(int opIdx)
210  {
211  return opIdx == REG_EXEC_LO || opIdx == REG_EXEC_HI;
212  }
213 
214  bool
215  isVccReg(int opIdx)
216  {
217  return opIdx == REG_VCC_LO || opIdx == REG_VCC_HI;
218  }
219 
220  bool
221  isFlatScratchReg(int opIdx)
222  {
223  return opIdx == REG_FLAT_SCRATCH_LO || opIdx == REG_FLAT_SCRATCH_HI;
224  }
225 
226  bool
227  isScalarReg(int opIdx)
228  {
229  // FLAT_SCRATCH and VCC are stored in an SGPR pair
230  if (opIdx <= REG_SGPR_MAX || opIdx == REG_FLAT_SCRATCH_LO ||
231  opIdx == REG_FLAT_SCRATCH_HI || opIdx == REG_VCC_LO ||
232  opIdx == REG_VCC_HI) {
233  return true;
234  }
235 
236  return false;
237  }
238 
239  bool
240  isVectorReg(int opIdx)
241  {
242  if (opIdx >= REG_VGPR_MIN && opIdx <= REG_VGPR_MAX)
243  return true;
244 
245  return false;
246  }
247 
248 } // namespace VegaISA
249 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::VegaISA::opSelectorToRegSym
std::string opSelectorToRegSym(int opIdx, int numRegs=0)
Definition: registers.cc:42
gem5::VegaISA::REG_POS_FOUR
@ REG_POS_FOUR
Definition: gpu_registers.hh:122
gem5::VegaISA::isNegConstVal
bool isNegConstVal(int opIdx)
Definition: registers.cc:187
gem5::VegaISA::REG_M0
@ REG_M0
Definition: gpu_registers.hh:76
gem5::VegaISA::REG_FLAT_SCRATCH_LO
@ REG_FLAT_SCRATCH_LO
Definition: gpu_registers.hh:54
gem5::VegaISA::REG_FLAT_SCRATCH_HI
@ REG_FLAT_SCRATCH_HI
Definition: gpu_registers.hh:55
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::VegaISA::REG_VGPR_MAX
@ REG_VGPR_MAX
Definition: gpu_registers.hh:134
gem5::VegaISA::REG_VCC_LO
@ REG_VCC_LO
Definition: gpu_registers.hh:58
gem5::VegaISA::isVccReg
bool isVccReg(int opIdx)
Definition: registers.cc:215
gem5::VegaISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:196
gem5::VegaISA::REG_VGPR_MIN
@ REG_VGPR_MIN
Definition: gpu_registers.hh:133
gem5::VegaISA::isLiteral
bool isLiteral(int opIdx)
Definition: registers.cc:203
gem5::VegaISA::REG_NEG_FOUR
@ REG_NEG_FOUR
Definition: gpu_registers.hh:123
gem5::VegaISA::REG_SGPR_MAX
@ REG_SGPR_MAX
Definition: gpu_registers.hh:53
gem5::VegaISA::REG_INT_CONST_NEG_MIN
@ REG_INT_CONST_NEG_MIN
Definition: gpu_registers.hh:83
gem5::VegaISA::REG_POS_TWO
@ REG_POS_TWO
Definition: gpu_registers.hh:120
gem5::VegaISA::REG_ZERO
@ REG_ZERO
Definition: gpu_registers.hh:80
gem5::VegaISA::REG_VCC_HI
@ REG_VCC_HI
Definition: gpu_registers.hh:59
gem5::VegaISA::opSelectorToRegIdx
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:124
gem5::VegaISA::isScalarReg
bool isScalarReg(int opIdx)
Definition: registers.cc:227
gem5::VegaISA::isPosConstVal
bool isPosConstVal(int opIdx)
Definition: registers.cc:178
gem5::VegaISA::REG_POS_ONE
@ REG_POS_ONE
Definition: gpu_registers.hh:118
gem5::VegaISA::REG_INT_CONST_POS_MIN
@ REG_INT_CONST_POS_MIN
Definition: gpu_registers.hh:81
gem5::VegaISA::REG_NEG_ONE
@ REG_NEG_ONE
Definition: gpu_registers.hh:119
gem5::VegaISA::REG_SRC_LITERAL
@ REG_SRC_LITERAL
Definition: gpu_registers.hh:132
gpu_registers.hh
gem5::VegaISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:209
gem5::VegaISA::isVectorReg
bool isVectorReg(int opIdx)
Definition: registers.cc:240
gem5::VegaISA::REG_EXEC_HI
@ REG_EXEC_HI
Definition: gpu_registers.hh:79
gem5::VegaISA::REG_NEG_HALF
@ REG_NEG_HALF
Definition: gpu_registers.hh:117
gem5::VegaISA::REG_NEG_TWO
@ REG_NEG_TWO
Definition: gpu_registers.hh:121
gem5::VegaISA::REG_POS_HALF
@ REG_POS_HALF
Definition: gpu_registers.hh:116
gem5::VegaISA::REG_INT_CONST_NEG_MAX
@ REG_INT_CONST_NEG_MAX
Definition: gpu_registers.hh:84
gem5::VegaISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:221
gem5::VegaISA::REG_EXEC_LO
@ REG_EXEC_LO
Definition: gpu_registers.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VegaISA::REG_INT_CONST_POS_MAX
@ REG_INT_CONST_POS_MAX
Definition: gpu_registers.hh:82

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