gem5  v22.0.0.2
vecregs.hh
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38 
39 #ifndef __ARCH_X86_VECREGS_HH__
40 #define __ARCH_X86_VECREGS_HH__
41 
43 #include "arch/generic/vec_reg.hh"
44 
45 namespace gem5
46 {
47 
48 namespace X86ISA
49 {
50 
51 // Not applicable to x86
54 
55 } // namespace X86ISA
56 } // namespace gem5
57 
58 #endif // __ARCH_X86_VECREGS_HH__
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:398
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::DummyVecRegContainer
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:268

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