gem5  v21.1.0.2
vecregs.hh
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38 
39 #ifndef __ARCH_X86_VECREGS_HH__
40 #define __ARCH_X86_VECREGS_HH__
41 
43 #include "arch/generic/vec_reg.hh"
44 #include "arch/x86/regs/ccr.hh"
45 #include "arch/x86/regs/float.hh"
46 #include "arch/x86/regs/int.hh"
47 #include "arch/x86/regs/misc.hh"
48 
49 namespace gem5
50 {
51 
52 namespace X86ISA
53 {
54 
55 // Not applicable to x86
59 
60 // Not applicable to x86
62 
63 } // namespace X86ISA
64 } // namespace gem5
65 
66 #endif // __ARCH_X86_VECREGS_HH__
gem5::VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:53
gem5::DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:266
ccr.hh
gem5::X86ISA::VecElem
::gem5::DummyVecElem VecElem
Definition: vecregs.hh:56
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
int.hh
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecRegContainer
VecRegContainer< DummyNumVecElemPerVecReg *sizeof(DummyVecElem)> DummyVecRegContainer
Definition: vec_reg.hh:269
gem5::X86ISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vecregs.hh:58
gem5::DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:267
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
misc.hh
gem5::DummyVecPredRegContainer
VecPredRegContainer< 8, false > DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:395
float.hh

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