Here is a list of all class members with links to the classes they belong to:

- d -

• d : ArmISA::PMU , KvmFPReg , sc_dt::ieee_double
• D : testbench
• d : tlm_utils::time_ordered_list< PAYLOAD >::element
• D0 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
• d1 : iGbReg::TxDesc
• D1 : MipsISA::PTE , PowerISA::PTE , RiscvISA::PTE
• d1 : testbench
• d2 : iGbReg::TxDesc
• d_data : GPUDynInst
• d_reg : VecRegisterState
• dacr : ArmISA::TLB
• data() : AlphaISA::RemoteGDB::AlphaGdbRegCache , Arguments
• Data() : Arguments::Data
• data : Arguments::Data , ArmISA::Decoder , ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::Stage2MMU::Stage2Translation , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , BaseGdbRegCache , BasePrefetcher::PrefetchInfo , BaseRemoteGDB::GdbCommand::Context , CacheBlk , CommandReg , CowDiskImage::Sector , DictionaryCompressor< T >::UncompressedPattern , DmaReadFifo::DmaDoneEvent , DMARequest , EthPacketData , GarnetSyntheticTraffic::GarnetSyntheticTrafficSenderState , ImageFileData , ItsCommand::CommandEntry , KvmFPReg , LSQUnit< Impl >::SQEntry , MemChecker::Transaction , MemoryImage::Segment , Minor::LSQ::LSQRequest , MipsISA::RemoteGDB::MipsGdbRegCache , MSICAP , MSIXCAP , MSIXTable , Net::IpOpt , Net::TcpOpt , Packet , PCIConfig , PMCAP , PowerISA::RemoteGDB::PowerGdbRegCache , PXCAP , RefCountingPtr< T > , RiscvISA::RemoteGDB::RiscvGdbRegCache , RubyRequest , sc_dt::scfx_rep_node , SMMURegs , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , Stats::DistBase< Derived, Stor > , Stats::DistInfo , Stats::DistPrint , Stats::DistProxy< Stat > , Stats::ScalarBase< Derived, Stor > , Stats::ScalarStatNode , Stats::SparseHistBase< Derived, Stor > , Stats::SparseHistInfo , Stats::SparseHistPrint , Stats::StatStor , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Stats::VectorDistInfo , Stats::VectorProxy< Stat > , Stats::VectorStatNode , Terminal , testbench , TimeBuffer< T > , Trace::InstRecord , Trace::TarmacBaseRecord::MemEntry , VncServer , WholeTranslationState , X86ISA::LdStOp , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• data_accesses : AlphaISA::TLB
• data_acv : AlphaISA::TLB
• data_amo_req : AtomicSimpleCPU
• data_corruption__all_bits : FaultModel
• data_corruption__few_bits : FaultModel
• data_fd : Terminal
• data_hits : AlphaISA::TLB
• DATA_INITIAL : MemChecker
• data_misses : AlphaISA::TLB
• data_polarity : HDLcd
• data_ptr : tlm::tlm_endian_context
• data_read() : sc_core::sc_fifo_out< T >
• data_read_event() : sc_core::sc_fifo< T > , sc_core::sc_fifo_nonblocking_out_if< T > , sc_core::sc_fifo_out< T >
• data_read_req : AtomicSimpleCPU
• data_start : aout_exechdr , ecoff_aouthdr
• data_status : Trace::InstRecord
• data_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_out< sc_dt::sc_bigint< W > > , sc_core::sc_out< sc_dt::sc_biguint< W > > , sc_core::sc_out< sc_dt::sc_int< W > > , sc_core::sc_out< sc_dt::sc_uint< W > >
• data_write_req : AtomicSimpleCPU
• data_written() : sc_core::sc_fifo_in< T >
• data_written_event() : sc_core::sc_fifo< T > , sc_core::sc_fifo_in< T > , sc_core::sc_fifo_nonblocking_in_if< T >
• DataAbort() : ArmISA::DataAbort
• dataAccesses : BaseTags::BaseTagStats
• dataArray : CacheMemory
• dataAvailable() : Pl011 , SerialDevice , SerialNullDevice , SimpleUart , Terminal , Uart8250 , Uart
• dataAvailableCallback : PS2Device
• dataBlks : BaseTags
• DataBlock() : DataBlock
• dataBuffer : IdeDisk
• dataCallback() : DMASequencer
• dataCount : UFSHostDevice::UPIUMessage
• dataDistribution : FlashDevice
• DataDouble : Trace::InstRecord
• dataDynamic() : Packet
• dataen_polarity : HDLcd
• DataEvent : BaseRemoteGDB
• dataEvent : BaseRemoteGDB
• DataEvent : Terminal
• dataEvent : Terminal
• DataEvent() : Terminal::DataEvent
• dataEvent : VirtIO9PDiod , VirtIO9PSocket
• DataEvent : VncServer
• dataEvent : VncServer
• DataEvent() : VncServer::DataEvent
• dataExpansions : BaseCache::CacheStats
• dataFd : VncServer
• dataHi : X86ISA::LdStSplitOp
• DataImmOp() : ArmISA::DataImmOp
• DataInt16 : Trace::InstRecord
• DataInt32 : Trace::InstRecord
• DataInt64 : Trace::InstRecord
• DataInt8 : Trace::InstRecord
• DataInvalid : Trace::InstRecord
• dataLastTick : TraceCPU::ElasticDataGen
• dataLatency : BaseCache
• dataLimit : StochasticGen
• dataLow : X86ISA::LdStSplitOp
• dataManipulated : LinearGen , RandomGen
• dataMasterId() : BaseCPU
• dataMasterID : TraceCPU
• dataMsg : UFSHostDevice::UPIUMessage
• dataName : Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• dataOffset : UFSHostDevice::UPIUMessage
• dataPacketLength : DistHeaderPkt::Header
• dataPort : BaseKvmCPU
• DataPort() : ComputeUnit::DataPort , Gicv3Its::DataPort
• dataPort : SimpleMemobj , X86ISA::I8042
• DataReg : PL031
• dataReg : X86ISA::I8042
• DataRegOp() : ArmISA::DataRegOp
• DataRegRegOp() : ArmISA::DataRegRegOp
• DataSectionIndex : BrigObject
• dataSize : ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::VldMultOp64 , ArmISA::VldSingleOp64 , ArmISA::VstMultOp64 , ArmISA::VstSingleOp64
• DataSize : LSQUnit< Impl >::SQEntry
• dataSize : X86ISA::EmulEnv , X86ISA::FpOp , X86ISA::MemOp , X86ISA::RegOpBase , X86ISA::Walker::WalkerState
• dataStatic() : Packet
• dataStaticConst() : Packet
• DataStatus : Trace::InstRecord
• dataTraceFile : TraceCPU
• dataTraceStream : ElasticTrace
• DataTranslation() : DataTranslation< ExecContextPtr >
• DataVec : Trace::InstRecord
• DataVecPred : Trace::InstRecord
• DataWrap() : Stats::DataWrap< Derived, InfoProxyType >
• DataWrapVec() : Stats::DataWrapVec< Derived, InfoProxyType >
• DataWrapVec2d() : Stats::DataWrapVec2d< Derived, InfoProxyType >
• DataWrapVec2d< Derived, Vector2dInfoProxy > : Stats::Vector2dBase< Derived, Stor >
• DataWrapVec< Derived, Vector2dInfoProxy > : Stats::Vector2dBase< Derived, Stor >
• DataWrapVec< Derived, VectorDistInfoProxy > : Stats::VectorDistBase< Derived, Stor >
• DataWrapVec< Derived, VectorInfoProxy > : Stats::VectorBase< Derived, Stor >
• DataX1Reg2ImmOp() : ArmISA::DataX1Reg2ImmOp
• DataX1RegImmOp() : ArmISA::DataX1RegImmOp
• DataX1RegOp() : ArmISA::DataX1RegOp
• DataX2RegImmOp() : ArmISA::DataX2RegImmOp
• DataX2RegOp() : ArmISA::DataX2RegOp
• DataX3RegOp() : ArmISA::DataX3RegOp
• DataXCondCompImmOp() : ArmISA::DataXCondCompImmOp
• DataXCondCompRegOp() : ArmISA::DataXCondCompRegOp
• DataXCondSelOp() : ArmISA::DataXCondSelOp
• DataXERegOp() : ArmISA::DataXERegOp
• DataXImmOnlyOp() : ArmISA::DataXImmOnlyOp
• DataXImmOp() : ArmISA::DataXImmOp
• DataXSRegOp() : ArmISA::DataXSRegOp
• date() : Time
• dati : test
• dato : test
• db : CheckpointIn
• dbg_cb : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• dbg_vtophys() : BaseSimpleCPU , CheckerCPU , MinorCPU
• dbgHeader() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• dbl() : ArmISA::FpOp , InstResult::MultiResult
• dblHi() : ArmISA::FpOp
• dblLow() : ArmISA::FpOp
• dbuf_size : tlm::tlm_endian_context
• dcache_access : AtomicSimpleCPU
• dcache_latency : AtomicSimpleCPU
• dcache_pkt : TimingSimpleCPU
• dcacheGen : TraceCPU
• dcacheInterface : InstructionQueue< Impl >
• dcacheNextEvent : TraceCPU
• dcachePort : AtomicSimpleCPU , CheckerCPU , LSQ< Impl >
• DcachePort() : LSQ< Impl >::DcachePort
• dcachePort : LSQUnit< Impl > , Minor::LSQ
• DcachePort() : Minor::LSQ::DcachePort
• dcachePort : TimingSimpleCPU
• DcachePort() : TimingSimpleCPU::DcachePort
• dcachePort : TraceCPU
• DcachePort() : TraceCPU::DcachePort
• dcacheRecvTimingResp() : TraceCPU
• DcacheRetry : BaseSimpleCPU
• dcacheRetryRecvd() : TraceCPU
• dcacheStallCycles : SimpleExecContext
• DcacheWaitResponse : BaseSimpleCPU
• DcacheWaitSwitch : BaseSimpleCPU
• dcc : RealViewCtrl
• dcp : StreamTableEntry
• dcpt : DCPTPrefetcher , SlimAMPMPrefetcher
• DCPTEntry() : DeltaCorrelatingPredictionTables::DCPTEntry
• DCPTPrefetcher() : DCPTPrefetcher
• deactivateIRQ() : Gicv3CPUInterface , Gicv3Distributor , Gicv3Redistributor
• deactivateStage() : ActivityRecorder , DefaultIEW< Impl > , FullO3CPU< Impl >
• deactivateThread() : DefaultCommit< Impl > , DefaultFetch< Impl > , FullO3CPU< Impl >
• deadlockCheckEvent : GPUCoalescer , Sequencer
• deallocate() : CacheMemory , MSHR , PerfectCacheMemory< ENTRY > , Queue< Entry > , TBETable< ENTRY > , WriteQueueEntry
• deallocateContext() : BaseKvmCPU
• deassertInt() : Gicv3
• deassertSPI() : Gicv3Distributor
• debug() : tlm::circular_buffer< T > , tlm::tlm_fifo< T > , tlm::tlm_fifo_debug_if< T >
• Debug_Break_Pri : EventBase
• Debug_Enable_Pri : EventBase
• debug_func_type : tlm_utils::callback_binder_fw< TYPES >
• DebugBreakEvent() : DebugBreakEvent
• debugCounter() : ArmISA::PMU::CounterState
• DebugEvent : ArmISA::ArmFault
• DebugException() : X86ISA::DebugException
• debugFunc() : GenericISA::M5DebugFault , GenericISA::M5FatalFault , GenericISA::M5HackFaultBase< Base > , GenericISA::M5InformFaultBase< Base > , GenericISA::M5PanicFault , GenericISA::M5WarnFaultBase< Base >
• debugPrint() : Check
• debugPrintkEvent : ArmSystem
• DebugPrintkEvent() : Linux::DebugPrintkEvent
• debugPrintkEvent : LinuxAlphaSystem
• debugSegFault : ComputeUnit
• debugVerify() : EventQueue
• dec : cp::Format , Stats::AvgStor , Stats::StatStor
• dec_use_count() : tlm_utils::instance_specific_extension_container
• decay : MultiperspectivePerceptron
• DECL_BIN_OP_T() : sc_dt::sc_fxnum_fast , sc_dt::sc_fxval_fast
• declare_router() : FaultModel
• decode() : AlphaISA::Decoder , ArmISA::Decoder , DefaultDecode< Impl > , DefaultFetch< Impl >::Stalls , FullO3CPU< Impl > , GenericISA::BasicDecodeCache , HsailISA::Decoder
• Decode() : Minor::Decode
• decode : Minor::Pipeline , MipsISA::Decoder , MultiSocketSimpleSwitchAT , PowerISA::Decoder , RiscvISA::Decoder , SimpleAddressMap , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• Decode : SimpleCPUPolicy< Impl >
• decode() : SparcISA::Decoder , X86ISA::Decoder
• decodeAddr() : DRAMCtrl
• decodeAddress() : GenericPciHost
• decodeBlock : TimeBufStruct< Impl >
• decodeBlockedCycles : DefaultDecode< Impl >
• decodeBranchMispred : DefaultDecode< Impl >
• decodeBranchResolved : DefaultDecode< Impl >
• decodeControlMispred : DefaultDecode< Impl >
• decodeCoProcReg() : ArmKvmCPU
• decodeDecodedInsts : DefaultDecode< Impl >
• decodedInsts : HsailISA::Decoder
• decodeIdleCycles : DefaultDecode< Impl >
• DecodeIdx : FullO3CPU< Impl >
• decodeInfo : Minor::Decode , TimeBufStruct< Impl >
• decodeInst() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• decodeInsts() : DefaultDecode< Impl >
• decodePages : GenericISA::BasicDecodeCache , X86ISA::Decoder
• DecodePages : X86ISA::Decoder
• decodePolicyName() : SMMUv3BaseCache
• decodePrologue() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• decodeQueue : DefaultDecode< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• Decoder() : AlphaISA::Decoder , ArmISA::Decoder
• decoder : DefaultFetch< Impl > , FetchUnit , HsailCode
• Decoder() : MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder
• decoder : SimpleThread
• Decoder() : SparcISA::Decoder , X86ISA::Decoder
• DecoderFaultInst() : DecoderFaultInst
• decoderFlavour : ArmISA::Decoder , ArmISA::ISA
• decodeRunCycles : DefaultDecode< Impl >
• decodeSave() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• decodeSquashCycles : DefaultDecode< Impl >
• decodeSquashedInsts : DefaultDecode< Impl >
• decodeStack() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• DecodeStageId : Minor::Pipeline
• decodeStatus : DefaultDecode< Impl >
• DecodeStatus : DefaultDecode< Impl >
• DecodeStruct : DefaultDecode< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , SimpleCPUPolicy< Impl >
• DecodeThreadInfo() : Minor::Decode::DecodeThreadInfo
• decodeToFetchDelay : DefaultFetch< Impl >
• decodeToRenameDelay : DefaultRename< Impl >
• decodeUnblock : TimeBufStruct< Impl >
• decodeUnblockCycles : DefaultDecode< Impl >
• decodeVFPCtrlReg() : ArmKvmCPU
• decodeWidth : DefaultDecode< Impl > , DefaultFetch< Impl >
• decompress() : BaseCacheCompressor , DictionaryCompressor< T > , DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits > , DictionaryCompressor< T >::MaskedPattern< mask > , DictionaryCompressor< T >::MaskedValuePattern< value, mask > , DictionaryCompressor< T >::Pattern , DictionaryCompressor< T >::RepeatedValuePattern< RepT > , DictionaryCompressor< T >::UncompressedPattern , MultiCompressor , PerfectCompressor
• decompressionLatency : PerfectCompressor
• decompressions : BaseCacheCompressor::BaseCacheCompressorStats
• decompressValue() : DictionaryCompressor< T >
• decrease() : CircularQueue< T >
• decreaseRefCounter() : LdsState
• decref() : RefCounted , sc_gem5::Process
• decrement_credit() : OutputUnit , OutVcState
• decrementable() : CircularQueue< T >::iterator
• DecrementAfter : ArmISA::RfeOp , ArmISA::SrsOp
• DecrementBefore : ArmISA::RfeOp , ArmISA::SrsOp
• decrNumPinnedWrites() : PhysRegId
• decrNumPinnedWritesToComplete() : PhysRegId
• decrTos() : ReturnAddrStack
• deep_copy_from() : tlm::tlm_generic_payload
• defAddr : X86ISA::Decoder
• DEFAULT : PseudoInst::InitParamKey
• default_color : HDLcd
• default_event() : sc_core::sc_event_queue , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_interface , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_gem5::ScSignalBaseT< T, WRITER_POLICY >
• default_handler() : sc_core::sc_report_handler
• DEFAULT_MAX_NUM_BASES : BaseDelta< BaseType, DeltaSizeBits >
• default_name() : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• default_observer : sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer
• Default_Pri : EventBase
• default_sign() : sc_dt::sc_signed , sc_dt::sc_unsigned
• default_value() : sc_dt::sc_context< T >
• defaultBackdoorWarned : SlavePort
• DefaultBTB() : DefaultBTB
• defaultCache : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , SparcISA::Decoder
• DefaultCommit() : DefaultCommit< Impl >
• defaultConfig : X86ISA::IntelMP::FloatingPointer
• DefaultDecode() : DefaultDecode< Impl >
• defaultEvent() : sc_gem5::ScSignalBase
• DefaultFetch() : DefaultFetch< Impl >
• DefaultFloatResult : ThreadContext
• defaultFloatRound : Brig::BrigDirectiveModule
• DefaultIEW() : DefaultIEW< Impl >
• DefaultIntResult : ThreadContext
• defaultOnCompletion() : X86ISA::IntMasterPort< Device >
• defaultPortID : BaseXBar
• defaultPriority : QoS::FixedPriorityPolicy
• DefaultPriority : sc_gem5::Scheduler
• defaultRange : BaseXBar
• DefaultRename() : DefaultRename< Impl >
• DefaultReportMessages() : sc_gem5::DefaultReportMessages
• defaultSid : DmaPort
• defaultSSid : DmaPort
• DefaultStackSize : Fiber
• defCc : ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::FpCondCompRegOp
• deferMemInst() : InstructionQueue< Impl >
• deferredMemInsts : InstructionQueue< Impl >
• DeferredPacket() : Bridge::DeferredPacket , PacketQueue::DeferredPacket , QueuedPrefetcher::DeferredPacket , SerialLink::DeferredPacket , SimpleMemory::DeferredPacket
• DeferredPacketList : PacketQueue
• deferredPacketReady() : PacketQueue
• deferredPacketReadyTime() : PacketQueue
• deferredTargets : MSHR
• define() : Label
• defined() : Label
• defns : TimingExprLet
• defOp : X86ISA::Decoder
• degree : AccessMapPatternMatching , IrregularStreamBufferPrefetcher , StridePrefetcher , TaggedPrefetcher
• dehash() : SkewedAssociative
• del() : RefCountingPtr< T >
• delay : Bridge::BridgeMasterPort , Bridge::BridgeSlavePort , DmaPort::DmaReqState , ItsAction , Minor::Latch< Data > , MSHR , MSHRQueue , SerialLink::SerialLinkMasterPort , SerialLink::SerialLinkSlavePort , SMMUAction , WholeTranslationState , WriteAllocator
• delayCtr : WriteAllocator
• delayed : ArmISA::TableWalker::WalkerState
• Delayed : LSQ< Impl >::LSQRequest
• delayed() : sc_gem5::Scheduler
• Delayed_Writeback_Pri : EventBase
• delayedCommit : DefaultFetch< Impl >
• delayedNotify : sc_gem5::Event
• delayedStartup() : KvmVM
• delayHead() : MessageBuffer
• delayHistogram : Profiler
• delayIntEvent() : IGbE
• delayQueue : BOPPrefetcher
• delayQueueEnabled : BOPPrefetcher
• DelayQueueEntry() : BOPPrefetcher::DelayQueueEntry
• delayQueueEvent : BOPPrefetcher
• delayQueueEventWrapper() : BOPPrefetcher
• delayQueueSize : BOPPrefetcher
• delayReq() : MemDelay , SimpleMemDelay
• delayResp() : MemDelay , SimpleMemDelay
• DelaySlotPCState() : GenericISA::DelaySlotPCState< MachInst >
• DelaySlotUPCState() : GenericISA::DelaySlotUPCState< MachInst >
• delaySnoopResp() : MemDelay
• delayThreshold : WriteAllocator
• delayTicks : BOPPrefetcher
• delayVar : DistEtherLink::TxLink , EtherLink::Link , EtherSwitch::Interface
• delayVCHistogram : Profiler
• delBp() : Iris::ThreadContext
• delChildEvent() : sc_gem5::Object
• delete_top() : tlm_utils::time_ordered_list< PAYLOAD >
• deleted : LSQ< Impl >::LSQSenderState
• deleteData() : Packet
• deleteIndirectInfo() : IndirectPredictor , SimpleIndirectPredictor
• deleteObjects() : CxxConfigManager
• deleteReqs() : WholeTranslationState
• deleteRequest() : LSQ< Impl >::LSQSenderState , Minor::LSQ::StoreBuffer
• delFromEvent() : sc_gem5::DynamicSensitivity , sc_gem5::Sensitivity , sc_gem5::StaticSensitivity
• deliverInterrupts() : X86KvmCPU
• deliveryMode : X86ISA::I82094AA , X86ISA::Interrupts
• deliveryStatus : X86ISA::I82094AA
• delSensitivity() : sc_gem5::Event
• delta : SignaturePathPrefetcherV2::GlobalHistoryEntry , STeMSPrefetcher::ActiveGenerationTableEntry::SequenceEntry , STeMSPrefetcher::RegionMissOrderBufferEntry , TraceCPU::FixedRetryGen
• delta_count() : sc_core::sc_simcontext
• delta_list() : tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list
• deltaBits : DeltaCorrelatingPredictionTables
• DeltaCorrelatingPredictionTables() : DeltaCorrelatingPredictionTables
• deltaMaskBits : DeltaCorrelatingPredictionTables
• DeltaPattern() : DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >
• deltaPointer : DeltaCorrelatingPredictionTables::DCPTEntry
• deltas : DeltaCorrelatingPredictionTables::DCPTEntry , sc_gem5::Scheduler
• deltasAtNow : sc_gem5::VcdTraceFile
• demandAccesses : BaseCache::CacheStats
• demandAddresses : SBOOEPrefetcher
• demandAvgMissLatency : BaseCache::CacheStats
• demandAvgMshrMissLatency : BaseCache::CacheStats
• demandHits : BaseCache::CacheStats
• demandMisses : BaseCache::CacheStats
• demandMissLatency : BaseCache::CacheStats
• demandMissRate : BaseCache::CacheStats
• demandMshrHits : BaseCache::CacheStats
• demandMshrMisses : BaseCache::CacheStats
• demandMshrMissLatency : BaseCache::CacheStats
• demandMshrMissRate : BaseCache::CacheStats
• demandReserve : MSHRQueue
• demapAll() : SparcISA::TLB
• demapContext() : SparcISA::TLB
• demapDataPage() : BaseDynInst< Impl > , CheckerCPU , FullO3CPU< Impl > , Minor::ExecContext , SimpleThread
• demapInstPage() : BaseDynInst< Impl > , CheckerCPU , FullO3CPU< Impl > , Minor::ExecContext , SimpleThread
• demapPage() : AlphaISA::TLB , ArmISA::TLB , BaseDynInst< Impl > , BaseTLB , CheckerCPU , ExecContext , FullO3CPU< Impl > , Iris::TLB , Minor::ExecContext , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SimpleExecContext , SimpleThread , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• depCheckShift : LSQUnit< Impl >
• DependencyEntry() : DependencyEntry< DynInstPtr >
• DependencyGraph() : DependencyGraph< DynInstPtr >
• dependentReads : SMMUv3SlaveInterface
• dependentReqRemoved : SMMUv3SlaveInterface
• dependents : TraceCPU::ElasticDataGen::GraphNode
• dependentWrites : SMMUv3SlaveInterface
• dependGraph : DependencyGraph< DynInstPtr > , InstructionQueue< Impl >
• dependInsts : MemDepUnit< MemDepPred, Impl >::MemDepEntry
• depends : HsaQueueEntry
• DepEntry : DependencyGraph< DynInstPtr >
• depFreeQueue : TraceCPU::ElasticDataGen
• depGraph : TraceCPU::ElasticDataGen
• depPred : MemDepUnit< MemDepPred, Impl >
• deprecatedConstructor() : sc_gem5::Module
• depsReady() : EmbeddedPyBind
• depth : Brig::BrigOperandConstantImage , PixelConverter , Request , VncInput::PixelFormat
• depTrace : ElasticTrace
• depTraceItr : ElasticTrace
• depTraceRevItr : ElasticTrace
• depWindowSize : ElasticTrace
• dequeue() : MessageBuffer , SimpleMemory , WireBuffer
• dequeueCallback() : NetworkInterface
• dequeueEvent : SimpleMemory
• dereferenceable() : CircularQueue< T >::iterator
• DerivedClockDomain() : DerivedClockDomain
• DerivO3CPU() : DerivO3CPU
• desc() : Debug::Flag
• Desc() : DistIface::RecvScheduler::Desc
• desc() : Stats::DataWrap< Derived, InfoProxyType > , Stats::DistPrint , Stats::Info , Stats::ScalarPrint , Stats::SparseHistPrint , Stats::VectorPrint , VirtDescriptor , vring
• descBase() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• DescCache() : IGbE::DescCache< T >
• descChainAddr : CopyEngineReg::ChanRegs
• descDmaRdBytes : EtherDevice
• descDmaReads : EtherDevice
• descDmaWrBytes : EtherDevice
• descDmaWrites : EtherDevice
• descEnd : IGbE::TxDescCache
• descHead() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• deschedule() : BaseGlobalEvent , EventManager , EventQueue , LdsState::TickEvent , sc_gem5::ScEvent , sc_gem5::Scheduler
• descheduleDeadlockEvent() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer
• descheduleInstCommitEvent() : BaseRemoteGDB
• descheduleInstCountEvent() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• deschedulePowerGatingEvent() : BaseCPU
• descInBlock() : IGbE::TxDescCache
• descLeft() : IGbE::DescCache< T >
• descLen() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• descQueue : DistIface::RecvScheduler
• descr() : PCEvent
• describe() : X86ISA::PageFault , X86ISA::X86FaultBase
• description() : BaseGlobalEvent , CountedExitEvent , CPUProgressEvent , DebugBreakEvent , DefaultFetch< Impl >::FinishTranslationEvent , EndQuiesceEvent , Event , EventFunctionWrapper , EventWrapper< T, F > , GlobalSimLoopExitEvent , GlobalSyncEvent , InstructionQueue< Impl >::FUCompletion , Intel8254Timer::Counter::CounterEvent , LocalSimLoopExitEvent , LSQUnit< Impl >::WritebackEvent , MC146818::RTCEvent , MC146818::RTCTickEvent , Minor::FUPipeline , MinorFUTiming , PCEvent , SMMUDeviceRetryEvent , Stats::StatEvent , TimingSimpleCPU::DcachePort::DTickEvent , TimingSimpleCPU::IcachePort::ITickEvent , TimingSimpleCPU::IprEvent , TimingSimpleCPU::TimingCPUPort::TickEvent , Trace::TarmacParserRecord::TarmacParserRecordEvent , X86ISA::GpuTLB::TLBEvent
• descriptions : Stats::DistPrint , Stats::ScalarPrint , Stats::SparseHistPrint , Stats::Text , Stats::VectorPrint
• DescriptorBase() : ArmISA::TableWalker::DescriptorBase
• DescriptorFetch : CopyEngine::CopyEngineChannel
• descriptors : VirtQueue
• descs : ArmFreebsdProcessBits::SyscallTable , ArmLinuxProcessBits::SyscallTable
• descSize() : iGbReg::Regs::RCTL
• descTail() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• descUnused() : IGbE::DescCache< T >
• descUsed() : IGbE::DescCache< T >
• deskew() : SkewedAssociative
• dest : ArmISA::DataImmOp , ArmISA::DataRegOp , ArmISA::DataRegRegOp , ArmISA::DataX1Reg2ImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX1RegOp , ArmISA::DataX2RegImmOp , ArmISA::DataX2RegOp , ArmISA::DataX3RegOp , ArmISA::DataXCondSelOp , ArmISA::DataXERegOp , ArmISA::DataXImmOnlyOp , ArmISA::DataXImmOp , ArmISA::DataXSRegOp , ArmISA::FpCondSelOp , ArmISA::FpRegImmOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegOp , ArmISA::FpRegRegRegCondOp , ArmISA::FpRegRegRegImmOp , ArmISA::FpRegRegRegOp , ArmISA::FpRegRegRegRegOp , ArmISA::Memory64 , ArmISA::Memory , ArmISA::MicroMemPairOp , ArmISA::MicroNeonMemOp , ArmISA::MicroNeonMixLaneOp64 , ArmISA::MicroNeonMixOp64 , ArmISA::MicroNeonMixOp , ArmISA::SveAdrOp , ArmISA::SveBinConstrPredOp , ArmISA::SveBinDestrPredOp , ArmISA::SveBinIdxUnpredOp , ArmISA::SveBinImmIdxUnpredOp , ArmISA::SveBinImmPredOp , ArmISA::SveBinImmUnpredConstrOp , ArmISA::SveBinImmUnpredDestrOp , ArmISA::SveBinUnpredOp , ArmISA::SveBinWideImmUnpredOp , ArmISA::SveCmpImmOp , ArmISA::SveCmpOp , ArmISA::SveComplexIdxOp , ArmISA::SveComplexOp , ArmISA::SveContigMemSI , ArmISA::SveContigMemSS , ArmISA::SveDotProdIdxOp , ArmISA::SveDotProdOp , ArmISA::SveElemCountOp , ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIndexIIOp , ArmISA::SveIndexIROp , ArmISA::SveIndexRIOp , ArmISA::SveIndexRROp , ArmISA::SveIntCmpImmOp , ArmISA::SveIntCmpOp , ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveMemPredFillSpill , ArmISA::SveMemVecFillSpill , ArmISA::SveOrdReducOp , ArmISA::SvePartBrkOp , ArmISA::SvePartBrkPropOp , ArmISA::SvePredBinPermOp , ArmISA::SvePredCountOp , ArmISA::SvePredCountPredOp , ArmISA::SvePredLogicalOp , ArmISA::SvePredUnaryWImplicitSrcOp , ArmISA::SvePredUnaryWImplicitSrcPredOp , ArmISA::SvePtrueOp , ArmISA::SveReducOp , ArmISA::SveSelectOp , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveTblOp , ArmISA::SveTerImmUnpredOp , ArmISA::SveTerPredOp , ArmISA::SveUnaryPredOp , ArmISA::SveUnaryPredPredOp , ArmISA::SveUnarySca2VecUnpredOp , ArmISA::SveUnaryUnpredOp , ArmISA::SveUnaryWideImmPredOp , ArmISA::SveUnaryWideImmUnpredOp , ArmISA::SveUnpackOp , ArmISA::SveWhileOp , ArmISA::SysDC64 , CopyEngineReg::DmaDesc , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::Call , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , McrrOp , MiscRegImmOp64 , MiscRegRegImmOp64 , MiscRegRegImmOp , MrrcOp , MrsOp , RegImmImmOp , RegImmOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp64 , RegMiscRegImmOp , RegOp , RegRegImmImmOp64 , RegRegImmImmOp , RegRegImmOp , RegRegOp , RegRegRegImmOp64 , RegRegRegImmOp , RegRegRegOp , RegRegRegRegOp , X86ISA::FpOp , X86ISA::I82094AA , X86ISA::MediaOpBase , X86ISA::RegOpBase
• dest2 : ArmISA::MemoryDImm64 , ArmISA::MemoryDImm , ArmISA::MemoryDReg , ArmISA::MicroMemPairOp , MrrcOp
• dest_ni : RouteInfo
• dest_router : RouteInfo
• dest_vect : HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >
• destApicID : X86ISA::IntelMP::IntAssignment
• destApicIntIn : X86ISA::IntelMP::IntAssignment
• DestCType : HsailISA::SpecialInst1Src< DestDataType > , HsailISA::SpecialInstNoSrc< DestDataType > , HsailISA::ThreeNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType, Src2DataType > , HsailISA::TwoNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType >
• destination : UFSHostDevice::SCSIResumeInfo , UFSHostDevice::taskStart , UFSHostDevice::transferDoneInfo , UFSHostDevice::transferStart
• destIsVec : ArmISA::SvePredCountOp
• destMode : X86ISA::I82094AA
• DestOperand : HsailISA::HsailOperandType< _DestOperand, _SrcOperand >
• destRegIdx() : BaseDynInst< Impl > , StaticInst
• destRegRecords : Trace::TarmacParserRecord
• destroyPacket() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• destroyStreams() : ProtoInputStream
• destruct() : sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer
• destSize : X86ISA::MediaOpBase
• detach() : ArmISA::PMU::CounterState , BaseRemoteGDB , EtherTapStub , PerfKvmCounter , Terminal , VncServer
• detachEvent() : ArmISA::PMU::PMUEvent
• determineArch() : ElfObject
• determineOpSys() : ElfObject
• dev : IGbEInt , NSGigEInt , PciBusAddr , RealViewCtrl , Sinic::Interface
• dev_mondo_head : SparcISA::ISA
• dev_mondo_tail : SparcISA::ISA
• dev_t : RiscvLinux64 , Solaris
• devBits : Gicv3Its
• device : DmaPort , IntSinkPin< Device > , PCIConfig , PioPort< Device >
• Device() : RealViewCtrl::Device , Sinic::Device
• device : Uart , VirtIOConsole , X86ISA::IntMasterPort< Device > , X86ISA::IntSlavePort< Device >
• DEVICE_SCOPE : Request
• DEVICE_TABLE : Gicv3Its
• deviceBusWidth : DRAMCtrl
• deviceEventQueue() : BaseKvmCPU
• DeviceFDEntry() : DeviceFDEntry
• deviceFeatures : VirtIODeviceBase
• DeviceFunc : RealViewCtrl
• DeviceId : Iob
• deviceId : ItsCommand::CommandEntry , VirtIODeviceBase
• DeviceId : VirtIODeviceBase
• DeviceInterface() : PciHost::DeviceInterface
• deviceNeedsRetry : SMMUv3SlaveInterface
• DeviceNotAvailable() : X86ISA::DeviceNotAvailable
• deviceOutOfRange() : Gicv3Its , ItsCommand
• deviceReadCallback : UFSHostDevice::UFSSCSIDevice
• deviceRegSet : ArmV8KvmCPU
• deviceRowBufferSize : DRAMCtrl
• devices : I2CBus , PciHost , RealViewCtrl
• deviceSize : DRAMCtrl
• devicesPerRank : DRAMCtrl
• deviceTiming : IdeController
• deviceUsed : VirtIO9PProxy
• devID : IdeDisk
• devIntrChangeMask() : NSGigE , Sinic::Device
• devIntrClear() : NSGigE , Sinic::Device
• devIntrPost() : NSGigE , Sinic::Device
• devlist : EtherBus
• devlist_t : EtherBus
• devname : BadDevice
• devState : IdeDisk
• DFB : Gicv3CPUInterface
• dg1 : testbench
• DiagnosticDump : X86ISA::I8042
• DIB : Gicv3CPUInterface
• dict_len : DmesgEntry
• dictionary : DictionaryCompressor< T >
• DictionaryCompressor() : DictionaryCompressor< T >
• DictionaryEntry : BaseDelta< BaseType, DeltaSizeBits > , CPack , DictionaryCompressor< T > , FPCD , RepeatedQwordsCompressor , ZeroCompressor
• dictionarySize : BaseDictionaryCompressor
• diff : stage1_2
• difference_type : CircularQueue< T >::iterator , sc_core::sc_vector_iter< Element, AccessPolicy >
• digit : sc_dt::sc_signed , sc_dt::sc_unsigned
• dim : Brig::BrigDirectiveVariable , TsunamiCChip
• diod_pid : VirtIO9PDiod
• DiodDataEvent() : VirtIO9PDiod::DiodDataEvent
• dir() : CheckpointIn , LoopPredictor::LoopEntry , OutputDirectory , TsunamiCChip
• dir_map_t : OutputDirectory
• DirectedGenerator() : DirectedGenerator
• directedStartEvent : RubyDirectedTester
• directory() : OutputDirectory
• DirectoryMemory() : DirectoryMemory
• directToStage2 : ArmISA::TLB
• dirs : OutputDirectory
• dirty() : ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , MmDisk
• DirVarToSE_map : StorageSpace
• disable() : ArmISA::PMU::PMUEvent , ArmISA::PMU::RegularEvent , ArmISA::PMU::SWIncrementEvent , Debug::AllFlags , Debug::CompoundFlag , Debug::Flag , Debug::SimpleFlag , PollEvent , sc_core::sc_process_handle , sc_gem5::Process
• disable_cb_bind() : tlm_utils::multi_init_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• DisableA20 : X86ISA::I8042
• disableAddrDists : CommMonitor::MonitorStats
• disableAll() : Debug::SimpleFlag , ListenSocket
• disableBandwidthHists : CommMonitor::MonitorStats
• disableBurstLengthHists : CommMonitor::MonitorStats
• disableCoalescing : TLBCoalescer
• disabled : ArmISA::UndefinedInstruction , PerfKvmCounterConfig , sc_gem5::Process
• disabledFault() : ArmISA::ArmStaticInst
• disableITTDists : CommMonitor::MonitorStats
• DisableKeyboard : X86ISA::I8042
• disableKeyboard : X86ISA::I8042
• disableLatencyHists : CommMonitor::MonitorStats
• disableLinearHists : StackDistProbe
• disableLogHists : StackDistProbe
• disableMemAccess() : Minor::LSQ::LSQRequest
• disableMemSlot() : KvmVM
• disableMouse : X86ISA::I8042
• DisableMouse : X86ISA::I8042
• disableOutstandingHists : CommMonitor::MonitorStats
• disableSanityCheck() : PacketQueue
• disableTransactionHists : CommMonitor::MonitorStats
• disarm() : BaseKvmTimer , PerfKvmTimer , PosixKvmTimer
• disassemble() : AddrOperandBase , CRegOperand , DRegOperand , FunctionRefOperand , GPUDynInst , GPUStaticInst , ImmOperand< T > , LabelOperand , ListOperand , NoRegAddrOperand , PowerISA::PCDependentDisassembly , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T > , SRegOperand , StaticInst , Trace::TarmacBaseRecord::InstEntry
• disassembly : GPUStaticInst
• discard() : ItsCommand
• DISCARD : ItsCommand
• discard() : LSQ< Impl >::LSQRequest , sc_dt::scfx_string
• Discarded : LSQ< Impl >::LSQRequest
• discardFetch() : Wavefront
• discardLeft : StackDistCalc::Node
• discardPendingSignal() : BaseKvmCPU
• discardRight : StackDistCalc::Node
• discardSenderState() : LSQ< Impl >::LSQRequest
• disk : AlphaBackdoor
• disk_size : RawDiskImage
• diskBlock : AlphaAccess , MipsAccess
• diskCount : AlphaAccess , MipsAccess
• diskData : MmDisk
• diskDelay : IdeDisk
• DiskImage() : DiskImage
• diskOperation : AlphaAccess , MipsAccess
• diskPAddr : AlphaAccess , MipsAccess
• diskSize : FlashDevice , UFSHostDevice::UFSSCSIDevice
• diskUnit : AlphaAccess , MipsAccess
• disp : PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::MemDispOp , SparcISA::BranchDisp , X86ISA::MemOp
• dispatch() : DefaultIEW< Impl >
• dispatch_workgroups() : Shader
• dispatchAccess() : IdeController
• dispatchActive : GpuDispatcher
• dispatchCount : GpuDispatcher
• dispatched : TimeBufStruct< Impl >::iewComm
• dispatchedToLQ : TimeBufStruct< Impl >::iewComm
• dispatchedToSQ : TimeBufStruct< Impl >::iewComm
• DispatchEntry() : ItsCommand::DispatchEntry
• dispatcher : ClDriver , GpuDispatcher::TLBPort , Shader
• dispatchId : NDRange , Wavefront
• dispatchInsts() : DefaultIEW< Impl >
• dispatchList : ComputeUnit , ExecStage , ScheduleStage
• dispatchStatus : DefaultIEW< Impl >
• DispatchTable : ItsCommand
• dispatchWidth : DefaultIEW< Impl >
• displacement : X86ISA::ExtMachInst
• displacementSize : X86ISA::Decoder
• DisplacementState : X86ISA::Decoder
• Display() : Display
• display_error() : tlm_utils::convenience_socket_base , tlm_utils::convenience_socket_cb_holder
• display_statistics() : sc_core::sc_mempool
• display_warning() : tlm_utils::convenience_socket_base , tlm_utils::convenience_socket_cb_holder
• DisplayTimings() : DisplayTimings
• displayTimings() : HDLcd
• dispSize : X86ISA::ExtMachInst
• DIST_RANK : PseudoInst::InitParamKey
• DIST_SIZE : GicV2 , PseudoInst::InitParamKey
• distanceFromTrigger() : PIFPrefetcher::CompactorEntry
• DistBase() : Stats::DistBase< Derived, Stor >
• DistEtherLink() : DistEtherLink
• DistHeaderPkt() : DistHeaderPkt
• distIface : DistEtherLink , DistEtherLink::Link
• DistIface() : DistIface
• distIfaceId : DistIface , TCPIface::NodeInfo
• distIfaceNum : DistIface , TCPIface::NodeInfo
• DistInfoProxy() : Stats::DistInfoProxy< Stat >
• DistParams() : Stats::DistParams
• distPioDelay : GicV2
• DistPrint() : Stats::DistPrint
• DistProxy() : Stats::DistProxy< Stat >
• DistProxy< Derived > : Stats::VectorDistBase< Derived, Stor >
• distRange : Gicv3 , KvmKernelGicV2
• Distribution() : Stats::Distribution
• distributor : Gicv3 , Gicv3CPUInterface , Gicv3Redistributor
• DistStor() : Stats::DistStor
• div_scfx_rep : sc_dt::scfx_rep
• div_signed_friend : sc_dt::sc_signed
• div_unsigned_friend : sc_dt::sc_unsigned
• divide_by_ten() : sc_dt::scfx_rep
• DivideError() : X86ISA::DivideError
• DLAB : Uart8250
• dm : MC146818
• dmaAborted : IdeDisk
• dmaAction() : DmaPort
• dmaAddr() : GenericPciHost , PciHost::DeviceInterface , PciHost , TsunamiPChip
• dmaBuffer : Pl111
• DmaCallback() : DmaCallback
• dmaCap1 : IdeController
• dmaDataFree : NSGigE
• dmaDescFree : NSGigE
• DmaDevice() : DmaDevice
• dmaDone() : DmaReadFifo , Pl111
• DmaDoneEvent() : DmaReadFifo::DmaDoneEvent
• dmaDoneEventAll : Pl111
• dmaDoneEventFree : Pl111
• DmaDoneEventUPtr : DmaReadFifo
• dmaEngine : HDLcd
• DmaEngine() : HDLcd::DmaEngine
• dmaError : IdeController
• dmaIdle : NSGigE
• dmaPending() : DmaDevice , DmaPort
• dmaPendingNum : Pl111
• dmaPort : DmaDevice
• DmaPort() : DmaPort
• dmaPort : Gicv3Its
• dmaPrdReadDone() : IdeDisk
• dmaPrdReadEvent : IdeDisk
• DMARead : CopyEngine::CopyEngineChannel
• dmaRead() : DmaDevice , IdeDisk
• dmaReadBytes : IdeDisk
• dmaReadCG : IdeDisk
• dmaReadDelay : NSGigE , Sinic::Device
• dmaReadDone() : IdeDisk
• dmaReadEvent : IdeDisk
• dmaReadFactor : NSGigE , Sinic::Device
• DmaReadFifo() : DmaReadFifo
• dmaReadFullPages : IdeDisk
• dmaReading : NSGigE
• dmaReadTxs : IdeDisk
• dmaReadWaitEvent : IdeDisk
• dmaReadWaiting : NSGigE
• DmaReqState() : DmaPort::DmaReqState
• DMARequest() : DMARequest
• DMASequencer() : DMASequencer
• dmaSize : Pl111
• dmaState : IdeDisk
• DmaState : NSGigE
• dmaTransferEvent : IdeDisk
• DMAWrite : CopyEngine::CopyEngineChannel
• dmaWrite() : DmaDevice
• dmaWriteBytes : IdeDisk
• dmaWriteCG : IdeDisk
• dmaWriteDelay : NSGigE , Sinic::Device
• dmaWriteDone() : IdeDisk
• dmaWriteEvent : IdeDisk
• dmaWriteFactor : NSGigE , Sinic::Device
• dmaWriteFullPages : IdeDisk
• dmaWriteInfo : UFSHostDevice
• dmaWriteTxs : IdeDisk
• dmaWriteWaitEvent : IdeDisk
• dmaWriteWaiting : NSGigE
• dmaWriting : NSGigE
• dmDrain() : Drainable
• dmDrainResume() : Drainable
• DmesgDumpEvent() : Linux::DmesgDumpEvent
• dmi_access_e : tlm::tlm_dmi
• DMI_ACCESS_NONE : tlm::tlm_dmi
• DMI_ACCESS_READ : tlm::tlm_dmi
• DMI_ACCESS_READ_WRITE : tlm::tlm_dmi
• DMI_ACCESS_WRITE : tlm::tlm_dmi
• dmi_cb : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• dmi_func_type : tlm_utils::callback_binder_bw< TYPES > , tlm_utils::callback_binder_fw< TYPES >
• dmi_type : SimpleLTInitiator1_dmi , SimpleLTInitiator2_dmi , SimpleLTInitiator3_dmi , SimpleLTInitiator_ext
• dnHigh : AUXU
• dnLow : AUXU
• do_binding() : tlm::tlm_transport_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• doBroadcastSignal() : SMMUProcess
• doCalibrateClocks() : FreebsdAlphaSystem
• doCkpt : DistIface::Sync
• doDelay() : SMMUProcess
• doDisplacementState() : X86ISA::Decoder
• doDmaDataRead() : IdeDisk
• doDmaDataWrite() : IdeDisk
• doDmaRead() : IdeDisk
• doDmaTransfer() : IdeDisk
• doDmaWrite() : IdeDisk
• doDRAMAccess() : DRAMCtrl
• doExit : DistIface::Sync
• doFastWrites : Cache
• doFromCacheState() : X86ISA::Decoder
• doFunctionalAccess() : Shader
• doImmediateState() : X86ISA::Decoder
• doing_local : MultiperspectivePerceptron
• doing_recency : MultiperspectivePerceptron
• doInit() : Stats::DistBase< Derived, Stor > , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor >
• doInstCommitAccounting() : Minor::Execute
• doInt() : ItsCommand
• doL0LongDescEvent : ArmISA::TableWalker
• doL0LongDescriptorWrapper() : ArmISA::TableWalker
• doL1DescEvent : ArmISA::TableWalker
• doL1Descriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doL1DescriptorWrapper() : ArmISA::TableWalker
• doL1LongDescEvent : ArmISA::TableWalker
• doL1LongDescriptorWrapper() : ArmISA::TableWalker
• doL2DescEvent : ArmISA::TableWalker
• doL2Descriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doL2DescriptorWrapper() : ArmISA::TableWalker
• doL2LongDescEvent : ArmISA::TableWalker
• doL2LongDescriptorWrapper() : ArmISA::TableWalker
• doL3LongDescEvent : ArmISA::TableWalker
• doL3LongDescriptorWrapper() : ArmISA::TableWalker
• doLongDescriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doLongDescriptorWrapper() : ArmISA::TableWalker
• domain : ArmISA::AbortFault< T > , ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor , ArmISA::TlbEntry
• DOMAIN_ID : EnergyCtrl
• domainFaults : ArmISA::TLB
• DomainID : DVFSHandler
• domainID() : DVFSHandler , EnergyCtrl
• DomainID : SrcClockDomain
• domainID() : SrcClockDomain
• domainIDIndexToRead : EnergyCtrl
• domainIDList : DVFSHandler
• domainIDToSet : DVFSHandler::UpdateEvent
• DomainLL : ArmISA::ArmFault
• Domains : DVFSHandler
• domains : DVFSHandler , ThermalModel
• DomainType : ArmISA::TlbEntry
• domatch() : ObjectMatch
• doMigrate : EventQueue::ScopedMigration
• doMMIOAccess() : BaseKvmCPU
• doMmuRegRead() : SparcISA::TLB , X86ISA::GpuTLB
• doMmuRegWrite() : SparcISA::TLB , X86ISA::GpuTLB
• doModRM() : X86ISA::EmulEnv
• doModRMState() : X86ISA::Decoder
• doMonitor() : AddressMonitor
• done : _cl_event , ChunkGenerator , DmaReadFifo::DmaDoneEvent , test , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , UFSHostDevice::SCSIResumeInfo , UFSHostDevice::taskStart , UFSHostDevice::transferStart
• doneEvent() : DistEtherLink::RxLink , DistEtherLink::TxLink , EtherLink::Link
• doneIds : GpuDispatcher
• doneSeqNum : TimeBufStruct< Impl >::commitComm , TimeBufStruct< Impl >::decodeComm
• doneSquashing : ROB< Impl >
• doneTargCalc() : BaseDynInst< Impl >
• dont_initialize() : sc_core::sc_module , sc_core::sc_spawn_options
• dontInitialize() : sc_gem5::Process
• doOneByteOpcodeState() : X86ISA::Decoder
• doOp() : ArmISA::FpOp
• doPrefixState() : X86ISA::Decoder
• doProcessEvent : ArmISA::TableWalker
• doRead() : ItsProcess , SMMUProcess
• doReadCD() : SMMUTranslationProcess
• doReadConfig() : SMMUTranslationProcess
• doReadPTE() : SMMUTranslationProcess
• doReadSTE() : SMMUTranslationProcess
• doResetState() : X86ISA::Decoder
• doRetry() : GarnetSyntheticTraffic
• doRxDmaRead() : NSGigE
• doRxDmaWrite() : NSGigE
• doSemaphoreDown() : SMMUProcess
• doSemaphoreUp() : SMMUProcess
• doService() : PCEventQueue
• doSIBState() : X86ISA::Decoder
• doSleep() : SMMUProcess
• doSmReturn() : ComputeUnit
• doSquash() : DefaultFetch< Impl > , DefaultRename< Impl > , InstructionQueue< Impl > , ROB< Impl >
• doStep() : ThermalModel
• doStopSync : DistIface::Sync
• doSyscall() : Process , SyscallDesc
• doThreeByte0F38OpcodeState() : X86ISA::Decoder
• doThreeByte0F3AOpcodeState() : X86ISA::Decoder
• doTimingSupplyResponse() : Cache
• doTwoByteOpcodeState() : X86ISA::Decoder
• doTxDmaRead() : NSGigE
• doTxDmaWrite() : NSGigE
• doubleBinSize() : Histogram
• DoubleFault() : X86ISA::DoubleFault
• doVex2Of2State() : X86ISA::Decoder
• doVex2Of3State() : X86ISA::Decoder
• doVex3Of3State() : X86ISA::Decoder
• doVexOpcodeState() : X86ISA::Decoder
• doWaitForSignal() : SMMUProcess
• down_flag : VncInput::KeyEventMessage
• downCounter : CountedExitEvent
• downgrade() : StoreTrace
• downstreamPending : MSHR
• doWrite() : ItsProcess , SMMUProcess
• doWritebacks() : BaseCache , Cache , NoncoherentCache
• doWritebacksAtomic() : BaseCache , Cache , NoncoherentCache
• dp : ArmISA::PMU
• dpBypassLength() : ComputeUnit
• dpBypassPipeLength : ComputeUnit
• DPG0 : Gicv3Redistributor
• DPG1NS : Gicv3Redistributor
• DPG1S : Gicv3Redistributor
• dport() : Net::TcpHdr , Net::UdpHdr
• dprintf() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , SparcISA::StackTrace , Trace::Logger , X86ISA::StackTrace
• dprintf_flag() : Trace::Logger
• drain() : ArchTimer , ArmISA::TableWalker , AtomicSimpleCPU , BaseKvmCPU , BasePixelPump::PixelEvent , BaseTrafficGen , BaseXBar::Layer< SrcType, DstType > , CopyEngine::CopyEngineChannel , CxxConfigManager , DefaultCommit< Impl > , DefaultFetch< Impl >::Stalls , DistIface , DmaCallback , DmaPort , DmaReadFifo , Drainable , DRAMCtrl , DRAMSim2 , FlashDevice , FullO3CPU< Impl > , GicV2 , Gicv3Its , IGbE , Minor::Execute , Minor::Pipeline , MinorCPU , MuxingKvmGic , PacketQueue , Process , QoS::MemSinkCtrl , Queue< Entry > , RubyPort , SimObject , SimpleMemory , SMMUv3 , SMMUv3SlaveInterface , TimingSimpleCPU , UFSHostDevice
• draina : PAL
• Drainable() : Drainable
• drainableCount() : DrainManager
• DrainAllInsts : Minor::Execute
• drainComplete() : DistIface::Sync
• DrainCurrentInst : Minor::Execute
• DrainHaltFetch : Minor::Execute
• drainImminent : DefaultCommit< Impl >
• draining() : DistIface::SyncEvent
• DrainManager : Drainable , DrainManager
• drainPending : DefaultCommit< Impl >
• drainResume() : ArchTimer , ArmISA::PMU , ArmISA::TableWalker , ArmISA::TLB , AtomicSimpleCPU , BaseKvmCPU , BasePixelPump::PixelEvent , CopyEngine::CopyEngineChannel , CxxConfigManager , DefaultCommit< Impl > , DefaultFetch< Impl > , DistIface , Drainable , DRAMCtrl , FullO3CPU< Impl > , GicV2 , HDLcd , IGbE , Minor::Execute , Minor::Pipeline , MinorCPU , MuxingKvmGic , NSGigE , RubySystem , Sinic::Device , System , TimingSimpleCPU
• drainSanityCheck() : BPredUnit , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , ROB< Impl >
• drainStall() : DefaultFetch< Impl >
• drainState() : Drainable
• DrainState : Minor::Execute
• drainState : Minor::Execute::ExecuteThreadInfo
• dram : DRAMCtrl::DRAMStats
• DRAMCtrl() : DRAMCtrl
• DramGen() : DramGen
• DRAMPacket() : DRAMCtrl::DRAMPacket
• DRAMPacketQueue : DRAMCtrl
• DRAMPower() : DRAMPower
• DramRotGen() : DramRotGen
• dramsim : DRAMSim2Wrapper
• DRAMSim2() : DRAMSim2
• DRAMSim2Wrapper() : DRAMSim2Wrapper
• DRAMStats() : DRAMCtrl::DRAMStats
• dre : StreamTableEntry
• dRegCount : HsaKernelInfo , HsaQueueEntry
• drir : TsunamiCChip
• drive : CommandReg
• driveID : IdeDisk
• driver : GpuDispatcher , VirtIODeviceBase
• driver_ok : VirtIODeviceBase
• drivers : Process
• dropFetch : Wavefront
• droppedPackets : EtherDevice
• dropPriority() : Gicv3CPUInterface
• drqBytesLeft : IdeDisk
• DS : Gicv3Distributor
• ds : X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED , X86ISA::RemoteGDB::X86GdbRegCache
• dse : MC146818
• dsize : aout_exechdr , ecoff_aouthdr
• dst : instr , Net::EthHdr , Net::Ip6Hdr , Net::IpHdr
• DST_BITS : Request
• dst_inport_dirn : LinkEntry
• DST_POC : Request
• DST_POU : Request
• dst_reg : GPUDynInst
• dst_reg_vec : GPUDynInst
• dstIs32b : ArmISA::SveElemCountOp
• dstIsVec : ArmISA::SveElemCountOp
• dstOptAddr() : Net::Ip6Opt
• dstOptExt() : Net::Ip6Hdr
• dstOptLength() : Net::Ip6Opt
• dstOpts : Net::ip6_opt_hdr
• dstOptType() : Net::Ip6Opt
• dstRegOpDist : Wavefront
• dtb : CheckerCPU , FullO3CPU< Impl > , SimpleThread
• DtbAcvFault() : AlphaISA::DtbAcvFault
• DtbAlignmentFault() : AlphaISA::DtbAlignmentFault
• DtbFault() : AlphaISA::DtbFault
• DtbFile() : DtbFile
• DtbPageFault() : AlphaISA::DtbPageFault
• DTBWaitResponse : BaseSimpleCPU
• DTE : ItsProcess
• DTickEvent() : TimingSimpleCPU::DcachePort::DTickEvent
• dTLB() : LSQUnit< Impl >
• DTLBIALL() : ArmISA::DTLBIALL
• DTLBIASID() : ArmISA::DTLBIASID
• DTLBIMVA() : ArmISA::DTLBIMVA
• DTLBPort() : ComputeUnit::DTLBPort
• dToE : Minor::Pipeline
• DumbTOD() : DumbTOD
• dummy : FrameBuffer , PowerISA::ISA , X86ISA::Decoder
• dummyBwIf : ClockRateControlInitiatorSocket , SignalInterruptInitiatorSocket
• DummyChecker() : DummyChecker
• dummyDevice : ArmISA::ISA
• dummyInst : ROB< Impl >
• DummyISADevice() : ArmISA::DummyISADevice
• dump() : ActivityRecorder , ArmKvmCPU , ArmV8KvmCPU , BaseDynInst< Impl > , BaseKvmCPU , BPredUnit , DependencyGraph< DynInstPtr > , DistEtherLink::Link , EtherBus , EtherDump , EtherLink::Link , EtherTapBase , Event , EventQueue , FunctionProfile , FUPool , IniFile , IniFile::Section , PCEventQueue , ProfileNode , sc_core::sc_fifo< T > , sc_core::sc_object , sc_dt::sc_fxcast_switch , sc_dt::sc_fxnum , sc_dt::sc_fxnum_bitref , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_bitref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxtype_params , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_length_param , sc_dt::sc_signed , sc_dt::sc_unsigned , sc_dt::scfx_params , sc_dt::scfx_rep , sc_gem5::Object , sc_gem5::ScSignalBaseT< T, WRITER_POLICY > , Stats::StatEvent , StoreSet , Trace::ExeTracerRecord , Trace::InstPBTraceRecord , Trace::InstRecord , Trace::IntelTraceRecord , Trace::Logger , Trace::NativeTraceRecord , Trace::TarmacBaseRecord , Trace::TarmacParserRecord , Trace::TarmacTracerRecord , Trie< Key, Value > , Trie< Key, Value >::Node , VirtDescriptor , VirtQueue , X86KvmCPU
• dump_status() : MultiSocketSimpleSwitchAT
• dumpAll() : SparcISA::TLB , X86ISA::GpuTLB
• dumpAllInput() : Minor::Fetch2
• dumpAndExit() : Checker< Impl > , CheckerCPU
• dumpChain() : VirtDescriptor
• dumpCount : Stats::Hdf5
• dumpDebugRegs() : X86KvmCPU
• dumpDmesg() : LinuxArmSystem
• dumpFpuRegs() : X86KvmCPU
• dumpFuncProfile() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , O3ThreadState< Impl > , SimpleThread , ThreadContext , ThreadState
• dumpHistory() : DefaultRename< Impl >
• dumpInsts() : Checker< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
• dumpIntRegs() : X86KvmCPU
• dumpKvmStateCoProc() : ArmKvmCPU
• dumpKvmStateCore() : ArmKvmCPU
• dumpKvmStateMisc() : ArmKvmCPU
• dumpKvmStateVFP() : ArmKvmCPU
• dumpLists() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• dumpMap() : SimpleAddressMap
• dumpMsg() : VirtIO9PBase
• dumpMSRs() : X86KvmCPU
• dumpPacket() : EtherDump
• dumpSettings() : HDLcd::DmaEngine , HDLcd::PixelPump
• dumpSpecRegs() : X86KvmCPU
• DumpStatsPCEvent() : DumpStatsPCEvent
• dumpStatsPCEvent : LinuxArmSystem
• DumpStatsPCEvent64() : DumpStatsPCEvent64
• dumpTrie() : TrieTestData
• dumpVCpuEvents() : X86KvmCPU
• dumpXCRs() : X86KvmCPU
• dumpXSave() : X86KvmCPU
• duplicateReqRemoved : SMMUv3SlaveInterface
• duplicateReqs : SMMUv3SlaveInterface
• duration : BaseGen
• duty_cycle() : sc_core::sc_clock
• dv : MC146818
• DVFS_DOMAINID_AT_INDEX : EnergyCtrl
• DVFS_HANDLER_STATUS : EnergyCtrl
• DVFS_HANDLER_TRANS_LATENCY : EnergyCtrl
• DVFS_NUM_DOMAINS : EnergyCtrl
• DVFS_Update_Pri : EventBase
• DVFSHandler() : DVFSHandler
• dvfsHandler : DVFSHandler::UpdateEvent , EnergyCtrl
• dWord0 : UFSHostDevice::LUNInfo , UFSHostDevice::UTPTransferReqDesc::RequestDescHeader , UFSHostDevice::UTPUPIUHeader
• dWord1 : UFSHostDevice::LUNInfo , UFSHostDevice::UTPTransferReqDesc::RequestDescHeader , UFSHostDevice::UTPUPIUHeader
• dWord2 : UFSHostDevice::UTPTransferReqDesc::RequestDescHeader , UFSHostDevice::UTPUPIUHeader
• dWord3 : UFSHostDevice::UTPTransferReqDesc::RequestDescHeader
• dyn_expr : MathExprPowerModel
• dynamic() : sc_core::sc_process_handle , sc_gem5::Process
• Dynamic : sc_gem5::Sensitivity
• DYNAMIC_DATA : Packet
• dynamic_id_count : GPUStaticInst
• dynamicGMemInstrCnt : ComputeUnit
• dynamicLMemInstrCnt : ComputeUnit
• dynamicPower : PowerModel , PowerModelState
• dynamicSenseMethod : sc_gem5::Event
• dynamicSenseThread : sc_gem5::Event
• DynamicSensitivity() : sc_gem5::DynamicSensitivity
• dynamicSensitivity : sc_gem5::Process
• DynamicSensitivityEvent() : sc_gem5::DynamicSensitivityEvent
• DynamicSensitivityEventAndList() : sc_gem5::DynamicSensitivityEventAndList
• DynamicSensitivityEventOrList() : sc_gem5::DynamicSensitivityEventOrList
• DynInst : DefaultFetch< Impl > , O3CPUImpl
• DynInstConstPtr : ElasticTrace , MemDepUnit< MemDepPred, Impl > , O3CPUImpl
• DynInstPtr : BaseDynInst< Impl > , Checker< Impl > , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultDecodeDefaultRename< Impl > , DefaultFetch< Impl > , DefaultFetchDefaultDecode< Impl > , DefaultIEW< Impl > , DefaultIEWDefaultCommit< Impl > , DefaultRename< Impl > , DefaultRenameDefaultIEW< Impl > , ElasticTrace , FullO3CPU< Impl > , InstructionQueue< Impl > , IssueStruct< Impl > , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , O3CPUImpl , ROB< Impl > , TimeBufStruct< Impl >