- d -

• data() : AlphaISA::RemoteGDB::AlphaGdbRegCache
• Data() : Arguments::Data
• data() : ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , BaseGdbRegCache , DmaReadFifo::DmaDoneEvent , ImageFileData , LSQUnit< Impl >::SQEntry , MipsISA::RemoteGDB::MipsGdbRegCache , Net::IpOpt , Net::TcpOpt , PowerISA::RemoteGDB::PowerGdbRegCache , RiscvISA::RemoteGDB::RiscvGdbRegCache , SparcISA::RemoteGDB::SPARC64GdbRegCache , SparcISA::RemoteGDB::SPARCGdbRegCache , Stats::DistBase< Derived, Stor > , Stats::DistProxy< Stat > , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Stats::VectorProxy< Stat > , Terminal , VncServer , X86ISA::RemoteGDB::AMD64GdbRegCache , X86ISA::RemoteGDB::X86GdbRegCache
• data_read() : sc_core::sc_fifo_out< T >
• data_read_event() : sc_core::sc_fifo< T > , sc_core::sc_fifo_nonblocking_out_if< T > , sc_core::sc_fifo_out< T >
• data_written() : sc_core::sc_fifo_in< T >
• data_written_event() : sc_core::sc_fifo< T > , sc_core::sc_fifo_in< T > , sc_core::sc_fifo_nonblocking_in_if< T >
• DataAbort() : ArmISA::DataAbort
• dataAvailable() : Pl011 , SerialDevice , SerialNullDevice , SimpleUart , Terminal , Uart8250 , Uart
• DataBlock() : DataBlock
• dataCallback() : DMASequencer
• dataDynamic() : Packet
• DataEvent() : Terminal::DataEvent , VncServer::DataEvent
• DataImmOp() : ArmISA::DataImmOp
• dataMasterId() : BaseCPU
• DataPort() : ComputeUnit::DataPort , Gicv3Its::DataPort
• DataRegOp() : ArmISA::DataRegOp
• DataRegRegOp() : ArmISA::DataRegRegOp
• dataStatic() : Packet
• dataStaticConst() : Packet
• DataTranslation() : DataTranslation< ExecContextPtr >
• DataWrap() : Stats::DataWrap< Derived, InfoProxyType >
• DataWrapVec() : Stats::DataWrapVec< Derived, InfoProxyType >
• DataWrapVec2d() : Stats::DataWrapVec2d< Derived, InfoProxyType >
• DataX1Reg2ImmOp() : ArmISA::DataX1Reg2ImmOp
• DataX1RegImmOp() : ArmISA::DataX1RegImmOp
• DataX1RegOp() : ArmISA::DataX1RegOp
• DataX2RegImmOp() : ArmISA::DataX2RegImmOp
• DataX2RegOp() : ArmISA::DataX2RegOp
• DataX3RegOp() : ArmISA::DataX3RegOp
• DataXCondCompImmOp() : ArmISA::DataXCondCompImmOp
• DataXCondCompRegOp() : ArmISA::DataXCondCompRegOp
• DataXCondSelOp() : ArmISA::DataXCondSelOp
• DataXERegOp() : ArmISA::DataXERegOp
• DataXImmOnlyOp() : ArmISA::DataXImmOnlyOp
• DataXImmOp() : ArmISA::DataXImmOp
• DataXSRegOp() : ArmISA::DataXSRegOp
• date() : Time
• dbg_vtophys() : BaseSimpleCPU , CheckerCPU , MinorCPU
• dbgHeader() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• dbl() : ArmISA::FpOp
• dblHi() : ArmISA::FpOp
• dblLow() : ArmISA::FpOp
• DcachePort() : LSQ< Impl >::DcachePort , Minor::LSQ::DcachePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort
• dcacheRecvTimingResp() : TraceCPU
• dcacheRetryRecvd() : TraceCPU
• DCPTEntry() : DeltaCorrelatingPredictionTables::DCPTEntry
• DCPTPrefetcher() : DCPTPrefetcher
• deactivateIRQ() : Gicv3CPUInterface , Gicv3Distributor , Gicv3Redistributor
• deactivateStage() : ActivityRecorder , DefaultIEW< Impl > , FullO3CPU< Impl >
• deactivateThread() : DefaultCommit< Impl > , DefaultFetch< Impl > , FullO3CPU< Impl >
• deallocate() : CacheMemory , MSHR , PerfectCacheMemory< ENTRY > , Queue< Entry > , TBETable< ENTRY > , WriteQueueEntry
• deallocateContext() : BaseKvmCPU
• deassertInt() : Gicv3
• deassertSPI() : Gicv3Distributor
• debug() : tlm::circular_buffer< T > , tlm::tlm_fifo< T > , tlm::tlm_fifo_debug_if< T >
• DebugBreakEvent() : DebugBreakEvent
• debugCounter() : ArmISA::PMU::CounterState
• DebugException() : X86ISA::DebugException
• debugFunc() : GenericISA::M5DebugFault , GenericISA::M5FatalFault , GenericISA::M5HackFaultBase< Base > , GenericISA::M5InformFaultBase< Base > , GenericISA::M5PanicFault , GenericISA::M5WarnFaultBase< Base >
• debugPrint() : Check
• DebugPrintkEvent() : Linux::DebugPrintkEvent
• debugVerify() : EventQueue
• dec() : Stats::AvgStor , Stats::StatStor
• dec_use_count() : tlm_utils::instance_specific_extension_container
• DECL_BIN_OP_T() : sc_dt::sc_fxnum_fast , sc_dt::sc_fxval_fast
• declare_router() : FaultModel
• decode() : AlphaISA::Decoder , ArmISA::Decoder , DefaultDecode< Impl > , GenericISA::BasicDecodeCache , HsailISA::Decoder
• Decode() : Minor::Decode
• decode() : MipsISA::Decoder , MultiSocketSimpleSwitchAT , PowerISA::Decoder , RiscvISA::Decoder , SimpleAddressMap , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS > , SparcISA::Decoder , X86ISA::Decoder
• decodeAddr() : DRAMCtrl
• decodeAddress() : GenericPciHost
• decodeCoProcReg() : ArmKvmCPU
• decodeInst() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• decodeInsts() : DefaultDecode< Impl >
• decodePolicyName() : SMMUv3BaseCache
• decodePrologue() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• Decoder() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• DecoderFaultInst() : DecoderFaultInst
• decoderFlavour() : ArmISA::ISA
• decodeSave() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• decodeStack() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• DecodeThreadInfo() : Minor::Decode::DecodeThreadInfo
• decodeVFPCtrlReg() : ArmKvmCPU
• decompress() : BaseCacheCompressor , DictionaryCompressor< T > , DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits > , DictionaryCompressor< T >::MaskedPattern< mask > , DictionaryCompressor< T >::MaskedValuePattern< value, mask > , DictionaryCompressor< T >::Pattern , DictionaryCompressor< T >::RepeatedValuePattern< RepT > , DictionaryCompressor< T >::UncompressedPattern , MultiCompressor , PerfectCompressor
• decompressValue() : DictionaryCompressor< T >
• decrease() : CircularQueue< T >
• decreaseRefCounter() : LdsState
• decref() : RefCounted , sc_gem5::Process
• decrement_credit() : OutputUnit , OutVcState
• decrementable() : CircularQueue< T >::iterator
• decrNumPinnedWrites() : PhysRegId
• decrNumPinnedWritesToComplete() : PhysRegId
• decrTos() : ReturnAddrStack
• deep_copy_from() : tlm::tlm_generic_payload
• default_event() : sc_core::sc_event_queue , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_interface , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_gem5::ScSignalBaseT< T, WRITER_POLICY >
• default_handler() : sc_core::sc_report_handler
• default_name() : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• default_sign() : sc_dt::sc_signed , sc_dt::sc_unsigned
• default_value() : sc_dt::sc_context< T >
• DefaultBTB() : DefaultBTB
• DefaultCommit() : DefaultCommit< Impl >
• DefaultDecode() : DefaultDecode< Impl >
• defaultEvent() : sc_gem5::ScSignalBase
• DefaultFetch() : DefaultFetch< Impl >
• DefaultIEW() : DefaultIEW< Impl >
• defaultOnCompletion() : X86ISA::IntMasterPort< Device >
• DefaultRename() : DefaultRename< Impl >
• DefaultReportMessages() : sc_gem5::DefaultReportMessages
• deferMemInst() : InstructionQueue< Impl >
• DeferredPacket() : Bridge::DeferredPacket , PacketQueue::DeferredPacket , QueuedPrefetcher::DeferredPacket , SerialLink::DeferredPacket , SimpleMemory::DeferredPacket
• deferredPacketReady() : PacketQueue
• deferredPacketReadyTime() : PacketQueue
• define() : Label
• defined() : Label
• dehash() : SkewedAssociative
• del() : RefCountingPtr< T >
• delay() : MSHR , MSHRQueue , WriteAllocator
• delayed() : sc_gem5::Scheduler
• delayedStartup() : KvmVM
• delayHead() : MessageBuffer
• delayIntEvent() : IGbE
• DelayQueueEntry() : BOPPrefetcher::DelayQueueEntry
• delayQueueEventWrapper() : BOPPrefetcher
• delayReq() : MemDelay , SimpleMemDelay
• delayResp() : MemDelay , SimpleMemDelay
• DelaySlotPCState() : GenericISA::DelaySlotPCState< MachInst >
• DelaySlotUPCState() : GenericISA::DelaySlotUPCState< MachInst >
• delaySnoopResp() : MemDelay
• delBp() : Iris::ThreadContext
• delChildEvent() : sc_gem5::Object
• delete_top() : tlm_utils::time_ordered_list< PAYLOAD >
• deleteData() : Packet
• deleteIndirectInfo() : IndirectPredictor , SimpleIndirectPredictor
• deleteObjects() : CxxConfigManager
• deleteReqs() : WholeTranslationState
• deleteRequest() : LSQ< Impl >::LSQSenderState , Minor::LSQ::StoreBuffer
• delFromEvent() : sc_gem5::DynamicSensitivity , sc_gem5::Sensitivity , sc_gem5::StaticSensitivity
• deliverInterrupts() : X86KvmCPU
• delSensitivity() : sc_gem5::Event
• delta_count() : sc_core::sc_simcontext
• delta_list() : tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list
• DeltaCorrelatingPredictionTables() : DeltaCorrelatingPredictionTables
• DeltaPattern() : DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >
• demapAll() : SparcISA::TLB
• demapContext() : SparcISA::TLB
• demapDataPage() : BaseDynInst< Impl > , CheckerCPU , FullO3CPU< Impl > , Minor::ExecContext , SimpleThread
• demapInstPage() : BaseDynInst< Impl > , CheckerCPU , FullO3CPU< Impl > , Minor::ExecContext , SimpleThread
• demapPage() : AlphaISA::TLB , ArmISA::TLB , BaseDynInst< Impl > , BaseTLB , CheckerCPU , ExecContext , FullO3CPU< Impl > , Iris::TLB , Minor::ExecContext , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB , SimpleExecContext , SimpleThread , SparcISA::TLB , X86ISA::GpuTLB , X86ISA::TLB
• DependencyEntry() : DependencyEntry< DynInstPtr >
• DependencyGraph() : DependencyGraph< DynInstPtr >
• deprecatedConstructor() : sc_gem5::Module
• depsReady() : EmbeddedPyBind
• dequeue() : MessageBuffer , SimpleMemory , WireBuffer
• dequeueCallback() : NetworkInterface
• dereferenceable() : CircularQueue< T >::iterator
• DerivedClockDomain() : DerivedClockDomain
• DerivO3CPU() : DerivO3CPU
• desc() : Debug::Flag
• Desc() : DistIface::RecvScheduler::Desc
• desc() : Stats::DataWrap< Derived, InfoProxyType >
• descBase() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• DescCache() : IGbE::DescCache< T >
• descHead() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• deschedule() : BaseGlobalEvent , EventManager , EventQueue , LdsState::TickEvent , sc_gem5::ScEvent , sc_gem5::Scheduler
• descheduleDeadlockEvent() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer
• descheduleInstCommitEvent() : BaseRemoteGDB
• descheduleInstCountEvent() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• deschedulePowerGatingEvent() : BaseCPU
• descInBlock() : IGbE::TxDescCache
• descLeft() : IGbE::DescCache< T >
• descLen() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• descr() : PCEvent
• describe() : X86ISA::PageFault , X86ISA::X86FaultBase
• description() : BaseGlobalEvent , CountedExitEvent , CPUProgressEvent , DebugBreakEvent , DefaultFetch< Impl >::FinishTranslationEvent , EndQuiesceEvent , Event , EventFunctionWrapper , EventWrapper< T, F > , GlobalSimLoopExitEvent , GlobalSyncEvent , InstructionQueue< Impl >::FUCompletion , Intel8254Timer::Counter::CounterEvent , LocalSimLoopExitEvent , LSQUnit< Impl >::WritebackEvent , MC146818::RTCEvent , MC146818::RTCTickEvent , SMMUDeviceRetryEvent , Stats::StatEvent , TimingSimpleCPU::DcachePort::DTickEvent , TimingSimpleCPU::IcachePort::ITickEvent , TimingSimpleCPU::IprEvent , TimingSimpleCPU::TimingCPUPort::TickEvent , Trace::TarmacParserRecord::TarmacParserRecordEvent , X86ISA::GpuTLB::TLBEvent
• DescriptorBase() : ArmISA::TableWalker::DescriptorBase
• descSize() : iGbReg::Regs::RCTL
• descTail() : IGbE::DescCache< T > , IGbE::RxDescCache , IGbE::TxDescCache
• descUnused() : IGbE::DescCache< T >
• descUsed() : IGbE::DescCache< T >
• deskew() : SkewedAssociative
• destRegIdx() : BaseDynInst< Impl > , StaticInst
• destroyPacket() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• destroyStreams() : ProtoInputStream
• destruct() : sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer
• detach() : ArmISA::PMU::CounterState , BaseRemoteGDB , EtherTapStub , PerfKvmCounter , Terminal , VncServer
• detachEvent() : ArmISA::PMU::PMUEvent
• determineArch() : ElfObject
• determineOpSys() : ElfObject
• Device() : RealViewCtrl::Device , Sinic::Device
• deviceEventQueue() : BaseKvmCPU
• DeviceFDEntry() : DeviceFDEntry
• DeviceInterface() : PciHost::DeviceInterface
• DeviceNotAvailable() : X86ISA::DeviceNotAvailable
• deviceOutOfRange() : Gicv3Its , ItsCommand
• devIntrChangeMask() : NSGigE , Sinic::Device
• devIntrClear() : NSGigE , Sinic::Device
• devIntrPost() : NSGigE , Sinic::Device
• DictionaryCompressor() : DictionaryCompressor< T >
• DiodDataEvent() : VirtIO9PDiod::DiodDataEvent
• dir() : CheckpointIn
• DirectedGenerator() : DirectedGenerator
• directory() : OutputDirectory
• DirectoryMemory() : DirectoryMemory
• dirty() : ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• disable() : ArmISA::PMU::PMUEvent , ArmISA::PMU::RegularEvent , ArmISA::PMU::SWIncrementEvent , Debug::AllFlags , Debug::CompoundFlag , Debug::Flag , Debug::SimpleFlag , PollEvent , sc_core::sc_process_handle , sc_gem5::Process
• disable_cb_bind() : tlm_utils::multi_init_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• disableAll() : Debug::SimpleFlag , ListenSocket
• disabled() : PerfKvmCounterConfig , sc_gem5::Process
• disabledFault() : ArmISA::ArmStaticInst
• disableMemAccess() : Minor::LSQ::LSQRequest
• disableMemSlot() : KvmVM
• disableSanityCheck() : PacketQueue
• disarm() : BaseKvmTimer , PerfKvmTimer , PosixKvmTimer
• disassemble() : AddrOperandBase , CRegOperand , DRegOperand , FunctionRefOperand , GPUDynInst , GPUStaticInst , ImmOperand< T > , LabelOperand , ListOperand , NoRegAddrOperand , PowerISA::PCDependentDisassembly , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T > , SRegOperand , StaticInst
• discard() : ItsCommand , LSQ< Impl >::LSQRequest , sc_dt::scfx_string
• discardFetch() : Wavefront
• discardPendingSignal() : BaseKvmCPU
• discardSenderState() : LSQ< Impl >::LSQRequest
• DiskImage() : DiskImage
• dispatch() : DefaultIEW< Impl >
• dispatch_workgroups() : Shader
• dispatchAccess() : IdeController
• DispatchEntry() : ItsCommand::DispatchEntry
• dispatchInsts() : DefaultIEW< Impl >
• Display() : Display
• display_error() : tlm_utils::convenience_socket_base , tlm_utils::convenience_socket_cb_holder
• display_statistics() : sc_core::sc_mempool
• display_warning() : tlm_utils::convenience_socket_base , tlm_utils::convenience_socket_cb_holder
• DisplayTimings() : DisplayTimings
• displayTimings() : HDLcd
• distanceFromTrigger() : PIFPrefetcher::CompactorEntry
• DistBase() : Stats::DistBase< Derived, Stor >
• DistEtherLink() : DistEtherLink
• DistHeaderPkt() : DistHeaderPkt
• DistIface() : DistIface
• DistInfoProxy() : Stats::DistInfoProxy< Stat >
• DistParams() : Stats::DistParams
• DistPrint() : Stats::DistPrint
• DistProxy() : Stats::DistProxy< Stat >
• Distribution() : Stats::Distribution
• DistStor() : Stats::DistStor
• divide_by_ten() : sc_dt::scfx_rep
• DivideError() : X86ISA::DivideError
• dmaAction() : DmaPort
• dmaAddr() : GenericPciHost , PciHost::DeviceInterface , PciHost , TsunamiPChip
• DmaCallback() : DmaCallback
• DmaDevice() : DmaDevice
• dmaDone() : DmaReadFifo , Pl111
• DmaDoneEvent() : DmaReadFifo::DmaDoneEvent
• DmaEngine() : HDLcd::DmaEngine
• dmaPending() : DmaDevice , DmaPort
• DmaPort() : DmaPort
• dmaPrdReadDone() : IdeDisk
• dmaRead() : DmaDevice
• dmaReadDone() : IdeDisk
• DmaReadFifo() : DmaReadFifo
• DmaReqState() : DmaPort::DmaReqState
• DMARequest() : DMARequest
• DMASequencer() : DMASequencer
• dmaWrite() : DmaDevice
• dmaWriteDone() : IdeDisk
• dmDrain() : Drainable
• dmDrainResume() : Drainable
• DmesgDumpEvent() : Linux::DmesgDumpEvent
• do_binding() : tlm::tlm_transport_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• doBroadcastSignal() : SMMUProcess
• doCalibrateClocks() : FreebsdAlphaSystem
• doDelay() : SMMUProcess
• doDisplacementState() : X86ISA::Decoder
• doDmaDataRead() : IdeDisk
• doDmaDataWrite() : IdeDisk
• doDmaRead() : IdeDisk
• doDmaTransfer() : IdeDisk
• doDmaWrite() : IdeDisk
• doDRAMAccess() : DRAMCtrl
• doFromCacheState() : X86ISA::Decoder
• doFunctionalAccess() : Shader
• doImmediateState() : X86ISA::Decoder
• doInit() : Stats::DistBase< Derived, Stor > , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor >
• doInstCommitAccounting() : Minor::Execute
• doInt() : ItsCommand
• doL0LongDescriptorWrapper() : ArmISA::TableWalker
• doL1Descriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doL1DescriptorWrapper() : ArmISA::TableWalker
• doL1LongDescriptorWrapper() : ArmISA::TableWalker
• doL2Descriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doL2DescriptorWrapper() : ArmISA::TableWalker
• doL2LongDescriptorWrapper() : ArmISA::TableWalker
• doL3LongDescriptorWrapper() : ArmISA::TableWalker
• doLongDescriptor() : ArmISA::TableWalker , ArmISA::TableWalker::WalkerState
• doLongDescriptorWrapper() : ArmISA::TableWalker
• domain() : ArmISA::TableWalker::DescriptorBase , ArmISA::TableWalker::L1Descriptor , ArmISA::TableWalker::L2Descriptor , ArmISA::TableWalker::LongDescriptor
• domainID() : DVFSHandler , SrcClockDomain
• domatch() : ObjectMatch
• doMMIOAccess() : BaseKvmCPU
• doMmuRegRead() : SparcISA::TLB , X86ISA::GpuTLB
• doMmuRegWrite() : SparcISA::TLB , X86ISA::GpuTLB
• doModRM() : X86ISA::EmulEnv
• doModRMState() : X86ISA::Decoder
• doMonitor() : AddressMonitor
• done() : ChunkGenerator , DmaReadFifo::DmaDoneEvent
• doneEvent() : DistEtherLink::RxLink
• doneTargCalc() : BaseDynInst< Impl >
• dont_initialize() : sc_core::sc_module , sc_core::sc_spawn_options
• dontInitialize() : sc_gem5::Process
• doOneByteOpcodeState() : X86ISA::Decoder
• doOp() : ArmISA::FpOp
• doPrefixState() : X86ISA::Decoder
• doRead() : ItsProcess , SMMUProcess
• doReadCD() : SMMUTranslationProcess
• doReadConfig() : SMMUTranslationProcess
• doReadPTE() : SMMUTranslationProcess
• doReadSTE() : SMMUTranslationProcess
• doResetState() : X86ISA::Decoder
• doRetry() : GarnetSyntheticTraffic
• doRxDmaRead() : NSGigE
• doRxDmaWrite() : NSGigE
• doSemaphoreDown() : SMMUProcess
• doSemaphoreUp() : SMMUProcess
• doService() : PCEventQueue
• doSIBState() : X86ISA::Decoder
• doSleep() : SMMUProcess
• doSmReturn() : ComputeUnit
• doSquash() : DefaultFetch< Impl > , DefaultRename< Impl > , InstructionQueue< Impl > , ROB< Impl >
• doStep() : ThermalModel
• doSyscall() : Process , SyscallDesc
• doThreeByte0F38OpcodeState() : X86ISA::Decoder
• doThreeByte0F3AOpcodeState() : X86ISA::Decoder
• doTimingSupplyResponse() : Cache
• doTwoByteOpcodeState() : X86ISA::Decoder
• doTxDmaRead() : NSGigE
• doTxDmaWrite() : NSGigE
• doubleBinSize() : Histogram
• DoubleFault() : X86ISA::DoubleFault
• doVex2Of2State() : X86ISA::Decoder
• doVex2Of3State() : X86ISA::Decoder
• doVex3Of3State() : X86ISA::Decoder
• doVexOpcodeState() : X86ISA::Decoder
• doWaitForSignal() : SMMUProcess
• downgrade() : StoreTrace
• doWrite() : ItsProcess , SMMUProcess
• doWritebacks() : BaseCache , Cache , NoncoherentCache
• doWritebacksAtomic() : BaseCache , Cache , NoncoherentCache
• dpBypassLength() : ComputeUnit
• dport() : Net::TcpHdr , Net::UdpHdr
• dprintf() : AlphaISA::StackTrace , ArmISA::StackTrace , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , SparcISA::StackTrace , Trace::Logger , X86ISA::StackTrace
• dprintf_flag() : Trace::Logger
• drain() : ArchTimer , ArmISA::TableWalker , AtomicSimpleCPU , BaseKvmCPU , BasePixelPump::PixelEvent , BaseTrafficGen , BaseXBar::Layer< SrcType, DstType > , CopyEngine::CopyEngineChannel , CxxConfigManager , DefaultCommit< Impl > , DistIface , DmaCallback , DmaPort , DmaReadFifo , Drainable , DRAMCtrl , DRAMSim2 , FlashDevice , FullO3CPU< Impl > , GicV2 , Gicv3Its , IGbE , Minor::Execute , Minor::Pipeline , MinorCPU , MuxingKvmGic , PacketQueue , Process , QoS::MemSinkCtrl , Queue< Entry > , RubyPort , SimObject , SimpleMemory , SMMUv3 , SMMUv3SlaveInterface , TimingSimpleCPU , UFSHostDevice
• Drainable() : Drainable
• drainableCount() : DrainManager
• drainComplete() : DistIface::Sync
• draining() : DistIface::SyncEvent
• DrainManager() : DrainManager
• drainResume() : ArchTimer , ArmISA::PMU , ArmISA::TableWalker , ArmISA::TLB , AtomicSimpleCPU , BaseKvmCPU , BasePixelPump::PixelEvent , CopyEngine::CopyEngineChannel , CxxConfigManager , DefaultCommit< Impl > , DefaultFetch< Impl > , DistIface , Drainable , DRAMCtrl , FullO3CPU< Impl > , GicV2 , HDLcd , IGbE , Minor::Execute , Minor::Pipeline , MinorCPU , MuxingKvmGic , NSGigE , RubySystem , Sinic::Device , System , TimingSimpleCPU
• drainSanityCheck() : BPredUnit , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , ROB< Impl >
• drainStall() : DefaultFetch< Impl >
• drainState() : Drainable
• DRAMCtrl() : DRAMCtrl
• DramGen() : DramGen
• DRAMPacket() : DRAMCtrl::DRAMPacket
• DRAMPower() : DRAMPower
• DramRotGen() : DramRotGen
• DRAMSim2() : DRAMSim2
• DRAMSim2Wrapper() : DRAMSim2Wrapper
• DRAMStats() : DRAMCtrl::DRAMStats
• dropPriority() : Gicv3CPUInterface
• dst() : Net::EthHdr , Net::Ip6Hdr , Net::IpHdr
• dstOptAddr() : Net::Ip6Opt
• dstOptExt() : Net::Ip6Hdr
• dstOptLength() : Net::Ip6Opt
• dstOptType() : Net::Ip6Opt
• DtbAcvFault() : AlphaISA::DtbAcvFault
• DtbAlignmentFault() : AlphaISA::DtbAlignmentFault
• DtbFault() : AlphaISA::DtbFault
• DtbFile() : DtbFile
• DtbPageFault() : AlphaISA::DtbPageFault
• DTickEvent() : TimingSimpleCPU::DcachePort::DTickEvent
• dTLB() : LSQUnit< Impl >
• DTLBIALL() : ArmISA::DTLBIALL
• DTLBIASID() : ArmISA::DTLBIASID
• DTLBIMVA() : ArmISA::DTLBIMVA
• DTLBPort() : ComputeUnit::DTLBPort
• DumbTOD() : DumbTOD
• DummyChecker() : DummyChecker
• DummyISADevice() : ArmISA::DummyISADevice
• dump() : ActivityRecorder , ArmKvmCPU , ArmV8KvmCPU , BaseDynInst< Impl > , BaseKvmCPU , BPredUnit , DependencyGraph< DynInstPtr > , EtherDump , Event , EventQueue , FunctionProfile , FUPool , IniFile , IniFile::Section , PCEventQueue , ProfileNode , sc_core::sc_fifo< T > , sc_core::sc_object , sc_dt::sc_fxcast_switch , sc_dt::sc_fxnum , sc_dt::sc_fxnum_bitref , sc_dt::sc_fxnum_fast , sc_dt::sc_fxnum_fast_bitref , sc_dt::sc_fxnum_fast_subref , sc_dt::sc_fxnum_subref , sc_dt::sc_fxtype_params , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::sc_length_param , sc_dt::sc_signed , sc_dt::sc_unsigned , sc_dt::scfx_params , sc_dt::scfx_rep , sc_gem5::Object , sc_gem5::ScSignalBaseT< T, WRITER_POLICY > , StoreSet , Trace::ExeTracerRecord , Trace::InstPBTraceRecord , Trace::InstRecord , Trace::IntelTraceRecord , Trace::Logger , Trace::NativeTraceRecord , Trace::TarmacBaseRecord , Trace::TarmacParserRecord , Trace::TarmacTracerRecord , Trie< Key, Value > , Trie< Key, Value >::Node , VirtDescriptor , VirtQueue , X86KvmCPU
• dump_status() : MultiSocketSimpleSwitchAT
• dumpAll() : SparcISA::TLB , X86ISA::GpuTLB
• dumpAllInput() : Minor::Fetch2
• dumpAndExit() : Checker< Impl > , CheckerCPU
• dumpChain() : VirtDescriptor
• dumpDebugRegs() : X86KvmCPU
• dumpDmesg() : LinuxArmSystem
• dumpFpuRegs() : X86KvmCPU
• dumpFuncProfile() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , O3ThreadState< Impl > , SimpleThread , ThreadContext , ThreadState
• dumpHistory() : DefaultRename< Impl >
• dumpInsts() : Checker< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
• dumpIntRegs() : X86KvmCPU
• dumpKvmStateCoProc() : ArmKvmCPU
• dumpKvmStateCore() : ArmKvmCPU
• dumpKvmStateMisc() : ArmKvmCPU
• dumpKvmStateVFP() : ArmKvmCPU
• dumpLists() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• dumpMap() : SimpleAddressMap
• dumpMsg() : VirtIO9PBase
• dumpMSRs() : X86KvmCPU
• dumpPacket() : EtherDump
• dumpSettings() : HDLcd::DmaEngine , HDLcd::PixelPump
• dumpSpecRegs() : X86KvmCPU
• DumpStatsPCEvent() : DumpStatsPCEvent
• DumpStatsPCEvent64() : DumpStatsPCEvent64
• dumpTrie() : TrieTestData
• dumpVCpuEvents() : X86KvmCPU
• dumpXCRs() : X86KvmCPU
• dumpXSave() : X86KvmCPU
• duty_cycle() : sc_core::sc_clock
• DVFSHandler() : DVFSHandler
• dynamic() : sc_core::sc_process_handle , sc_gem5::Process
• DynamicSensitivity() : sc_gem5::DynamicSensitivity
• DynamicSensitivityEvent() : sc_gem5::DynamicSensitivityEvent
• DynamicSensitivityEventAndList() : sc_gem5::DynamicSensitivityEventAndList
• DynamicSensitivityEventOrList() : sc_gem5::DynamicSensitivityEventOrList