gem5
v20.0.0.0
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#include <faults.hh>
Public Member Functions | |
DataAbort (Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, bool _stage2=false, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran) | |
ExceptionClass | ec (ThreadContext *tc) const override |
bool | routeToMonitor (ThreadContext *tc) const override |
bool | routeToHyp (ThreadContext *tc) const override |
uint32_t | iss () const override |
void | annotate (AnnotationIDs id, uint64_t val) override |
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AbortFault (Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, bool _stage2, ArmFault::TranMethod _tranMethod=ArmFault::UnknownTran) | |
bool | getFaultVAddr (Addr &va) const override |
void | invoke (ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr) override |
FSR | getFsr (ThreadContext *tc) const override |
uint8_t | getFaultStatusCode (ThreadContext *tc) const |
bool | abortDisable (ThreadContext *tc) override |
uint32_t | iss () const override |
bool | isStage2 () const override |
void | annotate (ArmFault::AnnotationIDs id, uint64_t val) override |
void | setSyndrome (ThreadContext *tc, MiscRegIndex syndrome_reg) override |
bool | isMMUFault () const |
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ArmFaultVals (ExtMachInst _machInst=0, uint32_t _iss=0) | |
FaultName | name () const override |
FaultStat & | countStat () override |
FaultOffset | offset (ThreadContext *tc) override |
FaultOffset | offset64 (ThreadContext *tc) override |
OperatingMode | nextMode () override |
uint8_t | armPcOffset (bool isHyp) override |
uint8_t | thumbPcOffset (bool isHyp) override |
uint8_t | armPcElrOffset () override |
uint8_t | thumbPcElrOffset () override |
bool | fiqDisable (ThreadContext *tc) override |
ExceptionClass | ec (ThreadContext *tc) const override |
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ArmFault (ExtMachInst _machInst=0, uint32_t _iss=0) | |
MiscRegIndex | getSyndromeReg64 () const |
MiscRegIndex | getFaultAddrReg64 () const |
void | invoke64 (ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr) |
void | update (ThreadContext *tc) |
ArmStaticInst * | instrAnnotate (const StaticInstPtr &inst) |
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virtual | ~FaultBase () |
Public Attributes | |
bool | isv |
uint8_t | sas |
uint8_t | sse |
uint8_t | srt |
uint8_t | cm |
bool | sf |
bool | ar |
Static Public Attributes | |
static const MiscRegIndex | FsrIndex = MISCREG_DFSR |
static const MiscRegIndex | FarIndex = MISCREG_DFAR |
static const MiscRegIndex | HFarIndex = MISCREG_HDFAR |
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static uint8_t | shortDescFaultSources [NumFaultSources] |
Encodings of the fault sources when the short-desc. More... | |
static uint8_t | longDescFaultSources [NumFaultSources] |
Encodings of the fault sources when the long-desc. More... | |
static uint8_t | aarch64FaultSources [NumFaultSources] |
Encodings of the fault sources in AArch64 state. More... | |
Additional Inherited Members | |
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enum | FaultSource { AlignmentFault = 0, InstructionCacheMaintenance, SynchExtAbtOnTranslTableWalkLL, SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, AccessFlagLL = TranslationLL + 4, DomainLL = AccessFlagLL + 4, PermissionLL = DomainLL + 4, DebugEvent = PermissionLL + 4, SynchronousExternalAbort, TLBConflictAbort, SynchPtyErrOnMemoryAccess, AsynchronousExternalAbort, AsynchPtyErrOnMemoryAccess, AddressSizeLL, PrefetchTLBMiss = AddressSizeLL + 4, PrefetchUncacheable, NumFaultSources, FaultSourceInvalid = 0xff } |
Generic fault source enums used to index into {short/long/aarch64}DescFaultSources[] to get the actual encodings based on the current register width state and the translation table format in use. More... | |
enum | AnnotationIDs { S1PTW, OVA, SAS, SSE, SRT, CM, OFA, SF, AR } |
enum | TranMethod { LpaeTran, VmsaTran, UnknownTran } |
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ArmFault::FaultVals | vals ("Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP) |
ArmFault::FaultVals | vals ("Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP) |
ArmFault::FaultVals | vals ("Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 4, 4, 4, 4, true, false, false, EC_HVC) |
ArmFault::FaultVals | vals ("Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP) |
ArmFault::FaultVals | vals ("Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP) |
ArmFault::FaultVals | vals ("Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_INVALID) |
ArmFault::FaultVals | vals ("Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 0, 0, 0, 0, false, false, false, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 2, 0, 0, false, false, false, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_INVALID) |
ArmFault::FaultVals | vals ("FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_INVALID) |
ArmFault::FaultVals | vals ("Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST) |
ArmFault::FaultVals | vals ("Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, false, false, false, EC_UNKNOWN) |
ArmFault::FaultVals | vals ("PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT) |
ArmFault::FaultVals | vals ("SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT) |
ArmFault::FaultVals | vals ("SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_SERROR) |
ArmFault::FaultVals | vals ("Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT) |
ArmFault::FaultVals | vals ("ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN) |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
ArmFault::FaultVals | vals |
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virtual Addr | getVector (ThreadContext *tc) |
Addr | getVector64 (ThreadContext *tc) |
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Addr | faultAddr |
The virtual address the fault occured at. More... | |
Addr | OVAddr |
Original virtual address. More... | |
bool | write |
TlbEntry::DomainType | domain |
uint8_t | source |
uint8_t | srcEncoded |
bool | stage2 |
bool | s1ptw |
ArmFault::TranMethod | tranMethod |
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ExtMachInst | machInst |
uint32_t | issRaw |
bool | from64 |
bool | to64 |
ExceptionLevel | fromEL |
ExceptionLevel | toEL |
OperatingMode | fromMode |
OperatingMode | toMode |
bool | faultUpdated |
bool | hypRouted |
bool | span |
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static FaultVals | vals |
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inline |
Definition at line 491 of file faults.hh.
References ArmISA::ArmFault::annotate(), ArmISA::ArmFault::FaultVals::ec, ArmISA::ArmFault::iss(), ArmISA::ArmFault::routeToHyp(), ArmISA::ArmFault::routeToMonitor(), and X86ISA::val.
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overridevirtual |
Reimplemented from ArmISA::ArmFault.
Definition at line 1377 of file faults.cc.
References ArmISA::AbortFault< T >::annotate(), ArmISA::ArmFault::AR, MipsISA::ar, ArmISA::ArmFault::CM, ArmISA::cm, ArmISA::ArmFault::OFA, ArmISA::ArmFault::SAS, ArmISA::ArmFault::SF, X86ISA::sf, ArmISA::ArmFault::SRT, ArmISA::ArmFault::SSE, and X86ISA::val.
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overridevirtual |
Implements ArmISA::ArmFault.
Definition at line 1287 of file faults.cc.
References ArmISA::ArmFault::AsynchronousExternalAbort, ArmISA::ArmFaultVals< T >::ec(), ArmISA::HypervisorCall::ec(), ArmISA::EC_DATA_ABORT_CURR_EL, ArmISA::EC_DATA_ABORT_LOWER_EL, ArmISA::ArmFault::fromEL, ArmISA::MISCREG_SPSR_HYP, ArmISA::MODE_HYP, panic, ThreadContext::readMiscReg(), ArmISA::ArmFault::to64, and ArmISA::ArmFault::toEL.
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overridevirtual |
Implements ArmISA::ArmFault.
Definition at line 1350 of file faults.cc.
References MipsISA::ar, ArmISA::cm, ArmISA::EL2, ArmISA::AbortFault< T >::iss(), X86ISA::sf, ArmISA::ArmFault::to64, ArmISA::ArmFault::toEL, and X86ISA::val.
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overridevirtual |
Reimplemented from ArmISA::ArmFault.
Definition at line 1328 of file faults.cc.
References ArmISA::ArmFault::AlignmentFault, ArmISA::ArmFault::AsynchronousExternalAbort, ArmISA::currEL(), ArmISA::ArmFault::DebugEvent, ArmISA::EL0, ArmISA::EL2, ArmISA::inSecureState(), ArmISA::MISCREG_HCR, ArmISA::MISCREG_HDCR, ArmISA::MISCREG_SCR, ThreadContext::readMiscRegNoEffect(), and ArmISA::ArmFault::SynchronousExternalAbort.
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overridevirtual |
Reimplemented from ArmISA::ArmFaultVals< DataAbort >.
Definition at line 1316 of file faults.cc.
References ArmISA::ArmFault::from64, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, and ThreadContext::readMiscRegNoEffect().
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