Here is a list of all class members with links to the classes they belong to:

- b -

• b : arr_struct2 , Block , tlm::tlm_bool< D >
• b2nb_thread() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• b_and : sc_dt::sc_fix , sc_dt::sc_fix_fast , sc_dt::sc_ufix , sc_dt::sc_ufix_fast
• b_cb : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• b_func_type : tlm_utils::callback_binder_fw< TYPES >
• b_not() : sc_dt::sc_bit , sc_dt::sc_bitref< X > , sc_dt::sc_fix , sc_dt::sc_fix_fast , sc_dt::sc_logic , sc_dt::sc_proxy< X > , sc_dt::sc_ufix , sc_dt::sc_ufix_fast
• b_or : sc_dt::sc_fix , sc_dt::sc_fix_fast , sc_dt::sc_ufix , sc_dt::sc_ufix_fast
• b_transport() : MultiSocketSimpleSwitchAT , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleLTTarget1 , tlm::tlm_blocking_transport_if< TRANS > , tlm_utils::callback_binder_fw< TYPES > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• b_xor : sc_dt::sc_fix , sc_dt::sc_fix_fast , sc_dt::sc_ufix , sc_dt::sc_ufix_fast
• ba : PowerISA::CondLogicOp
• back() : CircularQueue< T >
• back_cast() : sc_dt::sc_proxy< X >
• backdoor : AbstractMemory , MemBackdoor::Callback
• backdoorMap : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• backendLatency : DRAMCtrl
• backingStore : PhysicalMemory
• BackingStoreEntry() : BackingStoreEntry
• backward_nb_transport() : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH >
• BadAddressError : MemCmd
• bAdd : MathExpr
• BadDevice() : BadDevice
• baddr_t : SimpleDisk
• BadlyPredictedBranch : Minor::BranchData
• BadlyPredictedBranchTarget : Minor::BranchData
• badScore : Prefetcher::BOP
• badvaddr : MipsISA::RemoteGDB::MipsGdbRegCache
• bandwidth : GoodbyeObject , SimpleMemory
• bank : DRAMCtrl::Bank
• Bank() : DRAMCtrl::Bank
• bank : DRAMCtrl::Command , DRAMCtrl::DRAMPacket
• BANK_MASK : Gcn3ISA::InFmt_VOP_DPP
• bankBits : BankedArray , DramGen
• bankConflictPenalty : LdsState
• banked() : ArmISA::ISA::MiscRegLUTEntryInitializer
• banked64() : ArmISA::ISA::MiscRegLUTEntryInitializer
• BankedArray() : BankedArray
• bankedChild() : ArmISA::ISA::MiscRegLUTEntryInitializer
• bankedRegs : GicV2
• BankedRegs() : GicV2::BankedRegs
• bankgr : DRAMCtrl::Bank
• bankGroupArch : DRAMCtrl
• bankGroupsPerRank : DRAMCtrl
• bankId : DRAMCtrl::DRAMPacket
• bankRef : DRAMCtrl::DRAMPacket
• banks : BankedArray , DRAMCtrl::Rank , LdsState
• banksPerRank : DRAMCtrl
• BankType : MipsISA::ISA
• bankType : MipsISA::ISA
• BAR0_SIZE_BASE : PciVirtIO
• BARAddrs : PciDevice
• barCnt : Wavefront
• BareMetal() : RiscvISA::BareMetal
• Barrier() : Barrier
• barrier : BaseGlobalEvent , hsa_packet_header_s
• Barrier() : HsailISA::Barrier
• barrier_id : ComputeUnit
• barrierCnt : Wavefront
• BarrierDataRequest() : Minor::LSQ::BarrierDataRequest
• barrierEvent : BaseGlobalEvent
• BarrierEvent() : BaseGlobalEvent::BarrierEvent , GlobalEvent::BarrierEvent , GlobalSyncEvent::BarrierEvent
• barrierId : Wavefront
• barrierSlots : Wavefront
• BARSize : PciDevice
• base : ArmISA::Memory64 , ArmISA::Memory , ArmISA::RfeOp , ArmISA::SveContigMemSI , ArmISA::SveContigMemSS , ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveMemPredFillSpill , ArmISA::SveMemVecFillSpill , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SysDC64
• Base() : BloomFilter::Base
• base : Brig::BrigDirectiveArgBlockEnd , Brig::BrigDirectiveArgBlockStart , Brig::BrigDirectiveComment , Brig::BrigDirectiveControl , Brig::BrigDirectiveExecutable , Brig::BrigDirectiveExtension , Brig::BrigDirectiveFbarrier , Brig::BrigDirectiveLabel , Brig::BrigDirectiveLoc , Brig::BrigDirectiveModule , Brig::BrigDirectiveNone , Brig::BrigDirectivePragma , Brig::BrigDirectiveVariable , Brig::BrigInstAddr , Brig::BrigInstAtomic , Brig::BrigInstBase , Brig::BrigInstBasic , Brig::BrigInstBr , Brig::BrigInstCmp , Brig::BrigInstCvt , Brig::BrigInstImage , Brig::BrigInstLane , Brig::BrigInstMem , Brig::BrigInstMemFence , Brig::BrigInstMod , Brig::BrigInstQueryImage , Brig::BrigInstQuerySampler , Brig::BrigInstQueue , Brig::BrigInstSeg , Brig::BrigInstSegCvt , Brig::BrigInstSignal , Brig::BrigInstSourceType , Brig::BrigOperandAddress , Brig::BrigOperandAlign , Brig::BrigOperandCodeList , Brig::BrigOperandCodeRef , Brig::BrigOperandConstantBytes , Brig::BrigOperandConstantImage , Brig::BrigOperandConstantOperandList , Brig::BrigOperandConstantSampler , Brig::BrigOperandOperandList , Brig::BrigOperandRegister , Brig::BrigOperandString , Brig::BrigOperandWavesize
• Base : CircularQueue< T > , ClockRateControlInitiatorSocket , ClockRateControlTargetSocket
• base : cp::Format , EmbeddedPyBind
• Base : FastModel::CortexA76 , FastModel::ScxEvsCortexA76< Types > , FastModel::ScxEvsCortexA76x1Types , FastModel::ScxEvsCortexA76x2Types , FastModel::ScxEvsCortexA76x3Types , FastModel::ScxEvsCortexA76x4Types , GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::SimplePCState< MachInst > , GenericISA::UPCState< MachInst > , GlobalEvent , GlobalSyncEvent , HsailISA::Barrier , HsailISA::MemFence , HsailISA::Ret
• base : Loader::MemoryImage::Segment , MipsISA::MipsFaultBase
• Base : NullISA::PCState , Prefetcher::Base , SignalInterruptInitiatorSocket , SignalInterruptTargetSocket , Sinic::Base
• base : TimeBuffer< T > , X86ISA::EmulEnv , X86ISA::I386Process::VSyscallPage , X86ISA::MemOp
• Base : X86ISA::PCState
• base : X86ISA::X86_64Process::VSyscallPage
• Base16Delta8() : Base16Delta8
• Base32Delta16() : Base32Delta16
• Base32Delta8() : Base32Delta8
• Base64Delta16() : Base64Delta16
• Base64Delta32() : Base64Delta32
• Base64Delta8() : Base64Delta8
• base_addr : UserDesc64
• base_address : _hsa_queue_s , hsa_queue_s
• base_event() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• base_initiator_socket_type : tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• base_read() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• base_target_socket_type : tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• base_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_out< sc_dt::sc_bigint< W > > , sc_core::sc_out< sc_dt::sc_biguint< W > > , sc_core::sc_out< sc_dt::sc_int< W > > , sc_core::sc_out< sc_dt::sc_uint< W > > , sc_dt::sc_bv_base , sc_dt::sc_concref< X, Y > , sc_dt::sc_lv_base , sc_dt::sc_subref< X > , tlm::tlm_array< T > , tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::multi_init_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_target_base< BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• base_value_changed_event() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• base_write() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• baseAddr : Gcn3ISA::Inst_MUBUF::BufferRsrcDescriptor , PCIConfig
• baseaddr : Pl111
• baseAddr : PrdEntry , Prefetcher::BOP::DelayQueueEntry , Prefetcher::IndirectMemory::IndirectPatternDetectorEntry , Prefetcher::IndirectMemory::PrefetchTableEntry , UFSHostDevice::UFSHCDSGEntry
• baseAddr1 : MemTest
• baseAddr2 : MemTest
• BaseArmKvmCPU() : BaseArmKvmCPU
• BaseBufferArg() : BaseBufferArg
• BaseCache() : BaseCache
• BaseCacheCompressor() : BaseCacheCompressor
• BaseCacheCompressorStats() : BaseCacheCompressor::BaseCacheCompressorStats
• baseCheck() : Stats::Info
• BaseConfigEntry() : X86ISA::IntelMP::BaseConfigEntry
• BaseCPU() : BaseCPU , Iris::BaseCPU
• baseCpu : ThreadState
• BaseDelta() : BaseDelta< BaseType, DeltaSizeBits >
• BaseDictionaryCompressor() : BaseDictionaryCompressor
• BaseDynInst() : BaseDynInst< Impl >
• BaseDynInstPtr : BaseDynInst< Impl >
• baseEntries : X86ISA::IntelMP::ConfigTable
• baseFilename : CheckpointIn
• BaseGdbRegCache() : BaseGdbRegCache
• BaseGen() : BaseGen , BaseTrafficGen
• BaseGic() : BaseGic
• BaseGlobalEvent : BaseGlobalEvent::BarrierEvent , BaseGlobalEvent
• BaseGlobalEventTemplate() : BaseGlobalEventTemplate< Derived >
• BaseIndexingPolicy() : BaseIndexingPolicy
• BaseInterrupts() : BaseInterrupts
• BaseISADevice() : ArmISA::BaseISADevice
• baseIsSP : ArmISA::Memory64 , ArmISA::SveContigMemSI , ArmISA::SveContigMemSS , ArmISA::SveMemPredFillSpill , ArmISA::SveMemVecFillSpill
• BaseKvmCPU() : BaseKvmCPU , KvmVM
• BaseKvmTimer() : BaseKvmTimer
• BaseMemProbe() : BaseMemProbe
• basename() : sc_core::sc_event , sc_core::sc_object , sc_gem5::Event , sc_gem5::Object
• BaseO3CPU() : BaseO3CPU
• BaseO3DynInst() : BaseO3DynInst< Impl >
• BaseOperand() : BaseOperand
• basePC : X86ISA::Decoder
• BasePixelPump() : BasePixelPump
• basePointer : HSAQueueDescriptor
• basePtr() : MultiLevelPageTable< EntryTypes > , Wavefront
• BASER_ESZ : Gicv3Its
• BASER_INDIRECT : Gicv3Its
• BASER_SZ : Gicv3Its
• BASER_TYPE : Gicv3Its
• BASER_WMASK : Gicv3Its
• BASER_WMASK_UNIMPL : Gicv3Its
• BaseRemoteGDB() : BaseRemoteGDB
• BaseReplacementPolicy() : BaseReplacementPolicy
• BaseSetAssoc() : BaseSetAssoc
• BaseSimpleCPU() : BaseSimpleCPU
• BaseTags() : BaseTags
• BaseTagsCallback() : BaseTagsCallback
• BaseTagStats() : BaseTags::BaseTagStats
• BaseTLB() : BaseTLB
• BaseTrafficGen() : BaseTrafficGen
• BaseType : sc_core::sc_vector_iter< Element, AccessPolicy >
• baseUpdate() : TAGEBase
• BaseXBar() : BaseXBar
• BasicBlock() : BasicBlock
• basicBlock() : ControlFlowInfo
• basicBlocks : ControlFlowInfo
• BasicExtLink() : BasicExtLink
• BasicIntLink() : BasicIntLink
• BasicLink() : BasicLink
• BasicPioDevice() : BasicPioDevice
• BasicRouter() : BasicRouter
• BasicSignal() : BasicSignal
• bb : PowerISA::CondLogicOp
• bbMap : SimPoint
• bc : GPUDynInst
• bcd : Intel8254Timer , Pl111
• bCond : Barrier
• bdelayDoneSeqNum : DefaultDecode< Impl >
• bDiv : MathExpr
• bebo : Pl111
• bebuf_size : tlm::tlm_endian_context
• before_end_of_elaboration() : FastModel::SCGIC , FastModel::ScxEvsCortexA76< Types > , sc_core::sc_clock , sc_core::sc_export< IF > , sc_core::sc_export_base , sc_core::sc_module , sc_core::sc_port_b< IF > , sc_core::sc_port_base , sc_core::sc_prim_channel , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , sc_gem5::TlmToGem5Bridge< BITWIDTH > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• beforeEndOfElaboration() : sc_gem5::Module
• begin() : AddrRangeMap< V, max_cache_size > , AssociativeSet< Entry > , CircularQueue< T > , PacketFifo , sc_core::sc_attr_cltn , sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , sc_dt::sc_context< T > , SimpleRenameMap , SparcISA::TlbMap , Stats::Hdf5 , Stats::Output , Stats::Text
• beginGroup() : Stats::Hdf5 , Stats::Output , Stats::Text
• beginLine() : BasePixelPump
• beginResponse() : ExplicitATTarget , SimpleATTarget1 , SimpleATTarget2
• beginTransaction() : SMMUTranslationProcess
• bepo : Pl111
• best : cp::Format
• bestOffset : Prefetcher::BOP
• bestOffsetLearning() : Prefetcher::BOP
• bestSandbox : Prefetcher::SBOOE
• bestScore : Prefetcher::BOP
• bf : PowerISA::CondMoveOp
• bfa : PowerISA::CondMoveOp
• BGLoad : Sp804::Timer
• bgr : Pl111
• bi : PowerISA::BranchCond , sc_dt::scfx_index
• bias() : Loader::ElfObject , Loader::ObjectFile
• BIAS() : MultiperspectivePerceptron::BIAS
• bias : StatisticalCorrector
• bias0 : MultiperspectivePerceptron
• bias1 : MultiperspectivePerceptron
• biasBank : StatisticalCorrector
• biasmostly0 : MultiperspectivePerceptron
• biasmostly1 : MultiperspectivePerceptron
• biasSK : StatisticalCorrector
• big_endian : HDLcd
• bigendian : VncInput::PixelFormat
• BigFpMemImmOp() : ArmISA::BigFpMemImmOp
• BigFpMemLitOp() : ArmISA::BigFpMemLitOp
• BigFpMemPostOp() : ArmISA::BigFpMemPostOp
• BigFpMemPreOp() : ArmISA::BigFpMemPreOp
• BigFpMemRegOp() : ArmISA::BigFpMemRegOp
• bigPkt : TimingSimpleCPU::SplitFragmentSenderState
• bigThumb : ArmISA::Decoder
• BIMODAL_ALT_MATCH : TAGEBase
• BIMODAL_ONLY : TAGEBase
• bimodalAltMatchProviderCorrect : TAGEBase
• bimodalAltMatchProviderWrong : TAGEBase
• bimodalIndex : TAGEBase::BranchInfo
• BiModeBP() : BiModeBP
• binary : MathExpr::OpSearch
• BinaryNode() : Stats::BinaryNode< Op >
• binaryOp() : ArmISA::FpOp
• bind() : EtherInt , IntSinkPinBase , IntSourcePinBase , MasterPort , Port , RubyDummyPort , sc_core::sc_export< IF > , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_port_b< IF > , sc_core::sc_port_base , sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , sc_gem5::Port , sc_gem5::ScExportWrapper< IF > , sc_gem5::ScInterfaceWrapper< IF > , sc_gem5::ScPortWrapper< IF > , sc_gem5::TlmInitiatorBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL > , sc_gem5::TlmTargetBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL > , SlavePort , tlm::tlm_analysis_port< T > , tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , TokenMasterPort , TokenSlavePort
• bind_exports() : tlm::tlm_req_rsp_channel< REQ, RSP, REQ_CHANNEL, RSP_CHANNEL >
• bindAllPorts() : CxxConfigManager
• bindex() : MPP_TAGE , TAGE_SC_L_TAGE , TAGEBase
• Binding() : sc_gem5::Port::Binding
• bindingIndex : sc_gem5::Module
• bindings : sc_gem5::Port
• bindList() : Scheduler
• bindMasterPort() : CxxConfigManager
• bindObjectPorts() : CxxConfigManager
• bindPort() : CxxConfigManager
• bindPorts() : sc_gem5::Module
• bindTargetSocket() : MultiSocketSimpleSwitchAT
• bindToLoopback : ListenSocket
• bindWaveList() : FetchUnit
• binOp : MathExpr
• BiosInformation() : X86ISA::SMBios::BiosInformation
• BIPRP() : BIPRP
• bist : PCIConfig
• bit() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_int_base , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• bit_type : sc_dt::sc_bitref_r< T > , sc_dt::sc_proxy< X > , sc_dt::sc_proxy_traits< sc_bv_base > , sc_dt::sc_proxy_traits< sc_lv_base >
• BitCount : BmpWriter::InfoHeaderV1
• Bitfield : BitfieldBackend::BitfieldTypes< Storage >
• BitfieldRO : BitfieldBackend::BitfieldTypes< Storage >
• BitfieldROType() : BitfieldROType< Base >
• BitfieldType() : BitfieldType< Base >
• BitfieldTypeImpl() : BitfieldTypeImpl< Base >
• BitfieldWO : BitfieldBackend::BitfieldTypes< Storage >
• BitfieldWOType() : BitfieldWOType< Base >
• bitIndex() : NetDest
• bitmask : WaiterState
• bits : DictionaryCompressor< T >::MaskedPattern< mask > , ImmOperand< T > , MSIXPbaEntry , Set
• BitUnion16() : GenericTimerFrame
• BitUnion32() : A9GlobalTimer::Timer , ArchTimer , ArmISA::PMU , CpuLocalTimer::Timer , FVPBasePwrCtrl , GenericTimerMem , GicV2 , Gicv3CPUInterface , Gicv3Its , HDLcd , RealViewCtrl , Sp804::Timer , VGic , X86ISA::Interrupts , X86ISA::PageFault
• BitUnion64() : ContextDescriptor , Gicv3CPUInterface , Gicv3Distributor , Gicv3Its , SMMUCommand , StreamTableEntry , X86ISA::I82094AA
• BitUnion8() : GenericTimerFrame , Gicv3Redistributor , IdeController , Intel8254Timer , MC146818 , Pl050 , Pl111 , PS2Mouse , VirtIODeviceBase , X86ISA::I8042 , X86ISA::Speaker
• BitUnionOperators() : BitfieldBackend::BitUnionOperators< Base >
• blank_space : cp::Format
• blk : CacheBlkPrintWrapper
• blkAddr : MSHR::TargetList , QueueEntry
• blkAlign() : BaseTags
• blkcnt_t : RiscvLinux64
• blkMask : BaseTags
• blks : BaseSetAssoc , CompressedTags , FALRU , SectorBlk , SectorTags
• blkSize : BaseCache , BaseCacheCompressor , BaseTags , FALRU::CacheTracking , MSHR::TargetList , Prefetcher::AccessMapPatternMatching , Prefetcher::Base , QueueEntry , SuperBlk , UFSHostDevice::UFSSCSIDevice
• blksize_t : RiscvLinux64
• BlkType : FALRU
• Block : ArmISA::TableWalker::LongDescriptor , Block , BloomFilter::Block
• block() : DefaultDecode< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FlashDevice::PageMapEntry
• BLOCK_CACHED : Packet
• blockAddress() : Prefetcher::Base
• blockAddrMask : MemTest
• blockAlign() : MemTest
• blockBits : DramGen
• blocked : BaseCache , BaseCache::CacheSlavePort
• Blocked : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• blocked : Minor::Decode::DecodeThreadInfo , Minor::Fetch1::Fetch1ThreadInfo , Minor::Fetch2::Fetch2ThreadInfo , SimpleCache , SimpleMemobj
• blocked_causes : BaseCache::CacheStats
• blocked_cycles : BaseCache::CacheStats
• Blocked_NoMSHRs : BaseCache
• Blocked_NoTargets : BaseCache
• Blocked_NoWBBuffers : BaseCache
• BlockedCause : BaseCache
• blockedCycle : BaseCache
• blockedMemInsts : InstructionQueue< Impl >
• blockedPacket : SimpleCache::CPUSidePort , SimpleCache::MemSidePort , SimpleMemobj::CPUSidePort , SimpleMemobj::MemSidePort
• blockedWaitingResp : BaseTrafficGen
• blockEmptyEntries : FlashDevice
• blockIndex() : Prefetcher::Base
• BlockingInst : BaseDynInst< Impl >
• blockingRequest : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• blockingResponse : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• BlockMem() : SparcISA::BlockMem
• BlockMemImmMicro() : SparcISA::BlockMemImmMicro
• blockMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• BlockMemMicro() : SparcISA::BlockMemMicro
• blockOnQueue() : AbstractController
• blockSize : FlashDevice , MemTest , MultiperspectivePerceptron , SimpleCache
• blocksize : StochasticGen , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement
• blockSizeBits : GarnetSyntheticTraffic
• blocksPerDisk : FlashDevice
• blockThisCycle : DefaultRename< Impl >
• blockValidEntries : FlashDevice
• blue : BmpWriter::BmpPixel32 , Pixel , PngWriter::PngPixel24 , rgb_t
• Blue_Select : HDLcd
• blue_select : HDLcd
• bluemax : VncInput::PixelFormat
• blueshift : VncInput::PixelFormat
• BLURRYPATH() : MultiperspectivePerceptron::BLURRYPATH
• blurrypath_bits : MultiperspectivePerceptron
• blurrypath_histories : MultiperspectivePerceptron::ThreadData
• bmEnabled : IdeController
• bmiAddr : IdeController
• bmiSize : IdeController
• bmp : Pl111 , sc_gem5::TlmToGem5Bridge< BITWIDTH >
• BmpWriter() : BmpWriter
• bMul : MathExpr
• bMutex : Barrier
• bo : PowerISA::BranchCond
• Bootcs : RealViewCtrl
• bootldr : ArmISA::FsWorkload
• bootloader : RiscvISA::BareMetal
• bootLoaders : ArmISA::FsWorkload
• bootloaderSymtab : RiscvISA::BareMetal
• bootReleaseAddr : ArmISA::FsFreebsd
• BOP() : Prefetcher::BOP
• bottomDW : X86ISA::I82094AA
• bottomReserved : X86ISA::I82094AA
• BOUND_CTRL : Gcn3ISA::InFmt_VOP_DPP
• boundaries : FALRU::CacheTracking
• BoundRange() : X86ISA::BoundRange
• box_tick_cnt : Shader
• bpHistory : BPredUnit::PredictorHistory
• BpId : Iris::ThreadContext
• BpInfo() : Iris::ThreadContext::BpInfo
• BpInfoIt : Iris::ThreadContext
• BpInfoMap : Iris::ThreadContext
• BpInfoPtr : Iris::ThreadContext
• bPow : MathExpr
• bpp : VncInput::PixelFormat
• bpp1 : Pl111
• bpp12 : Pl111
• bpp16 : Pl111
• bpp16m565 : Pl111
• bpp2 : Pl111
• bpp24 : Pl111
• bpp4 : Pl111
• bpp8 : Pl111
• bpr1() : Gicv3CPUInterface
• BPredUnit() : BPredUnit
• bps : Iris::ThreadContext
• bpSpaceIds : FastModel::CortexA76TC
• branchAddr : TimeBufStruct< Impl >::decodeComm
• BranchCond() : PowerISA::BranchCond
• branchCount() : DefaultFetch< Impl > , TimeBufStruct< Impl >::decodeComm
• BranchData() : Minor::BranchData
• BranchDisp() : SparcISA::BranchDisp
• BranchEret64() : ArmISA::BranchEret64
• BranchEretA64() : ArmISA::BranchEretA64
• BranchImm() : ArmISA::BranchImm
• BranchImm13() : SparcISA::BranchImm13
• BranchImm64() : ArmISA::BranchImm64
• BranchImmCond() : ArmISA::BranchImmCond
• BranchImmCond64() : ArmISA::BranchImmCond64
• BranchImmImmReg64() : ArmISA::BranchImmImmReg64
• BranchImmReg() : ArmISA::BranchImmReg
• BranchImmReg64() : ArmISA::BranchImmReg64
• BranchInfo() : LoopPredictor::BranchInfo , MPP_TAGE::BranchInfo , StatisticalCorrector::BranchInfo , TAGE_SC_L_TAGE::BranchInfo , TAGEBase::BranchInfo
• branching() : GenericISA::DelaySlotPCState< MachInst > , GenericISA::DelaySlotUPCState< MachInst > , GenericISA::SimplePCState< MachInst > , GenericISA::UPCState< MachInst > , RiscvISA::PCState , X86ISA::PCState
• branchInp : Minor::Fetch2
• branchMispredict : DefaultIEWDefaultCommit< Impl > , TimeBufStruct< Impl >::decodeComm
• branchMispredicts : DefaultCommit< Impl > , DefaultIEW< Impl >
• BranchNBits() : SparcISA::BranchNBits< bits >
• BranchNonPCRel() : PowerISA::BranchNonPCRel
• BranchNonPCRelCond() : PowerISA::BranchNonPCRelCond
• branchPC : TAGEBase::BranchInfo
• BranchPCRel() : PowerISA::BranchPCRel
• BranchPCRelCond() : PowerISA::BranchPCRelCond
• branchPred : BaseSimpleCPU , DefaultFetch< Impl >
• BranchPrediction : Minor::BranchData
• branchPredictor : Minor::Fetch2
• branchRate : DefaultFetch< Impl >
• BranchReg() : ArmISA::BranchReg
• BranchReg64() : ArmISA::BranchReg64
• BranchRegCond() : ArmISA::BranchRegCond , PowerISA::BranchRegCond
• BranchRegReg() : ArmISA::BranchRegReg
• BranchRegReg64() : ArmISA::BranchRegReg64
• BranchRet64() : ArmISA::BranchRet64
• BranchRetA64() : ArmISA::BranchRetA64
• BranchSplit() : SparcISA::BranchSplit
• branchTaken : DefaultIEWDefaultCommit< Impl > , TimeBufStruct< Impl >::commitComm , TimeBufStruct< Impl >::decodeComm
• branchTarget() : ArmISA::BranchImm64 , ArmISA::BranchImmImmReg64 , ArmISA::BranchImmReg64 , BaseDynInst< Impl > , PowerISA::BranchNonPCRel , PowerISA::BranchNonPCRelCond , PowerISA::BranchPCRel , PowerISA::BranchPCRelCond , PowerISA::BranchRegCond , StaticInst
• brar : dp_regs
• BrDirectInst() : HsailISA::BrDirectInst
• brdr : dp_regs
• BreakPCEvent() : BreakPCEvent
• breakpoint() : BaseRemoteGDB , System
• Breakpoint() : X86ISA::Breakpoint
• breakpointEventStreamId : Iris::ThreadContext
• BreakpointFault() : RiscvISA::BreakpointFault
• breakpointHit() : Iris::ThreadContext
• Bridge() : Bridge
• bridge : Bridge::BridgeMasterPort , Bridge::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeMasterPort
• BridgeMasterPort() : Bridge::BridgeMasterPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeMasterPort
• BridgeSlavePort() : Bridge::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort
• brigInstBase : HsailISA::MachInst
• brigMajor : Brig::BrigModuleHeader
• brigMinor : Brig::BrigModuleHeader
• brigObj : HsailISA::MachInst
• BrigObject() : BrigObject
• BrigRegOperandInfo() : BrigRegOperandInfo
• brigSymbol : StorageElement
• BrIndirectInst() : HsailISA::BrIndirectInst
• BrInstBase() : HsailISA::BrInstBase< TargetType >
• BrnDirectInst() : HsailISA::BrnDirectInst
• BrnIndirectInst() : HsailISA::BrnIndirectInst
• BrnInstBase() : HsailISA::BrnInstBase< TargetType >
• broadcast() : ArmISA::DTLBIALL , ArmISA::DTLBIASID , ArmISA::DTLBIMVA , ArmISA::ITLBIALL , ArmISA::ITLBIASID , ArmISA::ITLBIMVA , ArmISA::TLBIOp , Net::EthAddr , NetDest , Set
• BRRIPReplData() : BRRIPRP::BRRIPReplData
• BRRIPRP() : BRRIPRP
• bsp : sc_gem5::Gem5ToTlmBridge< BITWIDTH >
• bSub : MathExpr
• bt : PowerISA::CondLogicOp
• btableHysteresis : TAGEBase
• btablePrediction : TAGEBase
• BTB : BPredUnit
• btb : DefaultBTB
• BTBCorrect : BPredUnit
• BTBEntry() : DefaultBTB::BTBEntry
• BTBHitPct : BPredUnit
• BTBHits : BPredUnit
• BTBLookup() : BPredUnit
• BTBLookups : BPredUnit
• btbUpdate() : BiModeBP
• BTBUpdate() : BPredUnit
• btbUpdate() : BPredUnit , LocalBP , MultiperspectivePerceptron , TAGE , TAGEBase , TournamentBP
• BTBValid() : BPredUnit
• btp : BIPRP , BRRIPRP
• BTransportPtr : tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process
• bubble() : Minor::BranchData , Minor::BubbleTraitsAdaptor< ElemType > , Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > , Minor::ForwardLineData , Minor::MinorDynInst , Minor::NoBubbleTraits< ElemType > , Minor::QueuedInst
• bubbleFill() : Minor::ForwardInstData
• bubbleFlag : Minor::ForwardLineData
• bubbleInst : Minor::MinorDynInst
• bucket_size : Stats::DistData , Stats::DistStor , Stats::DistStor::Params , Stats::HistStor
• buckets : Stats::DistStor::Params , Stats::HistStor::Params
• budgetbits : MultiperspectivePerceptron
• buf : Fifo< T > , iGbReg::RxDesc , sc_gem5::UniqueNameGen , Trace::InstPBTrace , Trace::TarmacParserRecord
• buf_alloc() : tlm::circular_buffer< T >
• buf_clear() : tlm::circular_buffer< T >
• buf_free() : tlm::circular_buffer< T >
• buf_read() : tlm::circular_buffer< T >
• buf_size_in_bytes : kfd_ioctl_dbg_address_watch_args , kfd_ioctl_dbg_wave_control_args
• buf_write() : tlm::circular_buffer< T >
• buff_per_vc : FaultModel::system_conf
• buffer : DmaReadFifo , EtherTapBase , GoodbyeObject
• Buffer : Minor::Latch< Data >
• buffer : Minor::Latch< Data > , TimeBuffer< T >::wire , tlm::tlm_fifo< T > , UFSHostDevice::transferInfo , VPtr< T >
• buffer_size : Pl111
• buffer_used : EtherTapStub
• BufferArg() : BufferArg
• bufferPtr() : BufferArg
• bufferram : ArmLinux32::tgt_sysinfo , ArmLinux64::tgt_sysinfo , MipsLinux::tgt_sysinfo , RiscvLinux32::tgt_sysinfo , RiscvLinux64::tgt_sysinfo , Sparc32Linux::tgt_sysinfo , SparcLinux::tgt_sysinfo , X86Linux32::tgt_sysinfo , X86Linux64::tgt_sysinfo
• bufferSize : GoodbyeObject , TAGEBase::FoldedHistory
• bufferUsed : GoodbyeObject
• buflen : EtherTapBase
• bufLen() : iGbReg::Regs::SRRCTL
• bufLength : EthPacketData
• bufPtr : BaseBufferArg
• bufptr : ns_desc32 , ns_desc64
• bufSize : Trace::InstPBTrace
• buildDispatcher() : ArmSemihosting::SemiCall
• buildDumper() : ArmSemihosting::SemiCall , SyscallDescABI< ABI >
• buildExecutor() : SyscallDescABI< ABI >
• buildImage() : Loader::DtbFile , Loader::ElfObject , Loader::ImageFile , Loader::RawImage
• buildInst() : DefaultFetch< Impl >
• buildPacket() : TimingSimpleCPU
• buildPackets() : LSQ< Impl >::LSQRequest , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest
• buildSplitPacket() : TimingSimpleCPU
• buildTageTables() : TAGE_SC_L_TAGE , TAGEBase
• Bulk() : BloomFilter::Bulk
• burst_len : HDLcd
• burstAlign() : DRAMCtrl
• burstCount : DRAMCtrl::BurstHelper
• burstDataCycles : DRAMCtrl
• BurstHelper() : DRAMCtrl::BurstHelper
• burstHelper : DRAMCtrl::DRAMPacket
• burstInterleave : DRAMCtrl
• burstLength : DRAMCtrl
• burstSize : DRAMCtrl , DRAMSim2Wrapper
• burstsServiced : DRAMCtrl::BurstHelper
• burstTicks : DRAMCtrl
• bus : PciBusAddr
• Bus() : X86ISA::IntelMP::Bus
• Bus_Options : HDLcd
• bus_options : HDLcd
• BUS_OPTIONS_RESETV : HDLcd
• busAddr() : PciDevice , PciHost::DeviceInterface
• BusHierarchy() : X86ISA::IntelMP::BusHierarchy
• busID : X86ISA::IntelMP::AddrSpaceMapping , X86ISA::IntelMP::Bus , X86ISA::IntelMP::BusHierarchy , X86ISA::IntelMP::CompatAddrSpaceMod
• busState : QoS::MemCtrl
• BusState : QoS::MemCtrl
• busStateNext : QoS::MemCtrl
• busType : X86ISA::IntelMP::Bus
• busUtil : DRAMCtrl::DRAMStats
• busUtilRead : DRAMCtrl::DRAMStats
• busUtilWrite : DRAMCtrl::DRAMStats
• BUSY : BaseXBar::Layer< SrcType, DstType >
• busy : ConditionRegisterState , CopyEngine::CopyEngineChannel , DistEtherLink::Link , DMASequencer , EtherBus , EtherLink::Link , Iob::IntBusy , sc_core::sc_event_and_list , sc_core::sc_event_or_list , Shader , SMMUCommandExecProcess , VectorRegisterFile
• busyBanks : BankedArray
• button_mask : VncInput::PointerEventMessage
• bw_interface_type : SimpleInitiatorWrapper , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , SimpleLTTarget1 , SimpleTargetWrapper , tlm::tlm_base_initiator_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm::tlm_base_target_socket< BUSWIDTH, FW_IF, BW_IF, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• bw_invalidate_direct_mem_ptr() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• bw_nb_transport() : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• bw_process : tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process
• bwgehl : StatisticalCorrector
• bwHist : StatisticalCorrector::SCThreadHistory
• bwID : MultiSocketSimpleSwitchAT::ConnectionInfo
• bwInstRead : AbstractMemory::MemStats
• bwm : StatisticalCorrector
• bwnb : StatisticalCorrector
• bwPEQcb() : MultiSocketSimpleSwitchAT
• bwRead : AbstractMemory::MemStats
• bwTotal : AbstractMemory::MemStats
• bwWrite : AbstractMemory::MemStats
• bypass() : SMMUTranslationProcess
• bypassCaches() : System
• byte : QTIsaac< ALPHA >
• byte_enable : tlm::tlm_endian_context
• byte_order : PixelConverter
• byte_trackers : MemChecker
• byteCount : Brig::BrigBase , Brig::BrigData , Brig::BrigModuleHeader , Brig::BrigSectionHeader , PrdEntry , WriteAllocator
• byteMask : MsrBase
• byteOrder : ArmFreebsd , ArmLinux , MipsLinux , PowerLinux , Prefetcher::IndirectMemory , RiscvLinux , SimpleUart , SparcLinux , SparcSolaris , VirtDescriptor , VirtIODeviceBase , VirtQueue , VirtQueue::VirtRing< T > , X86Linux
• bytes : Brig::BrigData , Brig::BrigOperandConstantBytes , DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits > , Net::EthAddr , Net::EthHdr , Net::Ip6Hdr , Net::IpHdr , Net::TcpHdr , Net::TcpOpt , Net::UdpHdr
• bytes_completed : DMARequest
• bytes_copied : kfd_ioctl_cross_memory_copy_args
• bytes_issued : DMARequest
• bytes_per_pixel : HDLcd
• bytesAccessed : DRAMCtrl::Bank
• bytesAllocated : LdsState
• bytesCopied : CopyEngine , IGbE::RxDescCache
• bytesInstRead : AbstractMemory::MemStats
• bytesPerActivate : DRAMCtrl::DRAMStats
• bytesPerPixel : Pl111
• bytesRead : AbstractMemory::MemStats , BaseTrafficGen::StatGroup
• bytesReadDRAM : DRAMCtrl::DRAMStats
• bytesReadSys : DRAMCtrl::DRAMStats
• bytesReadWrQ : DRAMCtrl::DRAMStats
• bytesValid : Packet
• bytesWritten : AbstractMemory::MemStats , BaseTrafficGen::StatGroup , DRAMCtrl::DRAMStats
• bytesWrittenSys : DRAMCtrl::DRAMStats
• ByteSz : LaneData< LS >
• ByteTable : X86ISA::Decoder
• ByteTracker() : MemChecker::ByteTracker