- i -

i : KvmFPReg
i2cAddr : I2CBus
iam : iGbReg::Regs
ibrd : Pl011
ic : Iob
icacheGen : TraceCPU
icacheNextEvent : TraceCPU
icachePort : AtomicSimpleCPU , CheckerCPU , DefaultFetch< Impl > , Minor::Fetch1 , TimingSimpleCPU , TraceCPU
icacheStallCycles : DefaultFetch< Impl > , SimpleExecContext
icacheState : Minor::Fetch1
iccrpr : GicV2
ICH_LR_EL2_STATE_ACTIVE : Gicv3CPUInterface
ICH_LR_EL2_STATE_ACTIVE_PENDING : Gicv3CPUInterface
ICH_LR_EL2_STATE_PENDING : Gicv3CPUInterface
icid : Gicv3Its
icountRscId : Iris::ThreadContext
icr : iGbReg::Regs
id : _hsa_queue_s , AbstractController::SenderState , ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , BasicBlock , GarnetSyntheticTraffic , hsa_queue_s , iGbReg::RxDesc , MemDepUnit< MemDepPred, Impl > , MemTest , Minor::Fetch1::FetchRequest , Minor::ForwardLineData , Minor::MinorDynInst , Network::AddrMapNode , Packet , Port , sc_gem5::ReportMsgInfo , SimpleCache::CPUSidePort , SimPoint::BBInfo , Stats::Info , ThermalNode
ID : tlm::tlm_extension< T >
id : vring_used_elem , X86ISA::I82094AA , X86ISA::IntelMP::IOAPIC
ID_9P : VirtIO9PBase
ID_BLOCK : VirtIOBlock
ID_CONSOLE : VirtIOConsole
id_count : Stats::Info
ID_INVALID : VirtIODummyDevice
IDbits : Gicv3CPUInterface
IDBITS : Gicv3Distributor
idBits : Gicv3Its
idcode : ArmISA::PMU
ideConfig : IdeController
ident : Net::ip6_opt_fragment
identification : Brig::BrigModuleHeader
idle_dur : ExecStage
idleCycles : FullO3CPU< Impl > , Ticked
idleDur : ExecStage
idleFraction : SimpleExecContext
idlePhaseStart : UFSHostDevice
idleRate : DefaultFetch< Impl >
idleTimes : UFSHostDevice::UFSHostDeviceStats
idr0 : SMMURegs
idr1 : SMMURegs
idr2 : SMMURegs
idr3 : SMMURegs
idr4 : SMMURegs
idr5 : SMMURegs
idRegs : CustomNoMaliGpu
ids : Iris::ThreadContext::BpInfo
idx : ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , ArmV8KvmCPU::IntRegInfo , ArmV8KvmCPU::MiscRegInfo , BankedArray::AccessRecord , FUPool::FUIdxQueue , LSQUnit< Impl >::LQSenderState , LSQUnit< Impl >::SQSenderState , vring_avail , vring_used
idx1 : Prefetcher::IndirectMemory::IndirectPatternDetectorEntry
idx2 : Prefetcher::IndirectMemory::IndirectPatternDetectorEntry
IDXEN : Gcn3ISA::InFmt_MTBUF , Gcn3ISA::InFmt_MUBUF
idxMask : DefaultBTB
idxStride : Gcn3ISA::Inst_MUBUF::BufferRsrcDescriptor
ie : RiscvISA::Interrupts
ier : dp_regs
IER : Uart8250
iew : DefaultRename< Impl >::Stalls , FullO3CPU< Impl >
iew_ptr : DefaultRename< Impl >
iewBlock : TimeBufStruct< Impl >
iewBlockCycles : DefaultIEW< Impl >
iewDispatchedInsts : DefaultIEW< Impl >
iewDispLoadInsts : DefaultIEW< Impl >
iewDispNonSpecInsts : DefaultIEW< Impl >
iewDispSquashedInsts : DefaultIEW< Impl >
iewDispStoreInsts : DefaultIEW< Impl >
iewExecLoadInsts : DefaultIEW< Impl >
iewExecRate : DefaultIEW< Impl >
iewExecSquashedInsts : DefaultIEW< Impl >
iewExecStoreInsts : DefaultIEW< Impl >
iewExecutedBranches : DefaultIEW< Impl >
iewExecutedInsts : DefaultIEW< Impl >
iewExecutedNop : DefaultIEW< Impl >
iewExecutedRefs : DefaultIEW< Impl >
iewExecutedSwp : DefaultIEW< Impl >
iewIdleCycles : DefaultIEW< Impl >
iewInfo : TimeBufStruct< Impl >
iewInstsToCommit : DefaultIEW< Impl >
iewIQFullEvents : DefaultIEW< Impl >
iewLSQFullEvents : DefaultIEW< Impl >
iewQueue : DefaultCommit< Impl > , DefaultIEW< Impl > , FullO3CPU< Impl >
iewSquashCycles : DefaultIEW< Impl >
iewStage : DefaultCommit< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
iewToCommitDelay : DefaultCommit< Impl >
iewToDecodeDelay : DefaultDecode< Impl >
iewToFetchDelay : DefaultFetch< Impl >
iewToRenameDelay : DefaultRename< Impl >
iewUnblock : TimeBufStruct< Impl >
iewUnblockCycles : DefaultIEW< Impl >
iface : sc_gem5::TraceVal<::sc_core::sc_signal_in_if< T >, Base >
iface_ : sc_gem5::ScInterfaceWrapper< IF >
ifc : SMMUAction , SMMUATSMasterPort , SMMUATSSlavePort , SMMUSlavePort , SMMUTranslationProcess
ifcSmmuLat : SMMUv3
ifcSmmuSem : SMMUv3
ifd : Loader::MemoryImage::Segment
ifetch_pkt : TimingSimpleCPU
ifetch_req : AtomicSimpleCPU
ifls : Pl011
iFmt_DS : Gcn3ISA::InstFormat
iFmt_DS_1 : Gcn3ISA::InstFormat
iFmt_EXP : Gcn3ISA::InstFormat
iFmt_EXP_1 : Gcn3ISA::InstFormat
iFmt_FLAT : Gcn3ISA::InstFormat
iFmt_FLAT_1 : Gcn3ISA::InstFormat
iFmt_INST : Gcn3ISA::InstFormat
iFmt_MIMG : Gcn3ISA::InstFormat
iFmt_MIMG_1 : Gcn3ISA::InstFormat
iFmt_MTBUF : Gcn3ISA::InstFormat
iFmt_MTBUF_1 : Gcn3ISA::InstFormat
iFmt_MUBUF : Gcn3ISA::InstFormat
iFmt_MUBUF_1 : Gcn3ISA::InstFormat
iFmt_SMEM : Gcn3ISA::InstFormat
iFmt_SMEM_1 : Gcn3ISA::InstFormat
iFmt_SOP1 : Gcn3ISA::InstFormat
iFmt_SOP2 : Gcn3ISA::InstFormat
iFmt_SOPC : Gcn3ISA::InstFormat
iFmt_SOPK : Gcn3ISA::InstFormat
iFmt_SOPP : Gcn3ISA::InstFormat
iFmt_VINTRP : Gcn3ISA::InstFormat
iFmt_VOP1 : Gcn3ISA::InstFormat
iFmt_VOP2 : Gcn3ISA::InstFormat
iFmt_VOP3 : Gcn3ISA::InstFormat
iFmt_VOP3_1 : Gcn3ISA::InstFormat
iFmt_VOP3_SDST_ENC : Gcn3ISA::InstFormat
iFmt_VOP_DPP : Gcn3ISA::InstFormat
iFmt_VOP_SDWA : Gcn3ISA::InstFormat
iFmt_VOPC : Gcn3ISA::InstFormat
igbe : IGbE::DescCache< T >
igehl : StatisticalCorrector
ignore : Trace::Logger
ignoredAddrRange : Trace::TarmacParser
ihr : dp_regs
ihs : Pl111
iidr : SMMURegs
im : StatisticalCorrector
image : CowDiskCallback , IdeDisk , KernelWorkload , Loader::ElfObject , MmDisk , Process , SimpleDisk , VirtIOBlock
imageData : Loader::ImageFile
imageQuery : Brig::BrigInstQueryImage
imageSegmentMemoryScope : Brig::BrigInstMemFence
imageType : Brig::BrigInstImage , Brig::BrigInstQueryImage
imask : ArchTimer
imcrPresent : X86ISA::IntelMP::FloatingPointer
imDe : Gicv3Its
imgehl : TAGE_SC_L_64KB_StatisticalCorrector
imgFormat : HDLcd , VncInput
imgWriter : HDLcd
imHist : TAGE_SC_L_64KB_StatisticalCorrector::SC_64KB_ThreadHistory
imli_counter : MultiperspectivePerceptron::ThreadData
imli_counter_bits : MultiperspectivePerceptron
imli_mask1 : MultiperspectivePerceptron
imli_mask4 : MultiperspectivePerceptron
imliCount : StatisticalCorrector::SCThreadHistory
imm : ArmISA::BranchImm64 , ArmISA::BranchImm , ArmISA::BranchImmReg64 , ArmISA::BranchImmReg , ArmISA::DataImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX2RegImmOp , ArmISA::DataXCondCompImmOp , ArmISA::DataXImmOnlyOp , ArmISA::DataXImmOp , ArmISA::FpRegImmOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegRegImmOp , ArmISA::MemoryImm64 , ArmISA::MemoryImm , ArmISA::MemoryLiteral64 , ArmISA::MicroIntImmOp , ArmISA::MicroIntImmXOp , ArmISA::MicroMemPairOp , ArmISA::MicroNeonMemOp , ArmISA::PredImmOp , ArmISA::SveBinImmIdxUnpredOp , ArmISA::SveBinImmPredOp , ArmISA::SveBinImmUnpredConstrOp , ArmISA::SveBinImmUnpredDestrOp , ArmISA::SveBinWideImmUnpredOp , ArmISA::SveCmpImmOp , ArmISA::SveComplexIdxOp , ArmISA::SveContigMemSI , ArmISA::SveDotProdIdxOp , ArmISA::SveElemCountOp , ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIntCmpImmOp , ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveMemPredFillSpill , ArmISA::SveMemVecFillSpill , ArmISA::SvePtrueOp , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveTerImmUnpredOp , ArmISA::SveUnaryWideImmPredOp , ArmISA::SveUnaryWideImmUnpredOp , ArmISA::SysDC64
IMM : Gcn3ISA::InFmt_SMEM
imm : ImmOp64 , ImmOp , McrrOp , MiscRegImmOp64 , MiscRegImplDefined64 , MiscRegRegImmOp64 , MiscRegRegImmOp , MrrcOp , MsrImmOp , PowerISA::IntImmOp , RegImmOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp64 , RegMiscRegImmOp , RegRegImmOp , RegRegRegImmOp64 , RegRegRegImmOp , RiscvISA::ImmOp< I > , SparcISA::BlockMemImmMicro , SparcISA::BranchImm13 , SparcISA::IntOpImm , SparcISA::MemImm , SparcISA::PrivImm , TAGE_SC_L_64KB_StatisticalCorrector
imm1 : ArmISA::BranchImmImmReg64 , ArmISA::DataX1Reg2ImmOp , ArmISA::SveIndexIIOp , ArmISA::SveIndexIROp , RegImmImmOp , RegRegImmImmOp64 , RegRegImmImmOp
imm2 : ArmISA::BranchImmImmReg64 , ArmISA::DataX1Reg2ImmOp , ArmISA::SveIndexIIOp , ArmISA::SveIndexRIOp , RegImmImmOp , RegRegImmImmOp64 , RegRegImmImmOp
imm8 : X86ISA::MediaOpImm , X86ISA::RegOpImm
imm_f32 : Gcn3ISA::InstFormat
imm_op : RegOrImmOperand< RegOperand, T >
imm_u32 : Gcn3ISA::InstFormat
immediate : X86ISA::ExtMachInst
immediateCollected : X86ISA::Decoder
immediateSize : X86ISA::Decoder
ImmediateTypeOneByte : X86ISA::Decoder
ImmediateTypeThreeByte0F38 : X86ISA::Decoder
ImmediateTypeThreeByte0F3A : X86ISA::Decoder
ImmediateTypeTwoByte : X86ISA::Decoder
ImmediateTypeVex : X86ISA::Decoder
imnb : TAGE_SC_L_64KB_StatisticalCorrector
imp : ArmISA::PMU
impdefAsNop : ArmISA::ISA
impl_kern_boundary_sync : Shader
ImplBits : PowerISA::VAddr
ImplMask : PowerISA::VAddr
importer : EmbeddedPython
importerModule : EmbeddedPython
imprecise : kfd_memory_exception_failure
imr : dp_regs , iGbReg::Regs
IMR : X86ISA::I8259
imsc : Pl011
IN_BARRIER : Gcn3ISA::StatusReg
IN_TG : Gcn3ISA::StatusReg
in_valid : a_new_struct
in_valid1 : memory
in_value1 : a_new_struct , memory
in_value2 : a_new_struct
inAddrMap : AbstractMemory , BackingStoreEntry
inAllCachesMask : FALRU::CacheTracking
inArgCount : Brig::BrigDirectiveExecutable
inb : StatisticalCorrector
inBuffer : PS2Device
inCachesMask : FALRUBlk
includeSquashInst : DefaultIEWDefaultCommit< Impl >
incoming_link : Message
increasedIndirectCounter : Prefetcher::IndirectMemory::PrefetchTableEntry
inCreditLink : NetworkInterface
incremental : VncInput::FrameBufferUpdateReq
index : ArmISA::MemoryReg , ArmISA::SveBinIdxUnpredOp , ArmISA::VldSingleOp64 , ArmISA::VstSingleOp64 , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::SQCPort , DataTranslation< ExecContextPtr > , LinkedFiber , MultiCompressor::MultiCompData , Prefetcher::IndirectMemory::PrefetchTableEntry , Prefetcher::PIF , StackDistCalc , Stats::DistProxy< Stat > , Stats::ScalarProxy< Stat > , TimeBuffer< T > , TimeBuffer< T >::wire , TimingExprRef , TimingExprSrcReg , TimingSimpleCPU::SplitFragmentSenderState , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , Trace::TarmacBaseRecord::RegEntry , TreePLRURP::TreePLRUReplData , VirtQueue::VirtRing< T >::Header , X86ISA::EmulEnv , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::MemOp
indexingPolicy : AssociativeSet< Entry > , BaseTags , Prefetcher::Stride::PCTableInfo
indexMask : LocalBP , StoreSet
indirect : Gicv3Its
indirectCounter : Prefetcher::IndirectMemory::PrefetchTableEntry
indirectHistory : BPredUnit::PredictorHistory
indirectHits : BPredUnit
indirectLookups : BPredUnit
indirectMispredicted : BPredUnit
indirectMisses : BPredUnit
infiniteSD : StackDistProbe
Infinity : StackDistCalc
inflight : RiscvISA::Walker::WalkerState , X86ISA::Walker::WalkerState
inFlightInsts : Minor::Execute::ExecuteThreadInfo
inflightLoads : GlobalMemPipeline
inFlightNodes : TraceCPU::ElasticDataGen::HardwareResource
inflightStores : GlobalMemPipeline
info : ArmISA::ISA::MiscRegLUTEntryInitializer , BmpWriter::CompleteV1Header , X86ISA::IntelMP::BusHierarchy
inFUMemInsts : Minor::Execute::ExecuteThreadInfo
iniFile : CxxIniFile
init : Brig::BrigDirectiveVariable
init_param : System
initConfidence : Prefetcher::Stride
initControlWord : X86ISA::I8259
initDone : sc_gem5::Scheduler
initEventStreamId : Iris::ThreadContext
initFunc : EmbeddedPyBind
initial_count : Intel8254Timer::Counter
initialApicId : X86ISA::I82094AA , X86ISA::Interrupts
initialized : DiskImage
Initialized : EventBase
initialized : sc_gem5::VcdTraceFile , TAGEBase
initialLoopAge : LoopPredictor
initialLoopIter : LoopPredictor
initialTCounterValue : TAGEBase
initialVal : SatCounter
initiator_port : tlm::tlm_slave_to_transport< REQ, RSP >
initiator_socket : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH > , MultiSocketSimpleSwitchAT , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
initList : sc_gem5::Scheduler
InitMask : EventBase
initMask : Wavefront
initValue : sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic >
initVector : X86ISA::Interrupts
initVirtMem : Process
injRate : GarnetSyntheticTraffic
injVnet : GarnetSyntheticTraffic
inLowPowerState : DRAMCtrl::Rank
inLSQ : Minor::MinorDynInst
inMacroop : Minor::Decode::DecodeThreadInfo
inMemorySystemLimit : Minor::LSQ
innerAttrs : ArmISA::TlbEntry
innerCache : Gicv3Its
inNetLink : NetworkInterface
inNode_ptr : NetworkInterface
inp : Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2
inputBuffer : Minor::Decode , Minor::Execute , Minor::Fetch2 , VirtualChannel
inputChar : MipsAccess
inputFull : X86ISA::I8042
inputIndex : Minor::Decode::DecodeThreadInfo , Minor::Execute::ExecuteThreadInfo , Minor::Fetch2::Fetch2ThreadInfo
inputParam1 : UFSHostDevice::UTPUPIUTaskReq
inputParam2 : UFSHostDevice::UTPUPIUTaskReq
inputParam3 : UFSHostDevice::UTPUPIUTaskReq
inputs : sc_core::sc_signal_resolved , sc_core::sc_signal_rv< W > , X86ISA::I82094AA , X86ISA::I8259
inputWire : Minor::Latch< Data >::Input
inRetry : DmaPort
insertedLoads : MemDepUnit< MemDepPred, Impl >
insertedStores : MemDepUnit< MemDepPred, Impl >
insertions : SMMUv3BaseCache
insertionsByStageLevel : WalkCache
inserts : ArmISA::TLB
inService : QueueEntry
inst : BaseSimpleCPU , BPredUnit::PredictorHistory , DependencyEntry< DynInstPtr > , InstructionQueue< Impl >::FUCompletion , LSQ< Impl >::LSQSenderState , LSQUnit< Impl >::LSQEntry , LSQUnit< Impl >::WritebackEvent , MemDepUnit< MemDepPred, Impl >::MemDepEntry , Minor::BranchData , Minor::ExecContext , Minor::LSQ::LSQRequest , Minor::QueuedInst , TimingExprEvalContext , Trace::TarmacParserRecord::TarmacParserRecordEvent
instAccesses : ArmISA::TLB
instance : Event , GpuDispatcher , Kvm
instanceCounter : Event
instBytes : X86ISA::Decoder
instCacheMap : X86ISA::Decoder
instcfg : StreamTableEntry
instCnt : BaseCPU
instcount : FullO3CPU< Impl >
instCount : Trace::TarmacTracerRecord::TraceInstEntry
instCyclesSALU : ComputeUnit
instCyclesVALU : ComputeUnit
instData : Gcn3ISA::Inst_DS , Gcn3ISA::Inst_EXP , Gcn3ISA::Inst_FLAT , Gcn3ISA::Inst_MIMG , Gcn3ISA::Inst_MTBUF , Gcn3ISA::Inst_MUBUF , Gcn3ISA::Inst_SMEM , Gcn3ISA::Inst_SOP1 , Gcn3ISA::Inst_SOP2 , Gcn3ISA::Inst_SOPC , Gcn3ISA::Inst_SOPK , Gcn3ISA::Inst_SOPP , Gcn3ISA::Inst_VINTRP , Gcn3ISA::Inst_VOP1 , Gcn3ISA::Inst_VOP2 , Gcn3ISA::Inst_VOP3 , Gcn3ISA::Inst_VOP3_SDST_ENC , Gcn3ISA::Inst_VOPC
instDone : ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
instFetchInstReturned : FetchStage
instFlags : BaseDynInst< Impl >
instHits : ArmISA::TLB
instLastTick : TraceCPU::FixedRetryGen
instList : Checker< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl > , ROB< Impl >
instListIt : BaseDynInst< Impl >
instMap : GenericISA::BasicDecodeCache , RiscvISA::Decoder , X86ISA::Decoder
instMasterID : TraceCPU
instMisses : ArmISA::TLB
instMnem : X86ISA::X86MicroopBase
instName : RiscvISA::UnimplementedFault
instNum : ElasticTrace::TraceInfo
inStoreBuffer : Minor::MinorDynInst
instPort : BaseKvmCPU , SimpleMemobj
instQueue : DefaultIEW< Impl > , Trace::TarmacTracer
instRecord : Trace::TarmacParserRecord
instResult : BaseDynInst< Impl >
instrExecuted : ExecStage
INSTRUCTION_ATC : Gcn3ISA::StatusReg
instructionBuffer : Wavefront
instructions : ControlFlowInfo
insts : DefaultDecode< Impl > , DefaultDecodeDefaultRename< Impl > , DefaultFetchDefaultDecode< Impl > , DefaultIEW< Impl > , DefaultIEWDefaultCommit< Impl > , DefaultRename< Impl > , DefaultRenameDefaultIEW< Impl > , IssueStruct< Impl > , Minor::ForwardInstData , SimPoint::BBInfo
instsBeingCommitted : Minor::Execute::ExecuteThreadInfo
instsCommitted : DefaultCommit< Impl >
instSeqNum : DefaultRename< Impl >::RenameHistory
instShift : SimpleIndirectPredictor
instShiftAmt : BPredUnit , DefaultBTB , TAGEBase
instsInProgress : DefaultRename< Impl >
instSize : DefaultFetch< Impl > , Trace::TarmacTracerRecord::TraceInstEntry
instsToExecute : InstructionQueue< Impl >
instsToReplay : MemDepUnit< MemDepPred, Impl >
instToWaitFor : Minor::MinorDynInst
instTraceFile : TraceCPU
instTraceStream : ElasticTrace
int : sc_dt::sc_fxnum_fast , sc_dt::sc_fxval_fast
INT_BITS_MAX : GicV2
INT_BUS_ERROR : HDLcd
INT_LINES_MAX : GicV2
int_mask : HDLcd
int_rawstat : HDLcd
INT_UNDERRUN : HDLcd
INT_VSYNC : HDLcd
intAluAccesses : InstructionQueue< Impl >
intBase : GenericArmPciHost
intConfig : GicV2
intCount : GenericArmPciHost
intCtl : Iob
intDelay : AmbaIntDevice , Pl011
integer : InstResult::MultiResult
integrationTestEnabled : Sp805
intEnable : A9GlobalTimer::Timer , CpuLocalTimer::Timer , Sp804::Timer
intEnabled : GicV2::BankedRegs , GicV2
interEvent : IGbE
interface : EtherLink , EtherSwitch::SwitchTableEntry , EtherTapBase , NSGigE , sc_core::sc_export< IF > , sc_gem5::Port::Binding , Sinic::Base
interfaceCallback : SerialDevice
interfaceId : EtherSwitch::Interface
interfaces : EtherSwitch
intermediateHeader : X86ISA::SMBios::SMBiosTable::SMBiosHeader
interpImage : Process
interpreter : Loader::ElfObject
interrupt : ArmISA::PMU , DefaultCommit< Impl > , MmioVirtIO
interruptDeliveryPending : PciVirtIO
interruptLine : PCIConfig
interruptMap : NoMaliGpu
interruptPending : DefaultFetch< Impl > , TimeBufStruct< Impl >::commitComm
interruptPin : PCIConfig , PciHost::DeviceInterface
interruptPriority : Minor::Execute
interrupts : ArmISA::Interrupts , BaseCPU , SparcISA::Interrupts
interruptStatus : MmioVirtIO
interruptType : X86ISA::IntelMP::IntAssignment
interval : Intel8254Timer::Counter::CounterEvent , MC146818::RTCEvent , MemTest
intervalCount : SimPoint
intervalDrift : SimPoint
intervalSize : SimPoint
intEvent : Pl011 , Pl111
intGroup : GicV2::BankedRegs , GicV2
inTick : IGbE
intid : Gicv3CPUInterface::hppi_t
INTID_NONSECURE : Gicv3
INTID_SECURE : Gicv3
INTID_SPURIOUS : Gicv3
intInstQueueReads : InstructionQueue< Impl >
intInstQueueWakeupAccesses : InstructionQueue< Impl >
intInstQueueWrites : InstructionQueue< Impl >
intInstructions : Minor::Fetch2
intLatency : GicV2
intList : UnifiedFreeList
intlvMatch : AddrRange
intMan : Iob
intMap : UnifiedRenameMap
intMasterPort : X86ISA::I82094AA , X86ISA::Interrupts
intNum : A9GlobalTimer::Timer , AmbaDmaDevice , AmbaIntDevice , ArmInterruptPin , Gicv3Its , Pl011 , Sp804::Timer , UFSHostDevice
intNumHyp : Gicv3Its
intOffset : ThreadContext
intPin : X86ISA::Cmos::X86RTC , X86ISA::I8254
intPolicy : GenericArmPciHost
intPriority : GicV2::BankedRegs , GicV2
intr_sum_type : Malta
intRaised : Sp805
intrClockFrequency : MipsAccess
intrctrl : CopyEngineReg::Regs , Platform
intrDelay : NSGigE , Sinic::Base
intReg32Ids : Iris::ThreadContext
intReg32IdxNameMap : FastModel::CortexA76TC
intReg64Ids : Iris::ThreadContext
intReg64IdxNameMap : FastModel::CortexA76TC
intRegFile : PhysRegFile
intRegfileReads : FullO3CPU< Impl >
intRegfileWrites : FullO3CPU< Impl >
intRegIds : PhysRegFile
intRegMap : ArmISA::ISA , ArmV8KvmCPU , SparcISA::ISA
intRegs : SimpleThread
intRenameLookups : DefaultRename< Impl >
intResult : ThreadContext
intrEvent : NSGigE , Sinic::Base
IntrMask : Sinic::Device
intrPending : IdeDisk
IntrStatus : Sinic::Device
intrTick : NSGigE , Sinic::Base
ints : ThreadContext
intSlavePort : X86ISA::Interrupts
IntSourcePinBase : IntSinkPinBase
intStatus : ArmISA::Interrupts , IdeController , SparcISA::Interrupts
intTimer : CpuLocalTimer::Timer
intType : Gicv3Its
intWatchdog : CpuLocalTimer::Timer
intWidth : ArmISA::ArmStaticInst
invAddrLoads : LSQUnit< Impl >
invAddrSwpfs : LSQUnit< Impl >
invalidationCallbacks : MemBackdoor
invalidName : CxxConfigParams
invalidPredictorIndex : TournamentBP
invariant_regs : ArmKvmCPU
inVisit : CxxConfigManager
invldPid : BaseCPU
io : Malta
ioApic : SouthBridge
iobJBusAddr : Iob
iobJBusSize : Iob
iobManAddr : Iob
iobManSize : Iob
ioe : Pl111
ioEnable : NSGigE
ioEnabled : IdeController
ioShift : IdeController
iov_base : ArmFreebsd32::tgt_iovec , ArmFreebsd64::tgt_iovec , ArmLinux32::tgt_iovec , ArmLinux64::tgt_iovec , Linux::tgt_iovec , OperatingSystem::tgt_iovec , X86Linux64::tgt_iovec
iov_len : ArmFreebsd32::tgt_iovec , ArmFreebsd64::tgt_iovec , ArmLinux32::tgt_iovec , ArmLinux64::tgt_iovec , Linux::tgt_iovec , OperatingSystem::tgt_iovec , X86Linux64::tgt_iovec
ip : RiscvISA::Interrupts
ipa : IPACache::Entry , SMMUEvent
ipaCache : SMMUv3
ipaCacheEnable : SMMUv3
ipaLat : SMMUv3
ipaMask : IPACache::Entry
ipaSem : SMMUv3
ipc : ComputeUnit , FullO3CPU< Impl > , Minor::MinorStats , Pl111
ipd : Prefetcher::IndirectMemory
ipdEntryTrackingMisses : Prefetcher::IndirectMemory
ipi_pending : Malta
iPred : BPredUnit
ips : ContextDescriptor
iqBranchInstsIssued : InstructionQueue< Impl >
iqCount : TimeBufStruct< Impl >::iewComm
iqEntries : DefaultRename< Impl >::FreeEntries
iqFloatInstsIssued : InstructionQueue< Impl >
iqInstsAdded : InstructionQueue< Impl >
iqInstsIssued : InstructionQueue< Impl >
iqIntInstsIssued : InstructionQueue< Impl >
iqMemInstsIssued : InstructionQueue< Impl >
iqMiscInstsIssued : InstructionQueue< Impl >
iqNonSpecInstsAdded : InstructionQueue< Impl >
iqPolicy : InstructionQueue< Impl >
iqPtr : InstructionQueue< Impl >::FUCompletion , MemDepUnit< MemDepPred, Impl >
iqSquashedInstsExamined : InstructionQueue< Impl >
iqSquashedInstsIssued : InstructionQueue< Impl >
iqSquashedNonSpecRemoved : InstructionQueue< Impl >
iqSquashedOperandsExamined : InstructionQueue< Impl >
ir0 : ContextDescriptor
ir1 : ContextDescriptor
IRM : Gicv3Distributor
irq_ctrl : SMMURegs
irq_ctrlack : SMMURegs
irqActive : Gicv3Distributor , Gicv3Redistributor
irqAffinityRouting : Gicv3Distributor
irqAsserted : ArmKvmCPU , BaseArmKvmCPU
irqConfig : Gicv3Distributor , Gicv3Redistributor
irqEnabled : Gicv3Distributor , Gicv3Redistributor
irqGroup : Gicv3Distributor , Gicv3Redistributor
irqGrpmod : Gicv3Distributor , Gicv3Redistributor
irqHyp : GenericTimer::CoreTimers
irqNsacr : Gicv3Distributor , Gicv3Redistributor
irqPending : Gicv3Distributor , Gicv3Redistributor
irqPhysNS : GenericTimer::CoreTimers
irqPhysS : GenericTimer::CoreTimers
irqPriority : Gicv3Distributor , Gicv3Redistributor
irqVirt : GenericTimer::CoreTimers
IRR : X86ISA::I8259
IRRV : X86ISA::Interrupts
is_device : ArmV8KvmCPU::MiscRegInfo
is_imm : RegOrImmOperand< RegOperand, T >
isa : ArmISA::BaseISADevice , FullO3CPU< Impl > , SimpleThread
isAbort : DistIface::Sync
isAtsRequest : SMMUTranslRequest
isBusy : SimpleMemory
isetstate : Trace::TarmacBaseRecord::InstEntry , Trace::TarmacBaseRecord::RegEntry
IsExitEvent : EventBase
isFetch : ArmISA::TableWalker::WalkerState
isFill : Prefetcher::Base::PrefetchListener
isForward : MSHR
isHyp : ArmISA::TableWalker::WalkerState , ArmISA::TLB , ArmISA::TlbEntry
isInWriteQueue : DRAMCtrl
isLeftNode : StackDistCalc::Node
isLoad : LSQ< Impl >::LSQSenderState , Minor::LSQ::LSQRequest
IsMainQueue : EventBase
isMarked : StackDistCalc::Node
isMaster : CxxConfigDirectoryEntry::PortDesc , DistIface
isMerging : ArmISA::SvePartBrkOp , ArmISA::SveUnaryWideImmPredOp
isParallel : BloomFilter::MultiBitSel
isPrefetch : SMMUTranslRequest
isPriv : ArmISA::TLB
isr : dp_regs
ISR : X86ISA::I8259
isRead : DramGen , HSAPacketProcessor::CmdQueueCmdDmaEvent
isReadOnly : BaseCache
isref : ThermalNode
ISRV : X86ISA::Interrupts
iss : McrMrcMiscInst
isSecure : ArmISA::TableWalker::WalkerState , ArmISA::TLB , QueueEntry
isSel : ArmISA::SvePredLogicalOp
isSimObject : CxxConfigDirectoryEntry::ParamDesc
isSplit : LSQ< Impl >::LSQSenderState , WholeTranslationState
issRaw : ArmISA::ArmFault
isStage2 : ArmISA::TableWalker , ArmISA::TLB
isStoreBlocked : LSQUnit< Impl >
issue_time : GPUCoalescerRequest , SequencerRequest
issuedPrefetches : Prefetcher::Base
issuedToMemory : Minor::LSQ::LSQRequest
issuedTranslationsTable : TLBCoalescer
issueEvent : GPUCoalescer
issueLat : MinorFU
issueLimit : Minor::Execute
issuePeriod : ComputeUnit
issuePipelinedIfetch : DefaultFetch< Impl >
issuePrefetchRequests : Prefetcher::BOP
issuePriority : Minor::Execute
issueRate : InstructionQueue< Impl >
issueTime : X86ISA::GpuTLB::TranslationState
issueToExecQueue : DefaultIEW< Impl >
issueToExecuteDelay : DefaultIEW< Impl >
issueToExecuteQueue : InstructionQueue< Impl >
issueWidth : DefaultIEW< Impl >
isSwitch : DistIface , TCPIface
istatus : ArchTimer
isTcp : IGbE::TxDescCache
isTimingMode : DRAMCtrl
isTranslationDelayed : Minor::LSQ::LSQRequest
isUncacheable : ArmISA::TableWalker::WalkerState
isv : ArmISA::DataAbort
isVector : CxxConfigDirectoryEntry::ParamDesc , CxxConfigDirectoryEntry::PortDesc
isWrite : ArmISA::TableWalker::WalkerState , SMMUTranslRequest
it : SnoopFilter::ReqLookupResult
it_ : sc_core::sc_vector_iter< Element, AccessPolicy >
itb : CheckerCPU , FullO3CPU< Impl > , SimpleThread
itBits : ArmISA::Decoder
item : std::deque< T > , std::list< T > , std::vector< T >
item1 : std::pair< X, Y >
item2 : std::pair< X, Y >
items : DecodeCache::AddrMap< Value >::CachePage
itLines : GicV2 , Gicv3Distributor
itr : iGbReg::Regs
its : Gicv3 , Gicv3Its::DataPort , ItsProcess
itsControl : Gicv3Its
itsNumber : Gicv3Its
itsTranslate : Gicv3Its
ittAddress : Gicv3Its
ittEntrySize : Gicv3Its
ittRange : Gicv3Its
ittReadRead : CommMonitor::MonitorStats
ittReqReq : CommMonitor::MonitorStats
ittWriteWrite : CommMonitor::MonitorStats
ix_start : HSAPacketProcessor::CmdQueueCmdDmaEvent