- w -

• w1 : top< T >
• w2 : top< T >
• wait_for_all : kfd_ioctl_wait_events_args
• wait_result : kfd_ioctl_wait_events_args
• waitForRetry : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• waiting : AddressMonitor , SMMUSignal
• waitingForLayer : BaseXBar::Layer< SrcType, DstType >
• waitingForPeer : BaseXBar::Layer< SrcType, DstType >
• waitingOnRetry : PacketQueue
• waitingPortId : SimpleCache
• waitingResp : BaseTrafficGen
• waitNum : DistIface::Sync
• wakeUpAllowedAt : DRAMCtrl::Rank
• wakeupDelay : HWScheduler
• wakeUpEvent : DRAMCtrl::Rank
• wakeupGuard : Minor::Fetch1::Fetch1ThreadInfo
• walkCache : SMMUv3
• walkCacheEnable : SMMUv3
• walkCacheNonfinalEnable : SMMUv3
• walkCacheS1Levels : SMMUv3
• walkCacheS2Levels : SMMUv3
• walker : RiscvISA::TLB , RiscvISA::Walker::WalkerPort , RiscvISA::Walker::WalkerState , X86ISA::GpuTLB , X86ISA::TLB , X86ISA::Walker::WalkerPort , X86ISA::Walker::WalkerState
• walkLat : SMMUv3
• walkSem : SMMUv3
• warmedUp : BaseTags
• warmupBound : BaseTags
• warmupCycle : BaseTags::BaseTagStats
• warned : SparcISA::WarnUnimplemented , WarnUnimplemented
• warning : MiscRegImplDefined64
• warnOnly : MemCheckerMonitor
• warnOnlyOnLoadError : CheckerCPU
• wasCall : BPredUnit::PredictorHistory
• wasIndirect : BPredUnit::PredictorHistory
• wasReturn : BPredUnit::PredictorHistory
• wasWholeLineWrite : MSHR
• watchdogControl : CpuLocalTimer::Timer
• watchdogDisableReg : CpuLocalTimer::Timer
• watchdogLoadValue : CpuLocalTimer::Timer
• watchdogMode : CpuLocalTimer::Timer
• watchdogZeroEvent : CpuLocalTimer::Timer
• waterMark : Pl111
• watermark : Pl111
• wavefront : ComputeUnit::ITLBPort::SenderState , ComputeUnit::SQCPort::SenderState , Gcn3ISA::GPUISA
• wavefrontSize : ComputeUnit
• waveIDQueue : ComputeUnit::waveQueue
• waveList : FetchUnit
• waveStatusList : ComputeUnit , ScheduleStage , ScoreboardCheckStage
• wb : ArmISA::RfeOp , ArmISA::SrsOp , ArmISA::VldMultOp64 , ArmISA::VldSingleOp64 , ArmISA::VstMultOp64 , ArmISA::VstSingleOp64 , StatisticalCorrector
• wbAlignment : IGbE::DescCache< T >
• wbBuf : IGbE::DescCache< T >
• wbCompDelay : IGbE
• wbCycle : DefaultIEW< Impl >
• wbDelay : IGbE
• wbDelayEvent : IGbE::DescCache< T >
• wbEvent : IGbE::DescCache< T >
• wbFanout : DefaultIEW< Impl >
• wbNumInst : DefaultIEW< Impl >
• wbOut : IGbE::DescCache< T >
• wbOutstanding : InstructionQueue< Impl >
• wbRate : DefaultIEW< Impl >
• wbStatus : DefaultIEW< Impl >
• wbw : StatisticalCorrector
• wbWidth : DefaultIEW< Impl >
• wcsr : dp_regs
• wday : MC146818
• WDOGLOCK_MAGIC : Sp805
• weight : QoS::PropFairPolicy
• wen : FVPBasePwrCtrl
• wf : GPUExecContext
• wfDynId : GPUDynInst , Wavefront
• wfId : Wavefront
• wfList : ComputeUnit
• wfSize : CallArgMem
• wfSlotId : ComputeUnit::waveIdentifier , GPUDynInst , Wavefront
• wfWait : ComputeUnit
• wg : MPP_StatisticalCorrector , TAGE_SC_L_8KB_StatisticalCorrector
• wg_disp_rem : NDRange
• wgBlockedDueLdsAllocation : ComputeUnit
• wgId : NDRange , Wavefront
• wgSize : HsaQueueEntry
• wgSz : Wavefront
• when : Trace::InstRecord
• whenReady : CacheBlk
• wi : StatisticalCorrector
• wide : ArmISA::VfpMacroOp
• width : AtomicSimpleCPU , BaseXBar
• Width : BmpWriter::InfoHeaderV1
• width : Brig::BrigInstBr , Brig::BrigInstLane , Brig::BrigInstMem , Brig::BrigOperandConstantImage , cp::Format , DisplayTimings , HsailISA::Barrier , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::CbrInstBase< TargetType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , MultiperspectivePerceptron::HistorySpec , Pl111 , VncInput::FrameBufferUpdateReq , VncServer::FrameBufferRect
• willChangePC : CheckerCPU
• wim : SparcISA::RemoteGDB::SPARCGdbRegCache , TAGE_SC_L_64KB_StatisticalCorrector
• WindowOverlap : SparcISA::ISA
• windowSize : TraceCPU::ElasticDataGen::InputStream , TraceCPU::ElasticDataGen
• withLoopBits : LoopPredictor
• withPC : MemTraceProbe
• wk : FVPBasePwrCtrl
• wl : StatisticalCorrector
• work : sc_gem5::ScEvent
• workaroundDmaLineCount : HDLcd
• workaroundSwapRB : HDLcd
• workgroup_size_x : _hsa_dispatch_packet_s , hsa_kernel_dispatch_packet_s
• workgroup_size_y : _hsa_dispatch_packet_s , hsa_kernel_dispatch_packet_s
• workgroup_size_z : _hsa_dispatch_packet_s , hsa_kernel_dispatch_packet_s
• workGroupId : Wavefront
• workGroupSz : Wavefront
• workItemFlatId : Wavefront
• workItemId : Wavefront
• workItemsBegin : System
• workItemsEnd : System
• workItemStats : System
• workload : CheckerCPU , System
• wp : MPP_StatisticalCorrector , TAGE_SC_L_64KB_StatisticalCorrector
• wr : RealViewCtrl
• wrAccesses : X86ISA::TLB
• wrAllowedAt : DRAMCtrl::Bank
• wrappedFileStream : ProtoInputStream , ProtoOutputStream
• wrapper : DRAMSim2 , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , sc_gem5::TlmToGem5Bridge< BITWIDTH >
• wrBufSlotsRemaining : SMMUv3SlaveInterface
• wrGmReqsInPipe : Wavefront
• writable : SMMUTranslationProcess::TranslResult , X86ISA::TlbEntry
• write : ArmISA::AbortFault< T > , DMARequest , Prefetcher::Base::PrefetchInfo , Sinic::Regs::Info , X86ISA::PageFault
• write_accesses : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• write_acv : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• write_byte : Intel8254Timer::Counter
• write_dispatch_id : _amd_queue_s
• write_hits : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• write_misses : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• write_pointer_address : kfd_ioctl_create_queue_args
• writeAccess : FlashDevice::FlashDeviceStats
• writeAccessEnabled : Sp805
• writeAccesses : ArmISA::TLB
• writeAddrDist : CommMonitor::MonitorStats
• writeAddrMask : CommMonitor::MonitorStats
• writeAllocator : BaseCache
• writebackClean : BaseCache
• writebackCount : DefaultIEW< Impl >
• writebacks : BaseCache::CacheStats
• writebackTempBlockAtomicEvent : BaseCache
• writeBandwidthHist : CommMonitor::MonitorStats
• writeBuffer : BaseCache
• writeBufferSize : DRAMCtrl , QoS::MemSinkCtrl
• writeBurstLengthHist : CommMonitor::MonitorStats
• writeBursts : DRAMCtrl::DRAMStats
• writeBW : BaseTrafficGen::StatGroup
• writeClusters : MemChecker::ByteTracker
• writeCompleteEvent : CopyEngine::CopyEngineChannel
• writeDoneEvent : DRAMCtrl::Rank , UFSHostDevice
• writeEnergy : DRAMCtrl::RankStats
• writeEntries : DRAMCtrl::Rank
• writeHighThreshold : DRAMCtrl
• writeHits : ArmISA::TLB
• writeIndex : HSAQueueDescriptor
• writeLatency : FlashDevice::FlashDeviceStats , FlashDevice
• writeLatencyHist : CommMonitor::MonitorStats
• writeLinearHist : StackDistProbe
• writeLogHist : StackDistProbe
• writeLowThreshold : DRAMCtrl
• writeMisses : ArmISA::TLB
• writePendingNum : UFSHostDevice
• writePktSize : DRAMCtrl::DRAMStats
• writePorts : RubyTester
• writeQueue : DRAMCtrl , QoS::MemSinkCtrl
• writeQueueSizes : QoS::MemCtrl
• writeReqDelay : SimpleMemDelay
• writeReqs : DRAMCtrl::DRAMStats
• writeRespDelay : SimpleMemDelay
• writeRowHitRate : DRAMCtrl::DRAMStats
• writeRowHits : DRAMCtrl::DRAMStats
• writes : MemChecker::WriteCluster , RiscvISA::Walker::WalkerState , X86ISA::Walker::WalkerState
• writesBitmap : MSHR::TargetList
• writeStamp : sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS > , sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
• writesThisTime : DRAMCtrl
• writeTrans : CommMonitor::MonitorStats
• writeTransHist : CommMonitor::MonitorStats
• writingInst : Minor::Scoreboard
• writtenBytes : CommMonitor::MonitorStats
• wrLmReqsInPipe : Wavefront
• wrMisses : X86ISA::TLB
• wroteToTimeBuffer : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• wrPerTurnAround : DRAMCtrl::DRAMStats
• wrQLenPdf : DRAMCtrl::DRAMStats
• wrToRdDly : DRAMCtrl
• wrToRdDlySameBG : DRAMCtrl
• ws : MPP_StatisticalCorrector_64KB , TAGE_SC_L_64KB_StatisticalCorrector
• wt : MPP_StatisticalCorrector_64KB , TAGE_SC_L_64KB_StatisticalCorrector
• wxn : ContextDescriptor