fetch2.hh

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/*
 * Copyright (c) 2013-2014 ARM Limited
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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * met: redistributions of source code must retain the above copyright
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#ifndef __CPU_MINOR_FETCH2_HH__
#define __CPU_MINOR_FETCH2_HH__

#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/pred/bpred_unit.hh"
#include "params/MinorCPU.hh"

namespace Minor
{

class Fetch2 : public Named
{
  protected:
    MinorCPU &cpu;

    Latch<ForwardLineData>::Output inp;

    Latch<BranchData>::Output branchInp;

    Latch<BranchData>::Input predictionOut;

    Latch<ForwardInstData>::Input out;

    std::vector<InputBuffer<ForwardInstData>> &nextStageReserve;

    unsigned int outputWidth;

    bool processMoreThanOneInput;

    BPredUnit &branchPredictor;

  public:
    /* Public so that Pipeline can pass it to Fetch1 */
    std::vector<InputBuffer<ForwardLineData>> inputBuffer;

  protected:
    struct Fetch2ThreadInfo {

        Fetch2ThreadInfo() :
            inputIndex(0),
            pc(TheISA::PCState(0)),
            havePC(false),
            lastStreamSeqNum(InstId::firstStreamSeqNum),
            fetchSeqNum(InstId::firstFetchSeqNum),
            expectedStreamSeqNum(InstId::firstStreamSeqNum),
            predictionSeqNum(InstId::firstPredictionSeqNum),
            blocked(false)
        { }

        Fetch2ThreadInfo(const Fetch2ThreadInfo& other) :
            inputIndex(other.inputIndex),
            pc(other.pc),
            havePC(other.havePC),
            lastStreamSeqNum(other.lastStreamSeqNum),
            expectedStreamSeqNum(other.expectedStreamSeqNum),
            predictionSeqNum(other.predictionSeqNum),
            blocked(other.blocked)
        { }

        unsigned int inputIndex;


        TheISA::PCState pc;

        bool havePC;

        InstSeqNum lastStreamSeqNum;

        InstSeqNum fetchSeqNum;

        InstSeqNum expectedStreamSeqNum;

        InstSeqNum predictionSeqNum;

        bool blocked;
    };

    std::vector<Fetch2ThreadInfo> fetchInfo;
    ThreadID threadPriority;

    Stats::Scalar intInstructions;
    Stats::Scalar fpInstructions;
    Stats::Scalar vecInstructions;
    Stats::Scalar loadInstructions;
    Stats::Scalar storeInstructions;
    Stats::Scalar amoInstructions;

  protected:
    const ForwardLineData *getInput(ThreadID tid);

    void popInput(ThreadID tid);

    void dumpAllInput(ThreadID tid);

    void updateBranchPrediction(const BranchData &branch);

    void predictBranch(MinorDynInstPtr inst, BranchData &branch);

    ThreadID getScheduledThread();

  public:
    Fetch2(const std::string &name,
        MinorCPU &cpu_,
        MinorCPUParams &params,
        Latch<ForwardLineData>::Output inp_,
        Latch<BranchData>::Output branchInp_,
        Latch<BranchData>::Input predictionOut_,
        Latch<ForwardInstData>::Input out_,
        std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);

  public:
    void evaluate();

    void minorTrace() const;

    void regStats();

    bool isDrained();
};

}

#endif /* __CPU_MINOR_FETCH2_HH__ */