#include <cpu_dummy.hh>

Inheritance diagram for BaseCPU:

Public Types
typedef BaseCPUParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
virtual Port &	getDataPort ()=0
	Purely virtual method that returns a reference to the data port. More...

virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

virtual Port &	getInstPort ()=0
	Purely virtual method that returns a reference to the instruction port. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

MasterID	dataMasterId () const
	Reads this CPU's unique data requestor ID. More...

MasterID	instMasterId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

virtual void	wakeup (ThreadID tid)=0

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadContext *tc) const

void	processProfileEvent ()

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active. More...

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended. More...

virtual void	haltContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now halted. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

void	startup () override
	startup() is the final initialization call before simulation. More...

void	regStats () override
	Callback to set stat parameters. More...

void	regProbePoints () override
	Register probe points for this object. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution. More...

virtual void	takeOverFrom (BaseCPU *cpu)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

virtual void	serializeThread (CheckpointOut &cp, ThreadID tid) const
	Serialize a single thread. More...

virtual void	unserializeThread (CheckpointIn &cp, ThreadID tid)
	Unserialize one thread. More...

virtual Counter	totalInsts () const =0

virtual Counter	totalOps () const =0

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from SimObject
virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

const Params *	params () const

	SimObject (const Params *_params)

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Static Public Member Functions
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Public Attributes
TheISA::MicrocodeRom	microcodeRom

EventFunctionWrapper *	profileEvent

ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Public Attributes inherited from ClockedObject
PowerState *	powerState

Static Public Attributes
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Protected Types
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Member Functions
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

MasterID	_instMasterId
	instruction side request id that must be placed in all requests More...

MasterID	_dataMasterId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Member Functions
void	enableFunctionTrace ()

void	traceFunctionsInternal (Addr pc)

Private Attributes
bool	functionTracingEnabled

std::ostream *	functionTraceStream

Addr	currentFunctionStart

Addr	currentFunctionEnd

Tick	functionEntryTick

std::vector< AddressMonitor >	addressMonitor

Static Private Attributes
static std::vector< BaseCPU * >	cpuList
	Static global cpu list. More...

PMU Probe points.
ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Detailed Description

Definition at line 43 of file cpu_dummy.hh.

Member Typedef Documentation

◆ Params

typedef BaseCPUParams BaseCPU::Params

Definition at line 306 of file base.hh.

Member Enumeration Documentation

◆ CPUState

enum BaseCPU::CPUState

protected

Enumerator
CPU_STATE_ON
CPU_STATE_SLEEP
CPU_STATE_WAKEUP

Definition at line 518 of file base.hh.

Constructor & Destructor Documentation

◆ BaseCPU()

BaseCPU::BaseCPU	(	Params *	params,
		bool	is_checker = `false`
	)

Definition at line 125 of file base.cc.

References _cpuId, _socketId, cpuList, csprintf(), currentFunctionEnd, currentFunctionStart, DPRINTF, enableFunctionTrace(), enterPwrGating(), MipsISA::event, fatal, fatal_if, OutputDirectory::findOrCreate(), FullSystem, functionEntryTick, functionTraceStream, functionTracingEnabled, interrupts, maxThreadsPerCPU, SimObject::name(), numThreads, MipsISA::p, params(), processProfileEvent(), profileEvent, EventManager::schedule(), simout, OutputStream::stream(), and tracer.

◆ ~BaseCPU()

BaseCPU::~BaseCPU ( )

virtual

Reimplemented in Iris::BaseCPU.

Definition at line 204 of file base.cc.

References profileEvent.

Member Function Documentation

◆ activateContext()

void BaseCPU::activateContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now active.

Reimplemented in TimingSimpleCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, AtomicSimpleCPU, MinorCPU, and BaseKvmCPU.

Definition at line 487 of file base.cc.

References CPU_STATE_WAKEUP, EventManager::deschedule(), DPRINTF, enterPwrGatingEvent, ClockedObject::powerState, Event::scheduled(), PowerState::set(), threadContexts, and updateCycleCounters().

Referenced by SimpleThread::activate(), MinorCPU::activateContext(), AtomicSimpleCPU::activateContext(), FullO3CPU< O3CPUImpl >::activateContext(), TimingSimpleCPU::activateContext(), Shader::hostWakeUp(), and FullO3CPU< O3CPUImpl >::numActiveThreads().

◆ armMonitor()

void BaseCPU::armMonitor	(	ThreadID	tid,
		Addr	address
	)

Definition at line 210 of file base.cc.

References addressMonitor, AddressMonitor::armed, DPRINTF, numThreads, AddressMonitor::pAddr, and AddressMonitor::vAddr.

Referenced by Minor::ExecContext::armMonitor(), CheckerCPU::armMonitor(), and SimpleExecContext::armMonitor().

◆ cacheLineSize()

unsigned int BaseCPU::cacheLineSize ( ) const

inline

Get the cache line size of the system.

Definition at line 387 of file base.hh.

References serialize(), and unserialize().

Referenced by AtomicSimpleCPU::amoMem(), Minor::Fetch1::Fetch1(), AtomicSimpleCPU::genMemFragmentRequest(), CheckerCPU::genMemFragmentRequest(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), ThreadState::initMemProxies(), Iris::ThreadContext::initMemProxies(), mwait(), mwaitAtomic(), and TimingSimpleCPU::writeMem().

◆ checkInterrupts()

bool BaseCPU::checkInterrupts ( ThreadContext * tc ) const

inline

Definition at line 254 of file base.hh.

References FullSystem, and ThreadContext::threadId().

Referenced by BaseSimpleCPU::checkForInterrupts(), IntrControl::havePosted(), and Minor::Execute::isInterrupted().

◆ clearInterrupt()

void BaseCPU::clearInterrupt	(	ThreadID	tid,
		int	int_num,
		int	index
	)

inline

Definition at line 242 of file base.hh.

Referenced by SparcISA::ISA::checkSoftInt(), IntrControl::clear(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), ArmISA::AbortFault< DataAbort >::invoke(), ArmISA::SystemError::invoke(), ArmISA::ArmSev::invoke(), SparcISA::ISA::setFSReg(), and SparcISA::ISA::setMiscReg().

◆ clearInterrupts()

void BaseCPU::clearInterrupts ( ThreadID tid )

inline

Definition at line 248 of file base.hh.

Referenced by IntrControl::clearAll(), and ArmISA::Reset::invoke().

◆ contextToThread()

ThreadID BaseCPU::contextToThread ( ContextID cid )

inline

Convert ContextID to threadID.

Definition at line 302 of file base.hh.

Referenced by Minor::LSQ::tryToSend().

◆ cpuId()

int BaseCPU::cpuId ( ) const

inline

Reads this CPU's ID.

Definition at line 179 of file base.hh.

Referenced by Iris::ThreadContext::cpuId(), X86ISA::Interrupts::setCPU(), takeOverFrom(), Trace::TarmacContext::tarmacCpuName(), PseudoInst::workbegin(), and PseudoInst::workend().

◆ dataMasterId()

MasterID BaseCPU::dataMasterId ( ) const

inline

Reads this CPU's unique data requestor ID.

Definition at line 185 of file base.hh.

Referenced by AtomicSimpleCPU::amoMem(), BaseKvmCPU::doMMIOAccess(), AtomicSimpleCPU::genMemFragmentRequest(), X86KvmCPU::handleKvmExitIO(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), mwaitAtomic(), Minor::LSQ::pushRequest(), and TimingSimpleCPU::writeMem().

◆ deschedulePowerGatingEvent()

void BaseCPU::deschedulePowerGatingEvent ( )

Definition at line 451 of file base.cc.

References EventManager::deschedule(), enterPwrGatingEvent, and Event::scheduled().

Referenced by MinorCPU::drain(), AtomicSimpleCPU::drain(), TimingSimpleCPU::drain(), and FullO3CPU< O3CPUImpl >::drain().

◆ enableFunctionTrace()

void BaseCPU::enableFunctionTrace ( )

private

Definition at line 199 of file base.cc.

References functionTracingEnabled.

Referenced by BaseCPU().

◆ enterPwrGating()

void BaseCPU::enterPwrGating ( void )

protected

Definition at line 533 of file base.cc.

References RiscvISA::OFF, ClockedObject::powerState, and PowerState::set().

Referenced by BaseCPU().

◆ findContext()

int BaseCPU::findContext ( ThreadContext * tc )

Given a Thread Context pointer return the thread num.

Definition at line 476 of file base.cc.

References threadContexts.

Referenced by SparcISA::ISA::serialize().

◆ flushTLBs()

void BaseCPU::flushTLBs ( )

Flush all TLBs in the CPU.

This method is mainly used to flush stale translations when switching CPUs. It is also exported to the Python world to allow it to request a TLB flush after draining the CPU to make it easier to compare traces when debugging handover/checkpointing.

Definition at line 652 of file base.cc.

References BaseTLB::flushAll(), ThreadContext::getCheckerCpuPtr(), ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), ArmISA::i, and threadContexts.

Referenced by switchOut().

◆ getContext()

virtual ThreadContext* BaseCPU::getContext ( int tn )

inlinevirtual

Given a thread num get tho thread context for it.

Reimplemented in BaseKvmCPU.

Definition at line 294 of file base.hh.

Referenced by Minor::Execute::commit(), Minor::Execute::commitInst(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Execute::executeMemRefInst(), Minor::Fetch1::fetchLine(), Minor::Fetch1::getScheduledThread(), Minor::Execute::handleMemResponse(), MinorCPU::init(), Shader::init(), Minor::Execute::isInterrupted(), Minor::Execute::issue(), Minor::Decode::popInput(), MipsISA::readRegOtherThread(), Minor::LSQ::recvTimingSnoopReq(), ElasticTrace::regProbeListeners(), Minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation(), MipsISA::setRegOtherThread(), Minor::LSQ::SingleDataRequest::startAddrTranslation(), Minor::Execute::takeInterrupt(), Minor::LSQ::threadSnoop(), Minor::Execute::tryPCEvents(), Minor::Execute::tryToBranch(), Minor::LSQ::tryToSend(), SparcISA::ISA::unserialize(), Shader::updateContext(), MipsISA::ISA::updateCPU(), and Minor::Fetch1::wakeupFetch().

◆ getCpuAddrMonitor()

AddressMonitor* BaseCPU::getCpuAddrMonitor ( ThreadID tid )

inline

Definition at line 610 of file base.hh.

Referenced by Minor::ExecContext::getAddrMonitor(), CheckerCPU::getAddrMonitor(), SimpleExecContext::getAddrMonitor(), Minor::LSQ::recvTimingSnoopReq(), TimingSimpleCPU::threadSnoop(), AtomicSimpleCPU::threadSnoop(), Minor::LSQ::threadSnoop(), and BaseSimpleCPU::wakeup().

◆ getCurrentInstCount()

Tick BaseCPU::getCurrentInstCount ( ThreadID tid )

Get the number of instructions executed by the specified thread on this CPU.

Used by Python to control simulation.

Parameters

tid	Thread monitor

Returns: Number of instructions executed

Definition at line 726 of file base.cc.

References threadContexts.

Referenced by scheduleInstStop().

◆ getDataPort()

virtual Port& BaseCPU::getDataPort ( )

pure virtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns: a reference to the data port

Implemented in TraceCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, MinorCPU, CheckerCPU, BaseKvmCPU, and Iris::BaseCPU.

Referenced by getPort(), TraceCPU::takeOverFrom(), and takeOverFrom().

◆ getInstPort()

virtual Port& BaseCPU::getInstPort ( )

pure virtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns: a reference to the instruction port

Implemented in TraceCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, MinorCPU, CheckerCPU, BaseKvmCPU, and Iris::BaseCPU.

Referenced by getPort(), TraceCPU::takeOverFrom(), and takeOverFrom().

◆ getInterruptController()

BaseInterrupts* BaseCPU::getInterruptController ( ThreadID tid )

inline

Definition at line 222 of file base.hh.

Referenced by Minor::Execute::checkInterrupts(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), Minor::Execute::hasInterrupt(), RiscvISA::ISA::readMiscReg(), ArmISA::ISA::readMiscReg(), RiscvISA::ISA::setMiscReg(), and Minor::Execute::takeInterrupt().

◆ getPid()

uint32_t BaseCPU::getPid ( ) const

inline

Definition at line 207 of file base.hh.

Referenced by takeOverFrom().

◆ getPort()

Port & BaseCPU::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

overridevirtual

Get a port on this CPU.

All CPUs have a data and instruction port, and this method uses getDataPort and getInstPort of the subclasses to resolve the two ports.

Parameters

if_name	the port name
idx	ignored index

Returns: a reference to the port with the given name

Reimplemented from SimObject.

Definition at line 417 of file base.cc.

References getDataPort(), getInstPort(), and SimObject::getPort().

Referenced by FastModel::CortexA76::getPort().

◆ getSendFunctional()

virtual PortProxy::SendFunctionalFunc BaseCPU::getSendFunctional ( )

inlinevirtual

Returns a sendFunctional delegate for use with port proxies.

Reimplemented in Iris::BaseCPU.

Definition at line 163 of file base.hh.

Referenced by ThreadState::initMemProxies().

◆ getTracer()

Trace::InstTracer* BaseCPU::getTracer ( )

inline

Provide access to the tracer pointer.

Definition at line 278 of file base.hh.

Referenced by Minor::Decode::popInput().

◆ haltContext()

void BaseCPU::haltContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now halted.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, and BaseKvmCPU.

Definition at line 527 of file base.cc.

References CPU_STATE_SLEEP, and updateCycleCounters().

Referenced by SimpleThread::halt(), and FullO3CPU< O3CPUImpl >::numActiveThreads().

◆ init()

void BaseCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from SimObject.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TraceCPU, MinorCPU, CheckerCPU, BaseSimpleCPU, BaseKvmCPU, AtomicSimpleCPU, and TimingSimpleCPU.

Definition at line 277 of file base.cc.

References MipsISA::event, ArmISA::i, numThreads, params(), registerThreadContexts(), scheduleInstStop(), threadContexts, and verifyMemoryMode().

Referenced by FullO3CPU< O3CPUImpl >::demapDataPage(), BaseKvmCPU::init(), BaseSimpleCPU::init(), Iris::BaseCPU::init(), MinorCPU::init(), TraceCPU::init(), and FullO3CPU< O3CPUImpl >::init().

◆ instCount()

Tick BaseCPU::instCount ( )

inline

Definition at line 213 of file base.hh.

Referenced by SparcISA::ISA::processHSTickCompare(), SparcISA::ISA::processSTickCompare(), SparcISA::ISA::readMiscReg(), SparcISA::ISA::setFSReg(), and SparcISA::ISA::setMiscReg().

◆ instMasterId()

MasterID BaseCPU::instMasterId ( ) const

inline

Reads this CPU's unique instruction requestor ID.

Definition at line 187 of file base.hh.

References InvalidPortID.

Referenced by Minor::Fetch1::fetchLine(), and BaseSimpleCPU::setupFetchRequest().

◆ mwait()

bool BaseCPU::mwait	(	ThreadID	tid,
		PacketPtr	pkt
	)

Definition at line 222 of file base.cc.

References addressMonitor, cacheLineSize(), DPRINTF, Packet::getAddr(), AddressMonitor::gotWakeup, ArmISA::mask, numThreads, AddressMonitor::pAddr, Packet::req, AddressMonitor::vAddr, and AddressMonitor::waiting.

Referenced by Minor::ExecContext::mwait(), CheckerCPU::mwait(), and SimpleExecContext::mwait().

◆ mwaitAtomic()

void BaseCPU::mwaitAtomic	(	ThreadID	tid,
		ThreadContext *	tc,
		BaseTLB *	dtb
	)

Definition at line 245 of file base.cc.

References addr, addressMonitor, cacheLineSize(), dataMasterId(), DPRINTF, ThreadContext::instAddr(), ArmISA::mask, NoFault, numThreads, AddressMonitor::pAddr, BaseTLB::Read, roundDown(), BaseTLB::translateAtomic(), AddressMonitor::vAddr, and AddressMonitor::waiting.

Referenced by Minor::ExecContext::mwaitAtomic(), CheckerCPU::mwaitAtomic(), and SimpleExecContext::mwaitAtomic().

◆ numContexts()

unsigned BaseCPU::numContexts ( )

inline

Get the number of thread contexts available.

Definition at line 297 of file base.hh.

◆ numSimulatedCPUs()

static int BaseCPU::numSimulatedCPUs ( )

inlinestatic

Definition at line 574 of file base.hh.

◆ numSimulatedInsts() [1/2]

static int BaseCPU::numSimulatedInsts ( )

inlinestatic

Definition at line 46 of file cpu_dummy.hh.

Referenced by Stats::Global::Global(), and ElasticTrace::regEtraceListeners().

◆ numSimulatedInsts() [2/2]

static Counter BaseCPU::numSimulatedInsts ( )

inlinestatic

Definition at line 575 of file base.hh.

References ArmISA::i, and Stats::total.

◆ numSimulatedOps() [1/2]

static int BaseCPU::numSimulatedOps ( )

inlinestatic

Definition at line 47 of file cpu_dummy.hh.

Referenced by Stats::Global::Global().

◆ numSimulatedOps() [2/2]

static Counter BaseCPU::numSimulatedOps ( )

inlinestatic

Definition at line 586 of file base.hh.

References ArmISA::i, and Stats::total.

◆ params()

const Params* BaseCPU::params ( ) const

inline

◆ pmuProbePoint()

ProbePoints::PMUUPtr BaseCPU::pmuProbePoint ( const char * name )

protected

Helper method to instantiate probe points belonging to this object.

Parameters

name	Name of the probe point.

Returns: A unique_ptr to the new probe point.

Definition at line 341 of file base.cc.

References SimObject::getProbeManager().

Referenced by regProbePoints().

◆ postInterrupt()

void BaseCPU::postInterrupt	(	ThreadID	tid,
		int	int_num,
		int	index
	)

inline

Definition at line 234 of file base.hh.

References FullSystem.

Referenced by SparcISA::ISA::checkSoftInt(), IntrControl::post(), ArmISA::sendEvent(), SparcISA::ISA::setFSReg(), and SparcISA::ISA::setMiscReg().

◆ probeInstCommit()

void BaseCPU::probeInstCommit	(	const StaticInstPtr &	inst,
		Addr	pc
	)

virtual

Helper method to trigger PMU probes for a committed instruction.

Parameters

inst	Instruction that just committed
pc	PC of the instruction that just committed

Definition at line 366 of file base.cc.

References StaticInst::isAtomic(), StaticInst::isControl(), StaticInst::isLastMicroop(), StaticInst::isLoad(), StaticInst::isMicroop(), StaticInst::isStore(), ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, and ppRetiredStores.

Referenced by Minor::Execute::doInstCommitAccounting(), FullO3CPU< O3CPUImpl >::instDone(), and BaseSimpleCPU::postExecute().

◆ processProfileEvent()

void BaseCPU::processProfileEvent ( )

Definition at line 668 of file base.cc.

References curTick(), ArmISA::i, params(), profileEvent, EventManager::schedule(), and threadContexts.

Referenced by BaseCPU().

◆ registerThreadContexts()

void BaseCPU::registerThreadContexts ( )

Definition at line 431 of file base.cc.

References _cpuId, Process::assignThreadContext(), ThreadContext::contextId(), FullSystem, ThreadContext::getProcessPtr(), System::multiThread, numThreads, System::registerThreadContext(), ThreadContext::setContextId(), system, and threadContexts.

Referenced by init().

◆ regProbePoints()

void BaseCPU::regProbePoints ( )

overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from SimObject.

Reimplemented in AtomicSimpleCPU, FullO3CPU< Impl >, and FullO3CPU< O3CPUImpl >.

Definition at line 350 of file base.cc.

References SimObject::getProbeManager(), pmuProbePoint(), ppActiveCycles, ppAllCycles, ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, ppRetiredStores, and ppSleeping.

Referenced by FullO3CPU< O3CPUImpl >::regProbePoints(), and AtomicSimpleCPU::regProbePoints().

◆ regStats()

void BaseCPU::regStats ( )

overridevirtual

Callback to set stat parameters.

This callback is typically used for complex stats (e.g., distributions) that need parameters in addition to a name and a description. Stat names and descriptions should typically be set from the constructor usingo from the constructor using the ADD_STAT macro.

Reimplemented from Stats::Group.

Reimplemented in TraceCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, MinorCPU, BaseSimpleCPU, BaseKvmCPU, and BaseO3CPU.

Definition at line 384 of file base.cc.

References ccprintf(), Stats::DataWrap< Derived, InfoProxyType >::desc(), ArmISA::i, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), numCycles, numWorkItemsCompleted, numWorkItemsStarted, Stats::Group::regStats(), and threadContexts.

Referenced by BaseO3CPU::regStats(), BaseKvmCPU::regStats(), BaseSimpleCPU::regStats(), MinorCPU::regStats(), and TraceCPU::regStats().

◆ scheduleInstStop()

void BaseCPU::scheduleInstStop	(	ThreadID	tid,
		Counter	insts,
		const char *	cause
	)

Schedule an event that exits the simulation loops after a predefined number of instructions.

This method is usually called from the configuration script to get an exit event some time in the future. It is typically used when the script wants to simulate for a specific number of instructions rather than ticks.

Parameters

tid	Thread monitor.
insts	Number of instructions into the future.
cause	Cause to signal in the exit event.

Definition at line 717 of file base.cc.

References MipsISA::event, getCurrentInstCount(), and threadContexts.

Referenced by init().

◆ schedulePowerGatingEvent()

void BaseCPU::schedulePowerGatingEvent ( )

Definition at line 459 of file base.cc.

References ThreadContext::Active, Clocked::clockEdge(), enterPwrGatingEvent, PowerState::get(), powerGatingOnIdle, ClockedObject::powerState, pwrGatingLatency, EventManager::schedule(), Event::scheduled(), and threadContexts.

Referenced by MinorCPU::drainResume(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), and FullO3CPU< O3CPUImpl >::drainResume().

◆ serialize()

void BaseCPU::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize this object to the given output stream.

Note: CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The stream to serialize to.

Implements Serializable.

Reimplemented in CheckerCPU, and MinorCPU.

Definition at line 679 of file base.cc.

References _pid, _switchedOut, csprintf(), ArmISA::i, instCnt, interrupts, numThreads, SERIALIZE_SCALAR, and serializeThread().

Referenced by MinorCPU::serialize(), and Iris::BaseCPU::serializeThread().

◆ serializeThread()

virtual void BaseCPU::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid
	)		const

inlinevirtual

Serialize a single thread.

Parameters

cp	The stream to serialize to.
tid	ID of the current thread.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, MinorCPU, Iris::BaseCPU, and BaseKvmCPU.

Definition at line 419 of file base.hh.

Referenced by FullO3CPU< O3CPUImpl >::isDraining(), and serialize().

◆ setPid()

void BaseCPU::setPid ( uint32_t pid )

inline

Definition at line 208 of file base.hh.

Referenced by ArmISA::DumpStats::process().

◆ socketId()

uint32_t BaseCPU::socketId ( ) const

inline

Reads this CPU's Socket ID.

Definition at line 182 of file base.hh.

Referenced by Iris::ThreadContext::socketId().

◆ startup()

void BaseCPU::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from SimObject.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, MinorCPU, BaseKvmCPU, and X86KvmCPU.

Definition at line 320 of file base.cc.

References _switchedOut, curTick(), FullSystem, PowerState::get(), RiscvISA::OFF, params(), ClockedObject::powerState, profileEvent, EventManager::schedule(), and PowerState::set().

Referenced by FullO3CPU< O3CPUImpl >::demapDataPage(), BaseKvmCPU::startup(), MinorCPU::startup(), BaseSimpleCPU::startup(), and FullO3CPU< O3CPUImpl >::startup().

◆ suspendContext()

void BaseCPU::suspendContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented in TimingSimpleCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, AtomicSimpleCPU, MinorCPU, and BaseKvmCPU.

Definition at line 501 of file base.cc.

References Clocked::clockEdge(), CPU_STATE_SLEEP, DPRINTF, enterPwrGatingEvent, powerGatingOnIdle, ClockedObject::powerState, pwrGatingLatency, EventManager::schedule(), PowerState::set(), ThreadContext::Suspended, ArmISA::t, threadContexts, and updateCycleCounters().

Referenced by BaseSimpleCPU::haltContext(), FullO3CPU< O3CPUImpl >::numActiveThreads(), SimpleThread::suspend(), MinorCPU::suspendContext(), AtomicSimpleCPU::suspendContext(), FullO3CPU< O3CPUImpl >::suspendContext(), and TimingSimpleCPU::suspendContext().

◆ switchedOut()

bool BaseCPU::switchedOut ( ) const

inline

Determine if the CPU is switched out.

Returns: True if the CPU is switched out, false otherwise.

Definition at line 363 of file base.hh.

◆ switchOut()

void BaseCPU::switchOut ( )

virtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented in Checker< Impl >, Checker< O3CPUImpl >, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, MinorCPU, and BaseKvmCPU.

Definition at line 539 of file base.cc.

References _switchedOut, EventManager::deschedule(), flushTLBs(), RiscvISA::OFF, ClockedObject::powerState, profileEvent, Event::scheduled(), and PowerState::set().

Referenced by Checker< O3CPUImpl >::Checker(), FullO3CPU< O3CPUImpl >::isDraining(), BaseKvmCPU::switchOut(), MinorCPU::switchOut(), AtomicSimpleCPU::switchOut(), TimingSimpleCPU::switchOut(), and FullO3CPU< O3CPUImpl >::switchOut().

◆ takeOverFrom()

void BaseCPU::takeOverFrom ( BaseCPU * cpu )

virtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented in Checker< Impl >, Checker< O3CPUImpl >, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, TraceCPU, AtomicSimpleCPU, MinorCPU, and BaseKvmCPU.

Definition at line 555 of file base.cc.

References _cpuId, _pid, _switchedOut, _taskId, ThreadContext::contextId(), cpuId(), curTick(), FullSystem, PowerState::get(), ThreadContext::getCheckerCpuPtr(), getDataPort(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), getInstPort(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), getPid(), BaseTLB::getTableWalkerPort(), ArmISA::i, interrupts, numThreads, ClockedObject::powerState, previousCycle, previousState, profileEvent, CpuEvent::replaceThreadContext(), System::replaceThreadContext(), EventManager::schedule(), PowerState::set(), system, BaseTLB::takeOverFrom(), Port::takeOverFrom(), ThreadContext::takeOverFrom(), taskId(), threadContexts, and ThreadContext::threadId().

Referenced by Checker< O3CPUImpl >::Checker(), FullO3CPU< O3CPUImpl >::isDraining(), BaseKvmCPU::takeOverFrom(), MinorCPU::takeOverFrom(), AtomicSimpleCPU::takeOverFrom(), TimingSimpleCPU::takeOverFrom(), and FullO3CPU< O3CPUImpl >::takeOverFrom().

◆ taskId() [1/2]

uint32_t BaseCPU::taskId ( ) const

inline

Get cpu task id.

Definition at line 203 of file base.hh.

Referenced by AtomicSimpleCPU::amoMem(), TimingSimpleCPU::fetch(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), ArmISA::DumpStats::process(), AtomicSimpleCPU::readMem(), takeOverFrom(), AtomicSimpleCPU::tick(), AtomicSimpleCPU::writeMem(), and TimingSimpleCPU::writeMem().

◆ taskId() [2/2]

void BaseCPU::taskId ( uint32_t id )

inline

Set cpu task id.

Definition at line 205 of file base.hh.

References ArmISA::id.

◆ totalInsts()

virtual Counter BaseCPU::totalInsts ( ) const

pure virtual

Implemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, CheckerCPU, TraceCPU, MinorCPU, BaseKvmCPU, and Iris::BaseCPU.

Referenced by FullO3CPU< O3CPUImpl >::numActiveThreads(), and RiscvISA::ISA::readMiscReg().

◆ totalOps()

virtual Counter BaseCPU::totalOps ( ) const

pure virtual

Implemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, TraceCPU, CheckerCPU, MinorCPU, BaseKvmCPU, and Iris::BaseCPU.

Referenced by FullO3CPU< O3CPUImpl >::numActiveThreads(), and CPUProgressEvent::process().

◆ traceFunctions()

void BaseCPU::traceFunctions ( Addr pc )

inline

Definition at line 568 of file base.hh.

Referenced by BaseSimpleCPU::postExecute().

◆ traceFunctionsInternal()

void BaseCPU::traceFunctionsInternal ( Addr pc )

private

Definition at line 752 of file base.cc.

References ccprintf(), csprintf(), currentFunctionEnd, currentFunctionStart, curTick(), Loader::debugSymbolTable, Loader::SymbolTable::findNearestSymbol(), functionEntryTick, functionTraceStream, and MipsISA::pc.

◆ unserialize()

void BaseCPU::unserialize ( CheckpointIn & cp )

overridevirtual

Reconstruct the state of this object from a checkpoint.

Note: CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The checkpoint use.

Implements Serializable.

Reimplemented in CheckerCPU, and MinorCPU.

Definition at line 700 of file base.cc.

References _pid, _switchedOut, csprintf(), ArmISA::i, instCnt, interrupts, numThreads, UNSERIALIZE_SCALAR, and unserializeThread().

Referenced by MinorCPU::unserialize().

◆ unserializeThread()

virtual void BaseCPU::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid
	)

inlinevirtual

Unserialize one thread.

Parameters

cp	The checkpoint use.
tid	ID of the current thread.

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, BaseSimpleCPU, MinorCPU, and BaseKvmCPU.

Definition at line 427 of file base.hh.

References name(), and MipsISA::pc.

Referenced by FullO3CPU< O3CPUImpl >::isDraining(), and unserialize().

◆ updateCycleCounters()

void BaseCPU::updateCycleCounters ( CPUState state )

inlineprotected

base method keeping track of cycle progression

Definition at line 528 of file base.hh.

References ProbePointArg< Arg >::notify().

Referenced by activateContext(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), TimingSimpleCPU::fetch(), BaseKvmCPU::haltContext(), BaseSimpleCPU::haltContext(), FullO3CPU< O3CPUImpl >::haltContext(), haltContext(), TimingSimpleCPU::sendFetch(), suspendContext(), TimingSimpleCPU::switchOut(), AtomicSimpleCPU::tick(), FullO3CPU< O3CPUImpl >::tick(), and TimingSimpleCPU::translationFault().

◆ verifyMemoryMode()

virtual void BaseCPU::verifyMemoryMode ( ) const

inlinevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, TimingSimpleCPU, AtomicSimpleCPU, BaseKvmCPU, and NonCachingSimpleCPU.

Definition at line 374 of file base.hh.

Referenced by init(), and FullO3CPU< O3CPUImpl >::isDraining().

◆ waitForRemoteGDB()

bool BaseCPU::waitForRemoteGDB ( ) const

Definition at line 778 of file base.cc.

References params().

◆ wakeup() [1/2]

static void BaseCPU::wakeup ( ThreadID tid )

inlinestatic

Definition at line 48 of file cpu_dummy.hh.

Referenced by FullO3CPU< O3CPUImpl >::deactivateStage(), and GenericTimer::CoreTimers::eventStreamCallback().

◆ wakeup() [2/2]

virtual void BaseCPU::wakeup ( ThreadID tid )

pure virtual

Implemented in FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, CheckerCPU, TraceCPU, MinorCPU, BaseKvmCPU, BaseSimpleCPU, and Iris::BaseCPU.

◆ workItemBegin()

void BaseCPU::workItemBegin ( )

inline

Definition at line 210 of file base.hh.

Referenced by PseudoInst::workbegin().

◆ workItemEnd()

void BaseCPU::workItemEnd ( )

inline

Definition at line 211 of file base.hh.

Referenced by PseudoInst::workend().

Member Data Documentation

◆ _cacheLineSize

const unsigned int BaseCPU::_cacheLineSize

protected

Cache the cache line size that we get from the system.

Definition at line 147 of file base.hh.

◆ _cpuId

int BaseCPU::_cpuId

protected

Definition at line 117 of file base.hh.

Referenced by BaseCPU(), registerThreadContexts(), and takeOverFrom().

◆ _dataMasterId

MasterID BaseCPU::_dataMasterId

protected

data side request id that must be placed in all requests

Definition at line 130 of file base.hh.

◆ _instMasterId

MasterID BaseCPU::_instMasterId

protected

instruction side request id that must be placed in all requests

Definition at line 127 of file base.hh.

◆ _pid

uint32_t BaseCPU::_pid

protected

The current OS process ID that is executing on this processor.

This is used to generate a taskId

Definition at line 141 of file base.hh.

Referenced by serialize(), takeOverFrom(), and unserialize().

◆ _socketId

const uint32_t BaseCPU::_socketId

protected

Each cpu will have a socket ID that corresponds to its physical location in the system.

This is usually used to bucket cpu cores under single DVFS domain. This information may also be required by the OS to identify the cpu core grouping (as in the case of ARM via MPIDR register)

Definition at line 124 of file base.hh.

Referenced by BaseCPU().

◆ _switchedOut

bool BaseCPU::_switchedOut

protected

Is the CPU switched out or active?

Definition at line 144 of file base.hh.

Referenced by serialize(), startup(), switchOut(), takeOverFrom(), and unserialize().

◆ _taskId

uint32_t BaseCPU::_taskId

protected

An intrenal representation of a task identifier within gem5.

This is used so the CPU can add which taskId (which is an internal representation of the OS process ID) to each request so components in the memory system can track which process IDs are ultimately interacting with them

Definition at line 137 of file base.hh.

Referenced by takeOverFrom().

◆ addressMonitor

std::vector<AddressMonitor> BaseCPU::addressMonitor

private

Definition at line 604 of file base.hh.

Referenced by armMonitor(), mwait(), and mwaitAtomic().

◆ cpuList

vector< BaseCPU * > BaseCPU::cpuList

staticprivate

Static global cpu list.

Definition at line 565 of file base.hh.

Referenced by BaseCPU().

◆ currentFunctionEnd

Addr BaseCPU::currentFunctionEnd

private

Definition at line 559 of file base.hh.

Referenced by BaseCPU(), and traceFunctionsInternal().

◆ currentFunctionStart

Addr BaseCPU::currentFunctionStart

private

Definition at line 558 of file base.hh.

Referenced by BaseCPU(), and traceFunctionsInternal().

◆ enterPwrGatingEvent

EventFunctionWrapper BaseCPU::enterPwrGatingEvent

protected

Definition at line 626 of file base.hh.

Referenced by activateContext(), deschedulePowerGatingEvent(), schedulePowerGatingEvent(), and suspendContext().

◆ functionEntryTick

Tick BaseCPU::functionEntryTick

private

Definition at line 560 of file base.hh.

Referenced by BaseCPU(), and traceFunctionsInternal().

◆ functionTraceStream

std::ostream* BaseCPU::functionTraceStream

private

Definition at line 557 of file base.hh.

Referenced by BaseCPU(), and traceFunctionsInternal().

◆ functionTracingEnabled

bool BaseCPU::functionTracingEnabled

private

Definition at line 556 of file base.hh.

Referenced by BaseCPU(), and enableFunctionTrace().

◆ instCnt

Tick BaseCPU::instCnt

protected

Instruction count used for SPARC misc register.

Todo:: unify this with the counters that cpus individually keep

Definition at line 111 of file base.hh.

Referenced by TimingSimpleCPU::completeIfetch(), serialize(), AtomicSimpleCPU::tick(), and unserialize().

◆ interrupts

std::vector<BaseInterrupts*> BaseCPU::interrupts

protected

Definition at line 218 of file base.hh.

Referenced by BaseCPU(), BaseSimpleCPU::checkForInterrupts(), X86KvmCPU::deliverInterrupts(), FullO3CPU< O3CPUImpl >::FullO3CPU(), FullO3CPU< O3CPUImpl >::getInterrupts(), BaseArmKvmCPU::kvmRun(), X86KvmCPU::kvmRun(), ArmKvmCPU::kvmRun(), FullO3CPU< O3CPUImpl >::processInterrupts(), serialize(), takeOverFrom(), and unserialize().

◆ invldPid

const uint32_t BaseCPU::invldPid = std::numeric_limits<uint32_t>::max()

static

Invalid or unknown Pid.

Possible when operating system is not present or has not assigned a pid yet

Definition at line 272 of file base.hh.

Referenced by ArmISA::FsLinux::startup().

◆ microcodeRom

TheISA::MicrocodeRom BaseCPU::microcodeRom

Definition at line 215 of file base.hh.

Referenced by BaseSimpleCPU::preExecute().

◆ numCycles

Stats::Scalar BaseCPU::numCycles

Definition at line 599 of file base.hh.

Referenced by BaseKvmCPU::activateContext(), AtomicSimpleCPU::activateContext(), BaseKvmCPU::kvmRun(), Minor::MinorStats::regStats(), BaseSimpleCPU::regStats(), FullO3CPU< O3CPUImpl >::regStats(), regStats(), TraceCPU::regStats(), TraceCPU::schedDcacheNext(), AtomicSimpleCPU::tick(), FullO3CPU< O3CPUImpl >::tick(), TimingSimpleCPU::updateCycleCounts(), and FullO3CPU< O3CPUImpl >::wakeCPU().

◆ numThreads

ThreadID BaseCPU::numThreads

Number of threads we're actually simulating (<= SMT_MAX_THREADS).

This is a constant for the duration of the simulation.

Definition at line 374 of file base.hh.

Referenced by AtomicSimpleCPU::activateContext(), TimingSimpleCPU::activateContext(), armMonitor(), BaseCPU(), BaseSimpleCPU::BaseSimpleCPU(), Minor::Execute::checkInterrupts(), Minor::Execute::drain(), Minor::Pipeline::drainResume(), MinorCPU::drainResume(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), Minor::Execute::drainResume(), ElasticTrace::ElasticTrace(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Fetch1::evaluate(), FullO3CPU< O3CPUImpl >::FullO3CPU(), FullO3CPU< O3CPUImpl >::getFreeTid(), BaseKvmCPU::init(), FullO3CPU< O3CPUImpl >::init(), init(), Minor::Execute::isDrained(), Minor::Fetch1::isDrained(), MinorCPU::MinorCPU(), mwait(), mwaitAtomic(), Minor::LSQ::recvTimingSnoopReq(), registerThreadContexts(), Minor::MinorStats::regStats(), BaseSimpleCPU::regStats(), FullO3CPU< O3CPUImpl >::regStats(), NonCachingSimpleCPU::sendPacket(), serialize(), MinorCPU::startup(), FullO3CPU< O3CPUImpl >::startup(), AtomicSimpleCPU::suspendContext(), TimingSimpleCPU::suspendContext(), BaseSimpleCPU::swapActiveThread(), takeOverFrom(), TimingSimpleCPU::threadSnoop(), AtomicSimpleCPU::threadSnoop(), Minor::LSQ::threadSnoop(), AtomicSimpleCPU::tick(), unserialize(), MinorCPU::wakeup(), and Minor::Execute::~Execute().

◆ numWorkItemsCompleted

Stats::Scalar BaseCPU::numWorkItemsCompleted

Definition at line 601 of file base.hh.

Referenced by regStats().

◆ numWorkItemsStarted

Stats::Scalar BaseCPU::numWorkItemsStarted

Definition at line 600 of file base.hh.

Referenced by regStats().

◆ PCMask

const Addr BaseCPU::PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

static

Definition at line 275 of file base.hh.

Referenced by Minor::Fetch2::evaluate(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::pipelineIcacheAccesses(), BaseSimpleCPU::preExecute(), and BaseSimpleCPU::setupFetchRequest().

◆ powerGatingOnIdle

const bool BaseCPU::powerGatingOnIdle

protected

Definition at line 625 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ ppActiveCycles

ProbePoints::PMUUPtr BaseCPU::ppActiveCycles

protected

CPU cycle counter, only counts if any thread contexts is active.

Definition at line 505 of file base.hh.

Referenced by regProbePoints().

◆ ppAllCycles

ProbePoints::PMUUPtr BaseCPU::ppAllCycles

protected

CPU cycle counter even if any thread Context is suspended.

Definition at line 502 of file base.hh.

Referenced by regProbePoints().

◆ ppRetiredBranches

ProbePoints::PMUUPtr BaseCPU::ppRetiredBranches

protected

Retired branches (any type)

Definition at line 499 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInsts

ProbePoints::PMUUPtr BaseCPU::ppRetiredInsts

protected

Instruction commit probe point.

This probe point is triggered whenever one or more instructions are committed. It is normally triggered once for every instruction. However, CPU models committing bundles of instructions may call notify once for the entire bundle.

Definition at line 490 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInstsPC

ProbePoints::PMUUPtr BaseCPU::ppRetiredInstsPC

protected

Definition at line 491 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredLoads

ProbePoints::PMUUPtr BaseCPU::ppRetiredLoads

protected

Retired load instructions.

Definition at line 494 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredStores

ProbePoints::PMUUPtr BaseCPU::ppRetiredStores

protected

Retired store instructions.

Definition at line 496 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppSleeping

ProbePointArg<bool>* BaseCPU::ppSleeping

protected

ProbePoint that signals transitions of threadContexts sets.

The ProbePoint reports information through it bool parameter.

If the parameter is true then the last enabled threadContext of the CPU object was disabled.
If the parameter is false then a threadContext was enabled, all the remaining threadContexts are disabled.

Definition at line 515 of file base.hh.

Referenced by regProbePoints().

◆ previousCycle

Cycles BaseCPU::previousCycle

protected

Definition at line 524 of file base.hh.

Referenced by takeOverFrom().

◆ previousState

CPUState BaseCPU::previousState

protected

Definition at line 525 of file base.hh.

Referenced by takeOverFrom().

◆ profileEvent

EventFunctionWrapper* BaseCPU::profileEvent

Definition at line 260 of file base.hh.

Referenced by BaseCPU(), processProfileEvent(), startup(), switchOut(), takeOverFrom(), and ~BaseCPU().

◆ pwrGatingLatency

const Cycles BaseCPU::pwrGatingLatency

protected

Definition at line 624 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ syscallRetryLatency

Cycles BaseCPU::syscallRetryLatency

Definition at line 618 of file base.hh.

Referenced by TimingSimpleCPU::advanceInst(), and AtomicSimpleCPU::tick().

◆ system

◆ threadContexts

std::vector<ThreadContext *> BaseCPU::threadContexts

protected

Definition at line 263 of file base.hh.

Referenced by activateContext(), BaseSimpleCPU::advancePC(), BaseKvmCPU::BaseKvmCPU(), BaseSimpleCPU::BaseSimpleCPU(), BaseSimpleCPU::checkPcEventQueue(), FastModel::CortexA76::clockPeriodUpdated(), Iris::CPU< CortexA76TC >::CPU(), FullO3CPU< O3CPUImpl >::drain(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), findContext(), flushTLBs(), FullO3CPU< O3CPUImpl >::FullO3CPU(), getCurrentInstCount(), FullO3CPU< O3CPUImpl >::getInterrupts(), BaseSimpleCPU::init(), Iris::BaseCPU::init(), init(), FastModel::CortexA76::initState(), MinorCPU::MinorCPU(), BaseSimpleCPU::postExecute(), FullO3CPU< O3CPUImpl >::processInterrupts(), processProfileEvent(), registerThreadContexts(), regStats(), scheduleInstStop(), schedulePowerGatingEvent(), Iris::BaseCPU::serializeThread(), CheckerCPU::setSystem(), FullO3CPU< O3CPUImpl >::startup(), suspendContext(), BaseKvmCPU::takeOverFrom(), takeOverFrom(), AtomicSimpleCPU::tick(), Iris::BaseCPU::totalInsts(), FullO3CPU< O3CPUImpl >::trap(), Iris::BaseCPU::wakeup(), FullO3CPU< O3CPUImpl >::wakeup(), and Iris::BaseCPU::~BaseCPU().

◆ tracer

Trace::InstTracer* BaseCPU::tracer

protected

Definition at line 265 of file base.hh.

Referenced by BaseCPU(), and BaseSimpleCPU::preExecute().

The documentation for this class was generated from the following files:

arch/null/cpu_dummy.hh
cpu/base.hh
cpu/base.cc

Public Types

Public Member Functions

Static Public Member Functions

Public Attributes

Static Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Private Member Functions

Private Attributes

Static Private Attributes

PMU Probe points.

Detailed Description

Member Typedef Documentation

◆ Params

Member Enumeration Documentation

◆ CPUState

Constructor & Destructor Documentation

◆ BaseCPU()

◆ ~BaseCPU()

Member Function Documentation

◆ activateContext()

◆ armMonitor()

◆ cacheLineSize()

◆ checkInterrupts()

◆ clearInterrupt()

◆ clearInterrupts()

◆ contextToThread()

◆ cpuId()

◆ dataMasterId()

◆ deschedulePowerGatingEvent()

◆ enableFunctionTrace()

◆ enterPwrGating()

◆ findContext()

◆ flushTLBs()

◆ getContext()

◆ getCpuAddrMonitor()

◆ getCurrentInstCount()

◆ getDataPort()

◆ getInstPort()

◆ getInterruptController()

◆ getPid()

◆ getPort()

◆ getSendFunctional()

◆ getTracer()

◆ haltContext()

◆ init()

◆ instCount()

◆ instMasterId()

◆ mwait()

◆ mwaitAtomic()

◆ numContexts()

◆ numSimulatedCPUs()

◆ numSimulatedInsts() [1/2]

◆ numSimulatedInsts() [2/2]

◆ numSimulatedOps() [1/2]

◆ numSimulatedOps() [2/2]

◆ params()

◆ pmuProbePoint()

◆ postInterrupt()

◆ probeInstCommit()

◆ processProfileEvent()

◆ registerThreadContexts()

◆ regProbePoints()

◆ regStats()

◆ scheduleInstStop()

◆ schedulePowerGatingEvent()

◆ serialize()

◆ serializeThread()

◆ setPid()

◆ socketId()

◆ startup()

◆ suspendContext()

◆ switchedOut()

◆ switchOut()

◆ takeOverFrom()

◆ taskId() [1/2]

◆ taskId() [2/2]

◆ totalInsts()

◆ totalOps()