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decode.hh
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37 
45 #ifndef __CPU_MINOR_DECODE_HH__
46 #define __CPU_MINOR_DECODE_HH__
47 
48 #include "cpu/minor/buffers.hh"
49 #include "cpu/minor/cpu.hh"
50 #include "cpu/minor/dyn_inst.hh"
51 #include "cpu/minor/pipe_data.hh"
52 
53 namespace Minor
54 {
55 
56 /* Decode takes instructions from Fetch2 and decomposes them into micro-ops
57  * to feed to Execute. It generates a new sequence number for each
58  * instruction: execSeqNum.
59  */
60 class Decode : public Named
61 {
62  protected:
65 
70 
73 
75  unsigned int outputWidth;
76 
80 
81  public:
82  /* Public for Pipeline to be able to pass it to Fetch2 */
84 
85  protected:
89 
92  inputIndex(0),
93  inMacroop(false),
94  execSeqNum(InstId::firstExecSeqNum),
95  blocked(false)
96  { }
97 
99  inputIndex(other.inputIndex),
100  inMacroop(other.inMacroop),
101  execSeqNum(other.execSeqNum),
102  blocked(other.blocked)
103  { }
104 
105 
108  unsigned int inputIndex;
109 
115  bool inMacroop;
117 
120 
122  bool blocked;
123  };
124 
127 
128  protected:
130  const ForwardInstData *getInput(ThreadID tid);
131 
133  void popInput(ThreadID tid);
134 
138  public:
139  Decode(const std::string &name,
140  MinorCPU &cpu_,
141  MinorCPUParams &params,
144  std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
145 
146  public:
148  void evaluate();
149 
150  void minorTrace() const;
151 
156  bool isDrained();
157 };
158 
159 }
160 
161 #endif /* __CPU_MINOR_DECODE_HH__ */
Data members after this line are cycle-to-cycle state.
Definition: decode.hh:88
bool blocked
Blocked indication for report.
Definition: decode.hh:122
Decode(const std::string &name, MinorCPU &cpu_, MinorCPUParams &params, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
Definition: decode.cc:46
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: decode.hh:72
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
Definition: decode.hh:69
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty...
Definition: buffers.hh:565
unsigned int inputIndex
Index into the inputBuffer&#39;s head marking the start of unhandled instructions.
Definition: decode.hh:108
Id for lines and instructions.
Definition: dyn_inst.hh:68
TheISA::PCState microopPC
Definition: decode.hh:116
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
Definition: activity.cc:44
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Definition: decode.hh:83
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: decode.hh:64
bool isDrained()
Is this stage drained? For Decoed, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
Definition: decode.cc:325
std::vector< DecodeThreadInfo > decodeInfo
Definition: decode.hh:125
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
Definition: decode.hh:119
void minorTrace() const
Definition: decode.cc:336
STL vector class.
Definition: stl.hh:37
DecodeThreadInfo()
Default Constructor.
Definition: decode.hh:91
Definition: trace.hh:147
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
Definition: decode.hh:67
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
Definition: decode.cc:295
uint64_t InstSeqNum
Definition: inst_seq.hh:37
Classes for buffer, queue and FIFO behaviour.
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Definition: decode.hh:79
const std::string & name() const
Definition: trace.hh:156
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:225
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: decode.cc:122
ThreadID threadPriority
Definition: decode.hh:126
DecodeThreadInfo(const DecodeThreadInfo &other)
Definition: decode.hh:98
Top level definition of the Minor in-order CPU model.
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
Definition: decode.cc:80
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:77
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:245
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
bool inMacroop
True when we&#39;re in the process of decomposing a micro-op and microopPC will be valid.
Definition: decode.hh:115
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition: pipe_data.hh:253
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: decode.cc:93
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Definition: decode.hh:75

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