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msr.cc
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28 
29 #include "arch/x86/regs/msr.hh"
30 
31 namespace X86ISA
32 {
33 
34 typedef MsrMap::value_type MsrVal;
35 
36 const MsrMap::value_type msrMapData[] = {
37  MsrVal(0x10, MISCREG_TSC),
38  MsrVal(0x1B, MISCREG_APIC_BASE),
39  MsrVal(0xFE, MISCREG_MTRRCAP),
40  MsrVal(0x174, MISCREG_SYSENTER_CS),
41  MsrVal(0x175, MISCREG_SYSENTER_ESP),
42  MsrVal(0x176, MISCREG_SYSENTER_EIP),
43  MsrVal(0x179, MISCREG_MCG_CAP),
44  MsrVal(0x17A, MISCREG_MCG_STATUS),
45  MsrVal(0x17B, MISCREG_MCG_CTL),
46  MsrVal(0x1D9, MISCREG_DEBUG_CTL_MSR),
47  MsrVal(0x1DB, MISCREG_LAST_BRANCH_FROM_IP),
48  MsrVal(0x1DC, MISCREG_LAST_BRANCH_TO_IP),
49  MsrVal(0x1DD, MISCREG_LAST_EXCEPTION_FROM_IP),
50  MsrVal(0x1DE, MISCREG_LAST_EXCEPTION_TO_IP),
51  MsrVal(0x200, MISCREG_MTRR_PHYS_BASE_0),
52  MsrVal(0x201, MISCREG_MTRR_PHYS_MASK_0),
53  MsrVal(0x202, MISCREG_MTRR_PHYS_BASE_1),
54  MsrVal(0x203, MISCREG_MTRR_PHYS_MASK_1),
55  MsrVal(0x204, MISCREG_MTRR_PHYS_BASE_2),
56  MsrVal(0x205, MISCREG_MTRR_PHYS_MASK_2),
57  MsrVal(0x206, MISCREG_MTRR_PHYS_BASE_3),
58  MsrVal(0x207, MISCREG_MTRR_PHYS_MASK_3),
59  MsrVal(0x208, MISCREG_MTRR_PHYS_BASE_4),
60  MsrVal(0x209, MISCREG_MTRR_PHYS_MASK_4),
61  MsrVal(0x20A, MISCREG_MTRR_PHYS_BASE_5),
62  MsrVal(0x20B, MISCREG_MTRR_PHYS_MASK_5),
63  MsrVal(0x20C, MISCREG_MTRR_PHYS_BASE_6),
64  MsrVal(0x20D, MISCREG_MTRR_PHYS_MASK_6),
65  MsrVal(0x20E, MISCREG_MTRR_PHYS_BASE_7),
66  MsrVal(0x20F, MISCREG_MTRR_PHYS_MASK_7),
67  MsrVal(0x250, MISCREG_MTRR_FIX_64K_00000),
68  MsrVal(0x258, MISCREG_MTRR_FIX_16K_80000),
69  MsrVal(0x259, MISCREG_MTRR_FIX_16K_A0000),
70  MsrVal(0x268, MISCREG_MTRR_FIX_4K_C0000),
71  MsrVal(0x269, MISCREG_MTRR_FIX_4K_C8000),
72  MsrVal(0x26A, MISCREG_MTRR_FIX_4K_D0000),
73  MsrVal(0x26B, MISCREG_MTRR_FIX_4K_D8000),
74  MsrVal(0x26C, MISCREG_MTRR_FIX_4K_E0000),
75  MsrVal(0x26D, MISCREG_MTRR_FIX_4K_E8000),
76  MsrVal(0x26E, MISCREG_MTRR_FIX_4K_F0000),
77  MsrVal(0x26F, MISCREG_MTRR_FIX_4K_F8000),
78  MsrVal(0x277, MISCREG_PAT),
79  MsrVal(0x2FF, MISCREG_DEF_TYPE),
80  MsrVal(0x400, MISCREG_MC0_CTL),
81  MsrVal(0x404, MISCREG_MC1_CTL),
82  MsrVal(0x408, MISCREG_MC2_CTL),
83  MsrVal(0x40C, MISCREG_MC3_CTL),
84  MsrVal(0x410, MISCREG_MC4_CTL),
85  MsrVal(0x414, MISCREG_MC5_CTL),
86  MsrVal(0x418, MISCREG_MC6_CTL),
87  MsrVal(0x41C, MISCREG_MC7_CTL),
88  MsrVal(0x401, MISCREG_MC0_STATUS),
89  MsrVal(0x405, MISCREG_MC1_STATUS),
90  MsrVal(0x409, MISCREG_MC2_STATUS),
91  MsrVal(0x40D, MISCREG_MC3_STATUS),
92  MsrVal(0x411, MISCREG_MC4_STATUS),
93  MsrVal(0x415, MISCREG_MC5_STATUS),
94  MsrVal(0x419, MISCREG_MC6_STATUS),
95  MsrVal(0x41D, MISCREG_MC7_STATUS),
96  MsrVal(0x402, MISCREG_MC0_ADDR),
97  MsrVal(0x406, MISCREG_MC1_ADDR),
98  MsrVal(0x40A, MISCREG_MC2_ADDR),
99  MsrVal(0x40E, MISCREG_MC3_ADDR),
100  MsrVal(0x412, MISCREG_MC4_ADDR),
101  MsrVal(0x416, MISCREG_MC5_ADDR),
102  MsrVal(0x41A, MISCREG_MC6_ADDR),
103  MsrVal(0x41E, MISCREG_MC7_ADDR),
104  MsrVal(0x403, MISCREG_MC0_MISC),
105  MsrVal(0x407, MISCREG_MC1_MISC),
106  MsrVal(0x40B, MISCREG_MC2_MISC),
107  MsrVal(0x40F, MISCREG_MC3_MISC),
108  MsrVal(0x413, MISCREG_MC4_MISC),
109  MsrVal(0x417, MISCREG_MC5_MISC),
110  MsrVal(0x41B, MISCREG_MC6_MISC),
111  MsrVal(0x41F, MISCREG_MC7_MISC),
112  MsrVal(0xC0000080, MISCREG_EFER),
113  MsrVal(0xC0000081, MISCREG_STAR),
114  MsrVal(0xC0000082, MISCREG_LSTAR),
115  MsrVal(0xC0000083, MISCREG_CSTAR),
116  MsrVal(0xC0000084, MISCREG_SF_MASK),
117  MsrVal(0xC0000100, MISCREG_FS_BASE),
118  MsrVal(0xC0000101, MISCREG_GS_BASE),
119  MsrVal(0xC0000102, MISCREG_KERNEL_GS_BASE),
120  MsrVal(0xC0000103, MISCREG_TSC_AUX),
121  MsrVal(0xC0010000, MISCREG_PERF_EVT_SEL0),
122  MsrVal(0xC0010001, MISCREG_PERF_EVT_SEL1),
123  MsrVal(0xC0010002, MISCREG_PERF_EVT_SEL2),
124  MsrVal(0xC0010003, MISCREG_PERF_EVT_SEL3),
125  MsrVal(0xC0010004, MISCREG_PERF_EVT_CTR0),
126  MsrVal(0xC0010005, MISCREG_PERF_EVT_CTR1),
127  MsrVal(0xC0010006, MISCREG_PERF_EVT_CTR2),
128  MsrVal(0xC0010007, MISCREG_PERF_EVT_CTR3),
129  MsrVal(0xC0010010, MISCREG_SYSCFG),
130  MsrVal(0xC0010016, MISCREG_IORR_BASE0),
131  MsrVal(0xC0010017, MISCREG_IORR_BASE1),
132  MsrVal(0xC0010018, MISCREG_IORR_MASK0),
133  MsrVal(0xC0010019, MISCREG_IORR_MASK1),
134  MsrVal(0xC001001A, MISCREG_TOP_MEM),
135  MsrVal(0xC001001D, MISCREG_TOP_MEM2),
136  MsrVal(0xC0010114, MISCREG_VM_CR),
137  MsrVal(0xC0010115, MISCREG_IGNNE),
138  MsrVal(0xC0010116, MISCREG_SMM_CTL),
139  MsrVal(0xC0010117, MISCREG_VM_HSAVE_PA)
140 };
141 
142 static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
143 
144 const MsrMap msrMap(msrMapData, msrMapData + msrMapSize);
145 
146 bool
147 msrAddrToIndex(MiscRegIndex &regNum, Addr addr)
148 {
149  MsrMap::const_iterator it(msrMap.find(addr));
150  if (it == msrMap.end()) {
151  return false;
152  } else {
153  regNum = it->second;
154  return true;
155  }
156 }
157 
158 } // namespace X86ISA
X86ISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:100
X86ISA::msrMapSize
static const unsigned msrMapSize
Definition: msr.cc:142
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
X86ISA::msrAddrToIndex
bool msrAddrToIndex(MiscRegIndex &regNum, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition: msr.cc:147
X86ISA::msrMap
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
X86ISA::MsrVal
MsrMap::value_type MsrVal
Definition: msr.cc:34
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86ISA::msrMapData
const MsrMap::value_type msrMapData[]
Definition: msr.cc:36
X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:79
X86ISA::MsrMap
std::unordered_map< Addr, MiscRegIndex > MsrMap
Definition: msr.hh:40
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