isa_traits.hh

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/*
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 * Copyright (c) 2007-2008 The Florida State University
 * Copyright (c) 2009 The University of Edinburgh
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#ifndef __ARCH_POWER_ISA_TRAITS_HH__
#define __ARCH_POWER_ISA_TRAITS_HH__

#include "arch/power/types.hh"
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"

namespace PowerISA
{

const ByteOrder GuestByteOrder = BigEndianByteOrder;

StaticInstPtr decodeInst(ExtMachInst);

const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;

const Addr PteShift = 3;
const Addr NPtePageShift = PageShift - PteShift;
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;

const int MachineBytes = 4;

// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;

const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;

} // namespace PowerISA

#endif // __ARCH_POWER_ISA_TRAITS_HH__