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isa_traits.hh
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41 
42 #ifndef __ARCH_RISCV_ISA_TRAITS_HH__
43 #define __ARCH_RISCV_ISA_TRAITS_HH__
44 
45 #include "arch/riscv/types.hh"
46 #include "base/types.hh"
47 #include "cpu/static_inst_fwd.hh"
48 
49 namespace RiscvISA
50 {
51 
52 const ByteOrder GuestByteOrder = LittleEndianByteOrder;
53 
54 const Addr PageShift = 12;
55 const Addr PageBytes = ULL(1) << PageShift;
56 
57 // Memory accesses can be unaligned (at least for double-word memory accesses)
58 const bool HasUnalignedMemAcc = true;
59 
60 const bool CurThreadInfoImplemented = false;
61 const int CurThreadInfoReg = -1;
62 
63 }
64 
65 #endif //__ARCH_RISCV_ISA_TRAITS_HH__
static_inst_fwd.hh
RiscvISA::CurThreadInfoImplemented
const bool CurThreadInfoImplemented
Definition: isa_traits.hh:60
RiscvISA::HasUnalignedMemAcc
const bool HasUnalignedMemAcc
Definition: isa_traits.hh:58
ByteOrder
ByteOrder
Definition: types.hh:245
RiscvISA::PageShift
const Addr PageShift
Definition: isa_traits.hh:54
RiscvISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:55
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:48
RiscvISA::CurThreadInfoReg
const int CurThreadInfoReg
Definition: isa_traits.hh:61
RiscvISA::GuestByteOrder
const ByteOrder GuestByteOrder
Definition: isa_traits.hh:52
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