system.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2012, 2014, 2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __SYSTEM_HH__
#define __SYSTEM_HH__

#include <string>
#include <unordered_map>
#include <utility>
#include <vector>

#include "arch/isa_traits.hh"
#include "base/loader/memory_image.hh"
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_master.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "params/System.hh"
#include "sim/futex_map.hh"
#include "sim/redirect_path.hh"
#include "sim/se_signal.hh"
#include "sim/sim_object.hh"
#include "sim/workload.hh"

class BaseRemoteGDB;
class KvmVM;
class ThreadContext;

class System : public SimObject, public PCEventScope
{
  private:

    class SystemPort : public MasterPort
    {
      public:

        SystemPort(const std::string &_name, SimObject *_owner)
            : MasterPort(_name, _owner)
        { }
        bool recvTimingResp(PacketPtr pkt) override
        { panic("SystemPort does not receive timing!\n"); return false; }
        void recvReqRetry() override
        { panic("SystemPort does not expect retry!\n"); }
    };

    std::list<PCEvent *> liveEvents;
    SystemPort _systemPort;

  public:

    void init() override;
    void startup() override;

    MasterPort& getSystemPort() { return _systemPort; }

    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;

    bool isAtomicMode() const {
        return memoryMode == Enums::atomic ||
            memoryMode == Enums::atomic_noncaching;
    }

    bool isTimingMode() const {
        return memoryMode == Enums::timing;
    }

    bool bypassCaches() const {
        return memoryMode == Enums::atomic_noncaching;
    }
    Enums::MemoryMode getMemoryMode() const { return memoryMode; }

    void setMemoryMode(Enums::MemoryMode mode);
    unsigned int cacheLineSize() const { return _cacheLineSize; }

    std::vector<ThreadContext *> threadContexts;
    ThreadContext *findFreeContext();

    ThreadContext *
    getThreadContext(ContextID tid) const
    {
        return threadContexts[tid];
    }

    const bool multiThread;

    using SimObject::schedule;

    bool schedule(PCEvent *event) override;
    bool remove(PCEvent *event) override;

    unsigned numContexts() const { return threadContexts.size(); }

    int numRunningContexts();

    Addr pagePtr;

    uint64_t init_param;

    PortProxy physProxy;

    Workload *workload = nullptr;

  public:
    KvmVM* getKvmVM() {
        return kvmVM;
    }

    bool validKvmEnvironment() const;

    PhysicalMemory& getPhysMem() { return physmem; }

    Addr freeMemSize() const;

    Addr memSize() const;

    bool isMemAddr(Addr addr) const;

    Arch getArch() const { return Arch::TheISA; }

    ByteOrder
    getGuestByteOrder() const
    {
#if THE_ISA != NULL_ISA
        return TheISA::GuestByteOrder;
#else
        panic("The NULL ISA has no endianness.");
#endif
    }

    Addr getPageBytes() const { return TheISA::PageBytes; }

    Addr getPageShift() const { return TheISA::PageShift; }

    ThermalModel * getThermalModel() const { return thermalModel; }

  protected:

    KvmVM *const kvmVM;

    PhysicalMemory physmem;

    Enums::MemoryMode memoryMode;

    const unsigned int _cacheLineSize;

    uint64_t workItemsBegin;
    uint64_t workItemsEnd;
    uint32_t numWorkIds;
    std::vector<bool> activeCpus;

    std::vector<MasterInfo> masters;

    ThermalModel * thermalModel;

  protected:
    std::string stripSystemName(const std::string& master_name) const;

  public:

    MasterID getMasterId(const SimObject* master,
                         std::string submaster = std::string());

    MasterID getGlobalMasterId(const std::string& master_name);

    std::string getMasterName(MasterID master_id);

    MasterID lookupMasterId(const SimObject* obj) const;

    MasterID lookupMasterId(const std::string& name) const;

    MasterID maxMasters() { return masters.size(); }

  protected:
    MasterID _getMasterId(const SimObject* master,
                          const std::string& master_name);

    std::string leafMasterName(const SimObject* master,
                               const std::string& submaster);

  public:

    void regStats() override;
    uint64_t
    incWorkItemsBegin()
    {
        return ++workItemsBegin;
    }

    uint64_t
    incWorkItemsEnd()
    {
        return ++workItemsEnd;
    }

    int
    markWorkItem(int index)
    {
        int count = 0;
        assert(index < activeCpus.size());
        activeCpus[index] = true;
        for (std::vector<bool>::iterator i = activeCpus.begin();
             i < activeCpus.end(); i++) {
            if (*i) count++;
        }
        return count;
    }

    inline void workItemBegin(uint32_t tid, uint32_t workid)
    {
        std::pair<uint32_t,uint32_t> p(tid, workid);
        lastWorkItemStarted[p] = curTick();
    }

    void workItemEnd(uint32_t tid, uint32_t workid);

  public:
    std::vector<BaseRemoteGDB *> remoteGDB;
    bool breakpoint();

  public:
    typedef SystemParams Params;

  protected:
    Params *_params;

    const AddrRange _m5opRange;

  public:
    System(Params *p);
    ~System();

    const Params *params() const { return (const Params *)_params; }

    const AddrRange &m5opRange() const { return _m5opRange; }

  public:

    Addr allocPhysPages(int npages);

    ContextID registerThreadContext(ThreadContext *tc,
                                    ContextID assigned = InvalidContextID);
    void replaceThreadContext(ThreadContext *tc, ContextID context_id);

    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

    void drainResume() override;

  public:
    Counter totalNumInsts;
    std::map<std::pair<uint32_t,uint32_t>, Tick>  lastWorkItemStarted;
    std::map<uint32_t, Stats::Histogram*> workItemStats;

    //
    // STATIC GLOBAL SYSTEM LIST
    //

    static std::vector<System *> systemList;
    static int numSystemsRunning;

    static void printSystems();

    FutexMap futexMap;

    static const int maxPID = 32768;

    std::set<int> PIDs;

    // By convention, all signals are owned by the receiving process. The
    // receiver will delete the signal upon reception.
    std::list<BasicSignal> signalList;

    // Used by syscall-emulation mode. This member contains paths which need
    // to be redirected to the faux-filesystem (a duplicate filesystem
    // intended to replace certain files on the host filesystem).
    std::vector<RedirectPath*> redirectPaths;
};

void printSystems();

#endif // __SYSTEM_HH__