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simple_mem.hh
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40 
46 #ifndef __MEM_SIMPLE_MEMORY_HH__
47 #define __MEM_SIMPLE_MEMORY_HH__
48 
49 #include <list>
50 
51 #include "mem/abstract_mem.hh"
52 #include "mem/port.hh"
53 #include "params/SimpleMemory.hh"
54 
62 {
63 
64  private:
65 
71  {
72 
73  public:
74 
75  const Tick tick;
76  const PacketPtr pkt;
77 
78  DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
79  { }
80  };
81 
82  class MemoryPort : public SlavePort
83  {
84  private:
86 
87  public:
88  MemoryPort(const std::string& _name, SimpleMemory& _memory);
89 
90  protected:
91  Tick recvAtomic(PacketPtr pkt) override;
93  PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
94  void recvFunctional(PacketPtr pkt) override;
95  bool recvTimingReq(PacketPtr pkt) override;
96  void recvRespRetry() override;
97  AddrRangeList getAddrRanges() const override;
98  };
99 
101 
106  const Tick latency;
107 
112 
119 
125  const double bandwidth;
126 
131  bool isBusy;
132 
137  bool retryReq;
138 
143  bool retryResp;
144 
149  void release();
150 
152 
157  void dequeue();
158 
160 
166  Tick getLatency() const;
167 
172  std::unique_ptr<Packet> pendingDelete;
173 
174  public:
175 
176  SimpleMemory(const SimpleMemoryParams *p);
177 
178  DrainState drain() override;
179 
180  Port &getPort(const std::string &if_name,
181  PortID idx=InvalidPortID) override;
182  void init() override;
183 
184  protected:
189  void recvRespRetry();
190 };
191 
192 #endif //__MEM_SIMPLE_MEMORY_HH__
Ports are used to interface objects to each other.
Definition: port.hh:56
bool isBusy
Track the state of the memory as either idle or busy, no need for an enum with only two states...
Definition: simple_mem.hh:131
const PortID InvalidPortID
Definition: types.hh:236
EventFunctionWrapper dequeueEvent
Definition: simple_mem.hh:159
MemoryPort port
Definition: simple_mem.hh:100
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: simple_mem.hh:172
A SlavePort is a specialisation of a port.
Definition: port.hh:254
DrainState
Object drain/handover states.
Definition: drain.hh:71
DeferredPacket(PacketPtr _pkt, Tick _tick)
Definition: simple_mem.hh:78
A deferred packet stores a packet along with its scheduled transmission time.
Definition: simple_mem.hh:70
const Tick latency_var
Fudge factor added to the latency.
Definition: simple_mem.hh:111
bool recvTimingReq(PacketPtr pkt)
Definition: simple_mem.cc:108
AbstractMemory declaration.
bool retryResp
Remember if we failed to send a response and are awaiting a retry.
Definition: simple_mem.hh:143
bool retryReq
Remember if we have to retry an outstanding request that arrived while we were busy.
Definition: simple_mem.hh:137
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: simple_mem.cc:58
The simple memory is a basic single-ported memory controller with a configurable throughput and laten...
Definition: simple_mem.hh:61
uint64_t Tick
Tick count type.
Definition: types.hh:61
SimpleMemory & memory
Definition: simple_mem.hh:85
const double bandwidth
Bandwidth in ticks per byte.
Definition: simple_mem.hh:125
void release()
Release the memory after being busy and send a retry if a request was rejected in the meanwhile...
Definition: simple_mem.cc:190
Port Object Declaration.
SimpleMemory(const SimpleMemoryParams *p)
Definition: simple_mem.cc:47
std::list< DeferredPacket > packetQueue
Internal (unbounded) storage to mimic the delay caused by the actual memory access.
Definition: simple_mem.hh:118
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:249
void recvRespRetry()
Definition: simple_mem.cc:233
void recvFunctional(PacketPtr pkt)
Definition: simple_mem.cc:90
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: simple_mem.cc:241
Tick recvAtomic(PacketPtr pkt)
Definition: simple_mem.cc:70
DrainState drain() override
Notify an object that it needs to drain its state.
Definition: simple_mem.cc:251
An abstract memory represents a contiguous block of physical memory, with an associated address range...
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:235
const Tick latency
Latency from that a request is accepted until the response is ready to be sent.
Definition: simple_mem.hh:106
Bitfield< 0 > p
EventFunctionWrapper releaseEvent
Definition: simple_mem.hh:151
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
Definition: simple_mem.cc:80
void dequeue()
Dequeue a packet from our internal packet queue and move it to the port where it will be sent as soon...
Definition: simple_mem.cc:201
Tick getLatency() const
Detemine the latency.
Definition: simple_mem.cc:226

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