43 #ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__ 44 #define __CPU_TRAFFIC_GEN_BASE_GEN_HH__ 105 virtual void enter() = 0;
138 Addr _blocksize,
Addr cacheline_size,
140 uint8_t read_percent,
Addr data_limit);
const Tick duration
Time to spend in this state.
const Addr dataLimit
Maximum amount of data to manipulate.
virtual void enter()=0
Enter this generator state.
const Tick minPeriod
Request generation period.
PacketPtr getPacket(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
Generate a new request and associated packet.
virtual PacketPtr getNextPacket()=0
Get the next generated packet.
virtual void exit()
Exit this generator state.
const MasterID masterID
The MasterID used for generating requests.
virtual Tick nextPacketTick(bool elastic, Tick delay) const =0
Determine the tick when the next packet is available.
uint64_t Tick
Tick count type.
const uint8_t readPercent
Percent of generated transactions that should be reads.
BaseGen(SimObject &obj, MasterID master_id, Tick _duration)
Create a base generator.
const Addr startAddr
Start of address range.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Declaration of the Packet class.
const Addr blocksize
Blocksize and address increment.
The traffic generator is a master module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces.
Base class for all generators, with the shared functionality and virtual functions for entering...
Abstract superclass for simulation objects.
const Addr endAddr
End of address range.
const std::string _name
Name to use for status and debug printing.
const Addr cacheLineSize
Cache line size in the simulated system.
std::string name() const
Get the name, useful for DPRINTFs.