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arch
generic
interrupts.hh
Go to the documentation of this file.
1
/*
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* Copyright 2019 Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
5
* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
7
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
9
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
12
* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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28
#ifndef __ARCH_GENERIC_INTERRUPTS_HH__
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#define __ARCH_GENERIC_INTERRUPTS_HH__
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#include "params/BaseInterrupts.hh"
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#include "
sim/sim_object.hh
"
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class
ThreadContext
;
35
class
BaseCPU
;
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37
class
BaseInterrupts
:
public
SimObject
38
{
39
protected
:
40
BaseCPU
*
cpu
;
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42
public
:
43
typedef
BaseInterruptsParams
Params
;
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45
BaseInterrupts
(Params *
p
) :
SimObject
(p) {}
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47
virtual
void
setCPU
(
BaseCPU
* newCPU) = 0;
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const
Params *
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params
()
const
51
{
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return
dynamic_cast<
const
Params *
>
(
_params
);
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}
54
55
/*
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* Functions for retrieving interrupts for the CPU to handle.
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*/
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59
/*
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* Return whether there are any interrupts waiting to be recognized.
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*/
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virtual
bool
checkInterrupts
(
ThreadContext
*tc)
const
= 0;
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/*
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* Return an interrupt to process. This should return an interrupt exactly
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* when checkInterrupts returns true.
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*/
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virtual
Fault
getInterrupt
(
ThreadContext
*tc) = 0;
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/*
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* Update interrupt related state after an interrupt has been processed.
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*/
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virtual
void
updateIntrInfo
(
ThreadContext
*tc) = 0;
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/*
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* Old functions needed for compatability but which will be phased out
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* eventually.
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*/
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virtual
void
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post
(
int
int_num,
int
index
)
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{
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panic
(
"Interrupts::post unimplemented!\n"
);
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}
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83
virtual
void
84
clear
(
int
int_num,
int
index
)
85
{
86
panic
(
"Interrupts::clear unimplemented!\n"
);
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}
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89
virtual
void
90
clearAll
()
91
{
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panic
(
"Interrupts::clearAll unimplemented!\n"
);
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}
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};
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#endif // __ARCH_GENERIC_INTERRUPTS_HH__
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition:
logging.hh:163
MipsISA::index
Bitfield< 30, 0 > index
Definition:
pra_constants.hh:44
BaseInterrupts::clearAll
virtual void clearAll()
Definition:
interrupts.hh:90
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:91
BaseInterrupts::getInterrupt
virtual Fault getInterrupt(ThreadContext *tc)=0
BaseInterrupts::setCPU
virtual void setCPU(BaseCPU *newCPU)=0
BaseInterrupts::clear
virtual void clear(int int_num, int index)
Definition:
interrupts.hh:84
BaseInterrupts::updateIntrInfo
virtual void updateIntrInfo(ThreadContext *tc)=0
BaseInterrupts
Definition:
interrupts.hh:37
BaseInterrupts::params
const Params * params() const
Definition:
interrupts.hh:50
BaseInterrupts::checkInterrupts
virtual bool checkInterrupts(ThreadContext *tc) const =0
BaseInterrupts::BaseInterrupts
BaseInterrupts(Params *p)
Definition:
interrupts.hh:45
BaseInterrupts::Params
BaseInterruptsParams Params
Definition:
interrupts.hh:43
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition:
sim_object.hh:111
sim_object.hh
BaseCPU
Definition:
cpu_dummy.hh:43
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
Fault
std::shared_ptr< FaultBase > Fault
Definition:
types.hh:238
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:93
BaseInterrupts::post
virtual void post(int int_num, int index)
Definition:
interrupts.hh:78
BaseInterrupts::cpu
BaseCPU * cpu
Definition:
interrupts.hh:40
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