gem5  v20.0.0.3
decoder.hh
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28 
29 #ifndef __ARCH_POWER_DECODER_HH__
30 #define __ARCH_POWER_DECODER_HH__
31 
33 #include "arch/types.hh"
34 #include "cpu/static_inst.hh"
35 
36 namespace PowerISA
37 {
38 
39 class ISA;
40 class Decoder
41 {
42  protected:
43  // The extended machine instruction being generated
45  bool instDone;
46 
47  public:
48  Decoder(ISA* isa = nullptr) : instDone(false)
49  {
50  }
51 
52  void
54  {
55  }
56 
57  void
59  {
60  instDone = false;
61  }
62 
63  // Use this to give data to the predecoder. This should be used
64  // when there is control flow.
65  void
66  moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
67  {
68  emi = betoh(inst);
69  instDone = true;
70  }
71 
72  // Use this to give data to the predecoder. This should be used
73  // when instructions are executed in order.
74  void
75  moreBytes(MachInst machInst)
76  {
77  moreBytes(0, 0, machInst);
78  }
79 
80  bool
82  {
83  return true;
84  }
85 
86  bool
88  {
89  return instDone;
90  }
91 
92  void takeOverFrom(Decoder *old) {}
93 
94  protected:
97 
98  public:
100 
106  {
107  return defaultCache.decode(this, mach_inst, addr);
108  }
109 
112  {
113  if (!instDone)
114  return NULL;
115  instDone = false;
116  return decode(emi, nextPC.instAddr());
117  }
118 };
119 
120 } // namespace PowerISA
121 
122 #endif // __ARCH_POWER_DECODER_HH__
bool instReady()
Definition: decoder.hh:87
uint64_t ExtMachInst
Definition: types.hh:39
StaticInstPtr decodeInst(ExtMachInst mach_inst)
ip6_addr_t addr
Definition: inet.hh:330
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:48
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:105
void takeOverFrom(Decoder *old)
Definition: decoder.hh:92
bool needMoreBytes()
Definition: decoder.hh:81
void process()
Definition: decoder.hh:53
ExtMachInst emi
Definition: decoder.hh:44
Bitfield< 4 > pc
uint32_t MachInst
Definition: types.hh:39
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Definition: decoder.hh:66
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:40
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
StaticInstPtr decode(PowerISA::PCState &nextPC)
Definition: decoder.hh:111
T betoh(T value)
Definition: byteswap.hh:143
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:96
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
void moreBytes(MachInst machInst)
Definition: decoder.hh:75

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