Go to the documentation of this file.
35 #ifndef __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
36 #define __MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
38 #include <unordered_map>
46 #include "params/RubySystem.hh"
116 uint64_t cache_trace_size,
117 uint64_t block_size_bytes);
121 uint64_t &uncompressed_trace_size);
123 uint64_t uncompressed_trace_size);
146 std::unordered_map<unsigned, std::vector<AbstractController*>>
netCntrls;
154 #endif //__MEM_RUBY_SYSTEM_RUBYSYSTEM_HH__
virtual void regStats()
Callback to set stat parameters.
std::vector< std::map< uint32_t, AbstractController * > > m_abstract_controls
bool functionalRead(Packet *ptr)
static uint32_t getBlockSizeBytes()
void registerAbstractController(AbstractController *)
void regStats(const std::string &name)
SimpleMemory * m_phys_mem
SimpleMemory * getPhysMem()
void unserialize(CheckpointIn &cp) override
Unserialize an object.
static void writeCompressedTrace(uint8_t *raw_data, std::string file, uint64_t uncompressed_trace_size)
std::unordered_map< RequestorID, unsigned > requestorToNetwork
static uint32_t m_block_size_bytes
The simple memory is a basic single-ported memory controller with a configurable throughput and laten...
void resetStats() override
Callback to reset stats.
void drainResume() override
Resume execution after a successful drain.
uint64_t Tick
Tick count type.
RubySystem(const Params *p)
void registerMachineID(const MachineID &mach_id, Network *network)
static bool m_cooldown_enabled
std::unordered_map< unsigned, std::vector< AbstractController * > > netCntrls
std::vector< std::unique_ptr< Network > > m_networks
void registerRequestorIDs()
void regStats() override
Callback to set stat parameters.
void registerNetwork(Network *)
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
const bool m_access_backing_store
void schedule(Event &event, Tick when)
void memWriteback() override
Write back dirty buffers to memory using functional writes.
static void readCompressedTrace(std::string filename, uint8_t *&raw_data, uint64_t &uncompressed_trace_size)
std::vector< AbstractController * > m_abs_cntrl_vec
bool empty() const
Returns true if no events are queued.
void makeCacheRecorder(uint8_t *uncompressed_trace, uint64_t cache_trace_size, uint64_t block_size_bytes)
bool functionalWrite(Packet *ptr)
bool getAccessBackingStore()
RubySystem & operator=(const RubySystem &obj)
std::unordered_map< MachineID, unsigned > machineToNetwork
void serialize(CheckpointOut &cp) const override
Serialize an object.
static bool getCooldownEnabled()
static uint32_t getMemorySizeBits()
static uint32_t m_memory_size_bits
virtual const std::string name() const
const Params * params() const
static bool m_randomization
void startup() override
startup() is the final initialization call before simulation.
static bool getWarmupEnabled()
static bool m_warmup_enabled
const SimObjectParams * _params
Cached copy of the object parameters.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
EventQueue * eventq
A pointer to this object's event queue.
Cycles is a wrapper class for representing cycle counts, i.e.
static unsigned m_systems_to_warmup
std::ostream CheckpointOut
static int getRandomization()
void enqueueRubyEvent(Tick tick)
static uint32_t m_block_size_bits
static uint32_t getBlockSizeBits()
CacheRecorder * m_cache_recorder
Generated on Wed Sep 30 2020 14:02:14 for gem5 by doxygen 1.8.17