gem5  v20.1.0.0
branch.hh
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40 
41 #ifndef __ARCH_ARM_INSTS_BRANCH_HH__
42 #define __ARCH_ARM_INSTS_BRANCH_HH__
43 
45 
46 namespace ArmISA
47 {
48 // Branch to a target computed with an immediate
49 class BranchImm : public PredOp
50 {
51  protected:
52  int32_t imm;
53 
54  public:
55  BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
56  int32_t _imm) :
57  PredOp(mnem, _machInst, __opClass), imm(_imm)
58  {}
59 
60  std::string generateDisassembly(
61  Addr pc, const Loader::SymbolTable *symtab) const override;
62 };
63 
64 // Conditionally Branch to a target computed with an immediate
65 class BranchImmCond : public BranchImm
66 {
67  public:
68  BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
69  int32_t _imm, ConditionCode _condCode) :
70  BranchImm(mnem, _machInst, __opClass, _imm)
71  {
72  // Only update if this isn't part of an IT block
73  if (!machInst.itstateMask)
74  condCode = _condCode;
75  }
76 };
77 
78 // Branch to a target computed with a register
79 class BranchReg : public PredOp
80 {
81  protected:
83 
84  public:
85  BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
86  IntRegIndex _op1) :
87  PredOp(mnem, _machInst, __opClass), op1(_op1)
88  {}
89 
90  std::string generateDisassembly(
91  Addr pc, const Loader::SymbolTable *symtab) const override;
92 };
93 
94 // Conditionally Branch to a target computed with a register
95 class BranchRegCond : public BranchReg
96 {
97  public:
98  BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
99  IntRegIndex _op1, ConditionCode _condCode) :
100  BranchReg(mnem, _machInst, __opClass, _op1)
101  {
102  // Only update if this isn't part of an IT block
103  if (!machInst.itstateMask)
104  condCode = _condCode;
105  }
106 };
107 
108 // Branch to a target computed with two registers
109 class BranchRegReg : public PredOp
110 {
111  protected:
114 
115  public:
116  BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
117  IntRegIndex _op1, IntRegIndex _op2) :
118  PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
119  {}
120 
121  std::string generateDisassembly(
122  Addr pc, const Loader::SymbolTable *symtab) const override;
123 };
124 
125 // Branch to a target computed with an immediate and a register
126 class BranchImmReg : public PredOp
127 {
128  protected:
129  int32_t imm;
131 
132  public:
133  BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
134  int32_t _imm, IntRegIndex _op1) :
135  PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
136  {}
137 };
138 
139 }
140 
141 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
ArmISA::PredOp::condCode
ConditionCode condCode
Definition: pred_inst.hh:214
ArmISA::ConditionCode
ConditionCode
Definition: ccregs.hh:63
ArmISA::BranchImm::imm
int32_t imm
Definition: branch.hh:52
ArmISA::BranchReg::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:45
ArmISA::BranchReg
Definition: branch.hh:79
ArmISA::BranchImm::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:55
Loader::SymbolTable
Definition: symtab.hh:59
ArmISA::IntRegIndex
IntRegIndex
Definition: intregs.hh:51
ArmISA::BranchRegCond
Definition: branch.hh:95
ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:210
ArmISA::BranchRegReg::op2
IntRegIndex op2
Definition: branch.hh:113
ArmISA
Definition: ccregs.hh:41
ArmISA::BranchImmReg
Definition: branch.hh:126
ArmISA::BranchRegReg::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: branch.cc:65
ArmISA::BranchRegCond::BranchRegCond
BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, ConditionCode _condCode)
Definition: branch.hh:98
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::BranchReg::op1
IntRegIndex op1
Definition: branch.hh:82
ArmISA::BranchImmCond
Definition: branch.hh:65
ArmISA::BranchRegReg::op1
IntRegIndex op1
Definition: branch.hh:112
StaticInst::ExtMachInst
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
Definition: static_inst.hh:89
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
pred_inst.hh
ArmISA::BranchImmCond::BranchImmCond
BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, ConditionCode _condCode)
Definition: branch.hh:68
ArmISA::BranchImmReg::BranchImmReg
BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm, IntRegIndex _op1)
Definition: branch.hh:133
StaticInst::machInst
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:243
ArmISA::BranchReg::BranchReg
BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1)
Definition: branch.hh:85
ArmISA::BranchImm::BranchImm
BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, int32_t _imm)
Definition: branch.hh:55
ArmISA::BranchImmReg::op1
IntRegIndex op1
Definition: branch.hh:130
ArmISA::BranchRegReg::BranchRegReg
BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2)
Definition: branch.hh:116
ArmISA::BranchImmReg::imm
int32_t imm
Definition: branch.hh:129
ArmISA::BranchImm
Definition: branch.hh:49
ArmISA::BranchRegReg
Definition: branch.hh:109

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