gem5  v20.1.0.0
bpred_unit.cc
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42 
43 #include "cpu/pred/bpred_unit.hh"
44 
45 #include <algorithm>
46 
47 #include "arch/types.hh"
48 #include "arch/utility.hh"
49 #include "base/trace.hh"
50 #include "config/the_isa.hh"
51 #include "debug/Branch.hh"
52 
54  : SimObject(params),
55  numThreads(params->numThreads),
56  predHist(numThreads),
57  BTB(params->BTBEntries,
58  params->BTBTagSize,
59  params->instShiftAmt,
60  params->numThreads),
61  RAS(numThreads),
62  iPred(params->indirectBranchPred),
63  stats(this),
64  instShiftAmt(params->instShiftAmt)
65 {
66  for (auto& r : RAS)
67  r.init(params->RASSize);
68 }
69 
71  : Stats::Group(parent),
72  ADD_STAT(lookups, "Number of BP lookups"),
73  ADD_STAT(condPredicted, "Number of conditional branches predicted"),
74  ADD_STAT(condIncorrect, "Number of conditional branches incorrect"),
75  ADD_STAT(BTBLookups, "Number of BTB lookups"),
76  ADD_STAT(BTBHits, "Number of BTB hits"),
77  ADD_STAT(BTBHitPct, "BTB Hit Percentage",
78  (BTBHits / BTBLookups) * 100),
79  ADD_STAT(RASUsed, "Number of times the RAS was used to get a target."),
80  ADD_STAT(RASIncorrect, "Number of incorrect RAS predictions."),
81  ADD_STAT(indirectLookups, "Number of indirect predictor lookups."),
82  ADD_STAT(indirectHits, "Number of indirect target hits."),
83  ADD_STAT(indirectMisses, "Number of indirect misses."),
84  ADD_STAT(indirectMispredicted, "Number of mispredicted indirect"
85  " branches.")
86 {
88 }
89 
92 {
94  ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
95 
96  return ptr;
97 }
98 
99 void
101 {
102  ppBranches = pmuProbePoint("Branches");
103  ppMisses = pmuProbePoint("Misses");
104 }
105 
106 void
108 {
109  // We shouldn't have any outstanding requests when we resume from
110  // a drained system.
111  for (const auto& ph M5_VAR_USED : predHist)
112  assert(ph.empty());
113 }
114 
115 bool
116 BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
118 {
119  // See if branch predictor predicts taken.
120  // If so, get its target addr either from the BTB or the RAS.
121  // Save off record of branch stuff so the RAS can be fixed
122  // up once it's done.
123 
124  bool pred_taken = false;
125  TheISA::PCState target = pc;
126 
127  ++stats.lookups;
128  ppBranches->notify(1);
129 
130  void *bp_history = NULL;
131  void *indirect_history = NULL;
132 
133  if (inst->isUncondCtrl()) {
134  DPRINTF(Branch, "[tid:%i] [sn:%llu] "
135  "Unconditional control\n",
136  tid,seqNum);
137  pred_taken = true;
138  // Tell the BP there was an unconditional branch.
139  uncondBranch(tid, pc.instAddr(), bp_history);
140  } else {
142  pred_taken = lookup(tid, pc.instAddr(), bp_history);
143 
144  DPRINTF(Branch, "[tid:%i] [sn:%llu] "
145  "Branch predictor predicted %i for PC %s\n",
146  tid, seqNum, pred_taken, pc);
147  }
148 
149  const bool orig_pred_taken = pred_taken;
150  if (iPred) {
151  iPred->genIndirectInfo(tid, indirect_history);
152  }
153 
154  DPRINTF(Branch, "[tid:%i] [sn:%llu] "
155  "Creating prediction history "
156  "for PC %s\n", tid, seqNum, pc);
157 
158  PredictorHistory predict_record(seqNum, pc.instAddr(), pred_taken,
159  bp_history, indirect_history, tid, inst);
160 
161  // Now lookup in the BTB or RAS.
162  if (pred_taken) {
163  if (inst->isReturn()) {
164  ++stats.RASUsed;
165  predict_record.wasReturn = true;
166  // If it's a function return call, then look up the address
167  // in the RAS.
168  TheISA::PCState rasTop = RAS[tid].top();
169  target = TheISA::buildRetPC(pc, rasTop);
170 
171  // Record the top entry of the RAS, and its index.
172  predict_record.usedRAS = true;
173  predict_record.RASIndex = RAS[tid].topIdx();
174  predict_record.RASTarget = rasTop;
175 
176  RAS[tid].pop();
177 
178  DPRINTF(Branch, "[tid:%i] [sn:%llu] Instruction %s is a return, "
179  "RAS predicted target: %s, RAS index: %i\n",
180  tid, seqNum, pc, target, predict_record.RASIndex);
181  } else {
182 
183  if (inst->isCall()) {
184  RAS[tid].push(pc);
185  predict_record.pushedRAS = true;
186 
187  // Record that it was a call so that the top RAS entry can
188  // be popped off if the speculation is incorrect.
189  predict_record.wasCall = true;
190 
191  DPRINTF(Branch,
192  "[tid:%i] [sn:%llu] Instruction %s was a call, adding "
193  "%s to the RAS index: %i\n",
194  tid, seqNum, pc, pc, RAS[tid].topIdx());
195  }
196 
197  if (inst->isDirectCtrl() || !iPred) {
198  ++stats.BTBLookups;
199  // Check BTB on direct branches
200  if (BTB.valid(pc.instAddr(), tid)) {
201  ++stats.BTBHits;
202  // If it's not a return, use the BTB to get target addr.
203  target = BTB.lookup(pc.instAddr(), tid);
204  DPRINTF(Branch,
205  "[tid:%i] [sn:%llu] Instruction %s predicted "
206  "target is %s\n",
207  tid, seqNum, pc, target);
208  } else {
209  DPRINTF(Branch, "[tid:%i] [sn:%llu] BTB doesn't have a "
210  "valid entry\n",tid,seqNum);
211  pred_taken = false;
212  predict_record.predTaken = pred_taken;
213  // The Direction of the branch predictor is altered
214  // because the BTB did not have an entry
215  // The predictor needs to be updated accordingly
216  if (!inst->isCall() && !inst->isReturn()) {
217  btbUpdate(tid, pc.instAddr(), bp_history);
218  DPRINTF(Branch,
219  "[tid:%i] [sn:%llu] btbUpdate "
220  "called for %s\n",
221  tid, seqNum, pc);
222  } else if (inst->isCall() && !inst->isUncondCtrl()) {
223  RAS[tid].pop();
224  predict_record.pushedRAS = false;
225  }
226  TheISA::advancePC(target, inst);
227  }
228  } else {
229  predict_record.wasIndirect = true;
231  //Consult indirect predictor on indirect control
232  if (iPred->lookup(pc.instAddr(), target, tid)) {
233  // Indirect predictor hit
235  DPRINTF(Branch,
236  "[tid:%i] [sn:%llu] "
237  "Instruction %s predicted "
238  "indirect target is %s\n",
239  tid, seqNum, pc, target);
240  } else {
242  pred_taken = false;
243  predict_record.predTaken = pred_taken;
244  DPRINTF(Branch,
245  "[tid:%i] [sn:%llu] "
246  "Instruction %s no indirect "
247  "target\n",
248  tid, seqNum, pc);
249  if (!inst->isCall() && !inst->isReturn()) {
250 
251  } else if (inst->isCall() && !inst->isUncondCtrl()) {
252  RAS[tid].pop();
253  predict_record.pushedRAS = false;
254  }
255  TheISA::advancePC(target, inst);
256  }
257  iPred->recordIndirect(pc.instAddr(), target.instAddr(), seqNum,
258  tid);
259  }
260  }
261  } else {
262  if (inst->isReturn()) {
263  predict_record.wasReturn = true;
264  }
265  TheISA::advancePC(target, inst);
266  }
267  predict_record.target = target.instAddr();
268 
269  pc = target;
270 
271  if (iPred) {
272  // Update the indirect predictor with the direction prediction
273  // Note that this happens after indirect lookup, so it does not use
274  // the new information
275  // Note also that we use orig_pred_taken instead of pred_taken in
276  // as this is the actual outcome of the direction prediction
277  iPred->updateDirectionInfo(tid, orig_pred_taken);
278  }
279 
280  predHist[tid].push_front(predict_record);
281 
282  DPRINTF(Branch,
283  "[tid:%i] [sn:%llu] History entry added. "
284  "predHist.size(): %i\n",
285  tid, seqNum, predHist[tid].size());
286 
287  return pred_taken;
288 }
289 
290 void
292 {
293  DPRINTF(Branch, "[tid:%i] Committing branches until "
294  "sn:%llu]\n", tid, done_sn);
295 
296  while (!predHist[tid].empty() &&
297  predHist[tid].back().seqNum <= done_sn) {
298  // Update the branch predictor with the correct results.
299  update(tid, predHist[tid].back().pc,
300  predHist[tid].back().predTaken,
301  predHist[tid].back().bpHistory, false,
302  predHist[tid].back().inst,
303  predHist[tid].back().target);
304 
305  if (iPred) {
306  iPred->commit(done_sn, tid, predHist[tid].back().indirectHistory);
307  }
308 
309  predHist[tid].pop_back();
310  }
311 }
312 
313 void
314 BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid)
315 {
316  History &pred_hist = predHist[tid];
317 
318  if (iPred) {
319  iPred->squash(squashed_sn, tid);
320  }
321 
322  while (!pred_hist.empty() &&
323  pred_hist.front().seqNum > squashed_sn) {
324  if (pred_hist.front().usedRAS) {
325  DPRINTF(Branch, "[tid:%i] [squash sn:%llu]"
326  " Restoring top of RAS to: %i,"
327  " target: %s\n", tid, squashed_sn,
328  pred_hist.front().RASIndex, pred_hist.front().RASTarget);
329 
330  RAS[tid].restore(pred_hist.front().RASIndex,
331  pred_hist.front().RASTarget);
332  } else if (pred_hist.front().wasCall && pred_hist.front().pushedRAS) {
333  // Was a call but predicated false. Pop RAS here
334  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] Squashing"
335  " Call [sn:%llu] PC: %s Popping RAS\n", tid, squashed_sn,
336  pred_hist.front().seqNum, pred_hist.front().pc);
337  RAS[tid].pop();
338  }
339 
340  // This call should delete the bpHistory.
341  squash(tid, pred_hist.front().bpHistory);
342  if (iPred) {
343  iPred->deleteIndirectInfo(tid, pred_hist.front().indirectHistory);
344  }
345 
346  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] "
347  "Removing history for [sn:%llu] "
348  "PC %#x\n", tid, squashed_sn, pred_hist.front().seqNum,
349  pred_hist.front().pc);
350 
351  pred_hist.pop_front();
352 
353  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] predHist.size(): %i\n",
354  tid, squashed_sn, predHist[tid].size());
355  }
356 }
357 
358 void
359 BPredUnit::squash(const InstSeqNum &squashed_sn,
360  const TheISA::PCState &corrTarget,
361  bool actually_taken, ThreadID tid)
362 {
363  // Now that we know that a branch was mispredicted, we need to undo
364  // all the branches that have been seen up until this branch and
365  // fix up everything.
366  // NOTE: This should be call conceivably in 2 scenarios:
367  // (1) After an branch is executed, it updates its status in the ROB
368  // The commit stage then checks the ROB update and sends a signal to
369  // the fetch stage to squash history after the mispredict
370  // (2) In the decode stage, you can find out early if a unconditional
371  // PC-relative, branch was predicted incorrectly. If so, a signal
372  // to the fetch stage is sent to squash history after the mispredict
373 
374  History &pred_hist = predHist[tid];
375 
377  ppMisses->notify(1);
378 
379  DPRINTF(Branch, "[tid:%i] Squashing from sequence number %i, "
380  "setting target to %s\n", tid, squashed_sn, corrTarget);
381 
382  // Squash All Branches AFTER this mispredicted branch
383  squash(squashed_sn, tid);
384 
385  // If there's a squash due to a syscall, there may not be an entry
386  // corresponding to the squash. In that case, don't bother trying to
387  // fix up the entry.
388  if (!pred_hist.empty()) {
389 
390  auto hist_it = pred_hist.begin();
391  //HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(),
392  // squashed_sn);
393 
394  //assert(hist_it != pred_hist.end());
395  if (pred_hist.front().seqNum != squashed_sn) {
396  DPRINTF(Branch, "Front sn %i != Squash sn %i\n",
397  pred_hist.front().seqNum, squashed_sn);
398 
399  assert(pred_hist.front().seqNum == squashed_sn);
400  }
401 
402 
403  if ((*hist_it).usedRAS) {
405  DPRINTF(Branch,
406  "[tid:%i] [squash sn:%llu] Incorrect RAS [sn:%llu]\n",
407  tid, squashed_sn, hist_it->seqNum);
408  }
409 
410  // There are separate functions for in-order and out-of-order
411  // branch prediction, but not for update. Therefore, this
412  // call should take into account that the mispredicted branch may
413  // be on the wrong path (i.e., OoO execution), and that the counter
414  // counter table(s) should not be updated. Thus, this call should
415  // restore the state of the underlying predictor, for instance the
416  // local/global histories. The counter tables will be updated when
417  // the branch actually commits.
418 
419  // Remember the correct direction for the update at commit.
420  pred_hist.front().predTaken = actually_taken;
421  pred_hist.front().target = corrTarget.instAddr();
422 
423  update(tid, (*hist_it).pc, actually_taken,
424  pred_hist.front().bpHistory, true, pred_hist.front().inst,
425  corrTarget.instAddr());
426 
427  if (iPred) {
429  pred_hist.front().indirectHistory, actually_taken);
430  }
431 
432  if (actually_taken) {
433  if (hist_it->wasReturn && !hist_it->usedRAS) {
434  DPRINTF(Branch, "[tid:%i] [squash sn:%llu] "
435  "Incorrectly predicted "
436  "return [sn:%llu] PC: %#x\n", tid, squashed_sn,
437  hist_it->seqNum,
438  hist_it->pc);
439  RAS[tid].pop();
440  hist_it->usedRAS = true;
441  }
442  if (hist_it->wasIndirect) {
444  if (iPred) {
446  hist_it->seqNum, pred_hist.front().indirectHistory,
447  corrTarget, tid);
448  }
449  } else {
450  DPRINTF(Branch,"[tid:%i] [squash sn:%llu] "
451  "BTB Update called for [sn:%llu] "
452  "PC %#x\n", tid, squashed_sn,
453  hist_it->seqNum, hist_it->pc);
454 
455  BTB.update((*hist_it).pc, corrTarget, tid);
456  }
457  } else {
458  //Actually not Taken
459  if (hist_it->usedRAS) {
460  DPRINTF(Branch,
461  "[tid:%i] [squash sn:%llu] Incorrectly predicted "
462  "return [sn:%llu] PC: %#x Restoring RAS\n", tid,
463  squashed_sn,
464  hist_it->seqNum, hist_it->pc);
465  DPRINTF(Branch,
466  "[tid:%i] [squash sn:%llu] Restoring top of RAS "
467  "to: %i, target: %s\n", tid, squashed_sn,
468  hist_it->RASIndex, hist_it->RASTarget);
469  RAS[tid].restore(hist_it->RASIndex, hist_it->RASTarget);
470  hist_it->usedRAS = false;
471  } else if (hist_it->wasCall && hist_it->pushedRAS) {
472  //Was a Call but predicated false. Pop RAS here
473  DPRINTF(Branch,
474  "[tid:%i] [squash sn:%llu] "
475  "Incorrectly predicted "
476  "Call [sn:%llu] PC: %s Popping RAS\n",
477  tid, squashed_sn,
478  hist_it->seqNum, hist_it->pc);
479  RAS[tid].pop();
480  hist_it->pushedRAS = false;
481  }
482  }
483  } else {
484  DPRINTF(Branch, "[tid:%i] [sn:%llu] pred_hist empty, can't "
485  "update\n", tid, squashed_sn);
486  }
487 }
488 
489 void
491 {
492  int i = 0;
493  for (const auto& ph : predHist) {
494  if (!ph.empty()) {
495  auto pred_hist_it = ph.begin();
496 
497  cprintf("predHist[%i].size(): %i\n", i++, ph.size());
498 
499  while (pred_hist_it != ph.end()) {
500  cprintf("sn:%llu], PC:%#x, tid:%i, predTaken:%i, "
501  "bpHistory:%#x\n",
502  pred_hist_it->seqNum, pred_hist_it->pc,
503  pred_hist_it->tid, pred_hist_it->predTaken,
504  pred_hist_it->bpHistory);
505  pred_hist_it++;
506  }
507 
508  cprintf("\n");
509  }
510  }
511 }
512 
IndirectPredictor::updateDirectionInfo
virtual void updateDirectionInfo(ThreadID tid, bool actually_taken)=0
BPredUnit::PredictorHistory::wasReturn
bool wasReturn
Whether or not the instruction was a return.
Definition: bpred_unit.hh:244
BPredUnit::regProbePoints
void regProbePoints() override
Register probe points for this object.
Definition: bpred_unit.cc:100
StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:178
IndirectPredictor::genIndirectInfo
virtual void genIndirectInfo(ThreadID tid, void *&indirect_history)=0
BPredUnit::BPredUnitStats::BTBHitPct
Stats::Formula BTBHitPct
Stat for percent times an entry in BTB found.
Definition: bpred_unit.hh:294
ArmISA::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC)
Definition: utility.hh:59
BPredUnit::ppMisses
ProbePoints::PMUUPtr ppMisses
Miss-predicted branches.
Definition: bpred_unit.hh:337
IndirectPredictor::recordTarget
virtual void recordTarget(InstSeqNum seq_num, void *indirect_history, const TheISA::PCState &target, ThreadID tid)=0
BPredUnit::RAS
std::vector< ReturnAddrStack > RAS
The per-thread return address stack.
Definition: bpred_unit.hh:275
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
IndirectPredictor::recordIndirect
virtual void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, ThreadID tid)=0
BPredUnit::dump
void dump()
Definition: bpred_unit.cc:490
BPredUnit::BPredUnitStats::lookups
Stats::Scalar lookups
Stat for number of BP lookups.
Definition: bpred_unit.hh:284
BPredUnit::BPredUnitStats::indirectMisses
Stats::Scalar indirectMisses
Stat for the number of indirect target misses.
Definition: bpred_unit.hh:305
BPredUnit::PredictorHistory::RASTarget
TheISA::PCState RASTarget
The RAS target (only valid if a return).
Definition: bpred_unit.hh:223
BPredUnit::iPred
IndirectPredictor * iPred
The indirect target predictor.
Definition: bpred_unit.hh:278
ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:50
BPredUnit::PredictorHistory::target
Addr target
Target of the branch.
Definition: bpred_unit.hh:252
BPredUnit::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: bpred_unit.cc:107
BPredUnit::btbUpdate
virtual void btbUpdate(ThreadID tid, Addr instPC, void *&bp_history)=0
If a branch is not taken, because the BTB address is invalid or missing, this function sets the appro...
BPredUnit::BPredUnitStats::condPredicted
Stats::Scalar condPredicted
Stat for number of conditional branches predicted.
Definition: bpred_unit.hh:286
IndirectPredictor::commit
virtual void commit(InstSeqNum seq_num, ThreadID tid, void *indirect_history)=0
BPredUnit::pmuProbePoint
ProbePoints::PMUUPtr pmuProbePoint(const char *name)
Helper method to instantiate probe points belonging to this object.
Definition: bpred_unit.cc:91
BPredUnit::BTB
DefaultBTB BTB
The BTB.
Definition: bpred_unit.hh:272
BPredUnit::BPredUnitStats::BPredUnitStats
BPredUnitStats(Stats::Group *parent)
Definition: bpred_unit.cc:70
BPredUnit::update
void update(const InstSeqNum &done_sn, ThreadID tid)
Tells the branch predictor to commit any updates until the given sequence number.
Definition: bpred_unit.cc:291
ArmISA::advancePC
void advancePC(PCState &pc, const StaticInstPtr &inst)
Definition: utility.hh:405
BPredUnit::BPredUnit
BPredUnit(const Params *p)
Definition: bpred_unit.cc:53
BPredUnit::lookup
virtual bool lookup(ThreadID tid, Addr instPC, void *&bp_history)=0
Looks up a given PC in the BP to see if it is taken or not taken.
BPredUnit::PredictorHistory
Definition: bpred_unit.hh:188
IndirectPredictor::changeDirectionPrediction
virtual void changeDirectionPrediction(ThreadID tid, void *indirect_history, bool actually_taken)=0
BPredUnit::BPredUnitStats::indirectHits
Stats::Scalar indirectHits
Stat for the number of indirect target hits.
Definition: bpred_unit.hh:303
BPredUnit::BPredUnitStats::condIncorrect
Stats::Scalar condIncorrect
Stat for number of conditional branches predicted incorrectly.
Definition: bpred_unit.hh:288
DefaultBTB::update
void update(Addr instPC, const TheISA::PCState &targetPC, ThreadID tid)
Updates the BTB with the target of a branch.
Definition: btb.cc:128
BPredUnit::BPredUnitStats::BTBHits
Stats::Scalar BTBHits
Stat for number of BTB hits.
Definition: bpred_unit.hh:292
cprintf
void cprintf(const char *format, const Args &...args)
Definition: cprintf.hh:152
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ADD_STAT
#define ADD_STAT(n,...)
Convenience macro to add a stat to a statistics group.
Definition: group.hh:67
BPredUnit::BPredUnitStats::RASUsed
Stats::Scalar RASUsed
Stat for number of times the RAS is used to get a target.
Definition: bpred_unit.hh:296
BPredUnit::BPredUnitStats::indirectMispredicted
Stats::Scalar indirectMispredicted
Stat for the number of indirect target mispredictions.
Definition: bpred_unit.hh:307
BPredUnit::BPredUnitStats::indirectLookups
Stats::Scalar indirectLookups
Stat for the number of indirect target lookups.
Definition: bpred_unit.hh:301
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
DefaultBTB::valid
bool valid(Addr instPC, ThreadID tid)
Checks if a branch is in the BTB.
Definition: btb.cc:89
MipsISA::r
r
Definition: pra_constants.hh:95
BPredUnit::BPredUnitStats::RASIncorrect
Stats::Scalar RASIncorrect
Stat for number of times the RAS is incorrect.
Definition: bpred_unit.hh:298
IndirectPredictor::lookup
virtual bool lookup(Addr br_addr, TheISA::PCState &br_target, ThreadID tid)=0
BPredUnit::uncondBranch
virtual void uncondBranch(ThreadID tid, Addr pc, void *&bp_history)=0
BPredUnit::stats
BPredUnit::BPredUnitStats stats
BPredUnit::predHist
std::vector< History > predHist
The per-thread predictor history.
Definition: bpred_unit.hh:269
BPredUnit::PredictorHistory::usedRAS
bool usedRAS
Whether or not the RAS was used.
Definition: bpred_unit.hh:235
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
SimObject::params
const Params * params() const
Definition: sim_object.hh:119
IndirectPredictor::squash
virtual void squash(InstSeqNum seq_num, ThreadID tid)=0
BPredUnit::PredictorHistory::wasIndirect
bool wasIndirect
Wether this instruction was an indirect branch.
Definition: bpred_unit.hh:247
SimObject::getProbeManager
ProbeManager * getProbeManager()
Get the probe manager for this object.
Definition: sim_object.cc:117
ProbePoints::PMUUPtr
std::unique_ptr< PMU > PMUUPtr
Definition: pmu.hh:56
SimObject::name
virtual const std::string name() const
Definition: sim_object.hh:133
BPredUnit::PredictorHistory::RASIndex
unsigned RASIndex
The RAS index of the instruction (only valid if a call).
Definition: bpred_unit.hh:226
BPredUnit::PredictorHistory::wasCall
bool wasCall
Whether or not the instruction was a call.
Definition: bpred_unit.hh:241
BPredUnit::Params
BranchPredictorParams Params
Definition: bpred_unit.hh:65
Stats::DataWrap::precision
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
Definition: statistics.hh:319
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
bpred_unit.hh
BPredUnit::BPredUnitStats::BTBLookups
Stats::Scalar BTBLookups
Stat for number of BTB lookups.
Definition: bpred_unit.hh:290
std::deque
STL deque class.
Definition: stl.hh:44
Stats::Group
Statistics container.
Definition: group.hh:83
BPredUnit::predict
bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, TheISA::PCState &pc, ThreadID tid)
Predicts whether or not the instruction is a taken branch, and the target of the branch if it is take...
Definition: bpred_unit.cc:116
StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:176
Stats
Definition: statistics.cc:61
RefCountingPtr< StaticInst >
BPredUnit::PredictorHistory::pushedRAS
bool pushedRAS
Definition: bpred_unit.hh:238
trace.hh
DefaultBTB::lookup
TheISA::PCState lookup(Addr instPC, ThreadID tid)
Looks up an address in the BTB.
Definition: btb.cc:110
BPredUnit::ppBranches
ProbePoints::PMUUPtr ppBranches
Branches seen by the branch predictor.
Definition: bpred_unit.hh:334
IndirectPredictor::deleteIndirectInfo
virtual void deleteIndirectInfo(ThreadID tid, void *indirect_history)=0
BPredUnit::squash
void squash(const InstSeqNum &squashed_sn, ThreadID tid)
Squashes all outstanding updates until a given sequence number.
Definition: bpred_unit.cc:314
StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:177
BPredUnit::PredictorHistory::predTaken
bool predTaken
Whether or not it was predicted taken.
Definition: bpred_unit.hh:232
StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:181
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:92

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