cache_blk.hh

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#ifndef __MEM_CACHE_CACHE_BLK_HH__
#define __MEM_CACHE_CACHE_BLK_HH__
 
#include <cassert>
#include <cstdint>
#include <iosfwd>
#include <list>
#include <string>
 
#include "base/printable.hh"
#include "base/types.hh"
#include "mem/cache/replacement_policies/base.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
 
enum CacheBlkStatusBits : unsigned {
    BlkValid =          0x01,
    BlkWritable =       0x02,
    BlkReadable =       0x04,
    BlkDirty =          0x08,
    BlkHWPrefetched =   0x20,
    BlkSecure =         0x40,
    BlkCompressed =     0x80
};
 
class CacheBlk : public ReplaceableEntry
{
  public:
    uint32_t task_id;
 
    Addr tag;
    uint8_t *data;
 
    typedef unsigned State;
 
    State status;
 
    Tick whenReady;
 
    unsigned refCount;
 
    int srcRequestorId;
 
    Tick tickInserted;
 
  protected:
    class Lock {
      public:
        ContextID contextId;     // locking context
        Addr lowAddr;      // low address of lock range
        Addr highAddr;     // high address of lock range
 
        // check for matching execution context, and an address that
        // is within the lock
        bool matches(const RequestPtr &req) const
        {
            Addr req_low = req->getPaddr();
            Addr req_high = req_low + req->getSize() -1;
            return (contextId == req->contextId()) &&
                   (req_low >= lowAddr) && (req_high <= highAddr);
        }
 
        // check if a request is intersecting and thus invalidating the lock
        bool intersects(const RequestPtr &req) const
        {
            Addr req_low = req->getPaddr();
            Addr req_high = req_low + req->getSize() - 1;
 
            return (req_low <= highAddr) && (req_high >= lowAddr);
        }
 
        Lock(const RequestPtr &req)
            : contextId(req->contextId()),
              lowAddr(req->getPaddr()),
              highAddr(lowAddr + req->getSize() - 1)
        {
        }
    };
 
    std::list<Lock> lockList;
 
  public:
    CacheBlk() : data(nullptr), tickInserted(0)
    {
        invalidate();
    }
 
    CacheBlk(const CacheBlk&) = delete;
    CacheBlk& operator=(const CacheBlk&) = delete;
    virtual ~CacheBlk() {};
 
    bool isWritable() const
    {
        const State needed_bits = BlkWritable | BlkValid;
        return (status & needed_bits) == needed_bits;
    }
 
    bool isReadable() const
    {
        const State needed_bits = BlkReadable | BlkValid;
        return (status & needed_bits) == needed_bits;
    }
 
    bool isValid() const
    {
        return (status & BlkValid) != 0;
    }
 
    virtual void invalidate()
    {
        tag = MaxAddr;
        task_id = ContextSwitchTaskId::Unknown;
        status = 0;
        whenReady = MaxTick;
        refCount = 0;
        srcRequestorId = Request::invldRequestorId;
        lockList.clear();
    }
 
    bool isDirty() const
    {
        return (status & BlkDirty) != 0;
    }
 
    bool wasPrefetched() const
    {
        return (status & BlkHWPrefetched) != 0;
    }
 
    bool isSecure() const
    {
        return (status & BlkSecure) != 0;
    }
 
    virtual void setValid()
    {
        assert(!isValid());
        status |= BlkValid;
    }
 
    virtual void setSecure()
    {
        status |= BlkSecure;
    }
 
    Tick getWhenReady() const
    {
        assert(whenReady != MaxTick);
        return whenReady;
    }
 
    void setWhenReady(const Tick tick)
    {
        assert(tick >= tickInserted);
        whenReady = tick;
    }
 
    virtual void insert(const Addr tag, const bool is_secure,
                        const int src_requestor_ID, const uint32_t task_ID);
 
    void trackLoadLocked(PacketPtr pkt)
    {
        assert(pkt->isLLSC());
        auto l = lockList.begin();
        while (l != lockList.end()) {
            if (l->intersects(pkt->req))
                l = lockList.erase(l);
            else
                ++l;
        }
 
        lockList.emplace_front(pkt->req);
    }
 
    void clearLoadLocks(const RequestPtr &req)
    {
        auto l = lockList.begin();
        while (l != lockList.end()) {
            if (l->intersects(req) && l->contextId != req->contextId()) {
                l = lockList.erase(l);
            } else {
                ++l;
            }
        }
    }
 
    std::string
    print() const override
    {
        unsigned state = isWritable() << 2 | isDirty() << 1 | isValid();
        char s = '?';
        switch (state) {
          case 0b111: s = 'M'; break;
          case 0b011: s = 'O'; break;
          case 0b101: s = 'E'; break;
          case 0b001: s = 'S'; break;
          case 0b000: s = 'I'; break;
          default:    s = 'T'; break; // @TODO add other types
        }
        return csprintf("state: %x (%c) valid: %d writable: %d readable: %d "
                        "dirty: %d | tag: %#x %s", status, s,
                        isValid(), isWritable(), isReadable(), isDirty(), tag,
                        ReplaceableEntry::print());
    }
 
    bool checkWrite(PacketPtr pkt)
    {
        assert(pkt->isWrite());
 
        // common case
        if (!pkt->isLLSC() && lockList.empty())
            return true;
 
        const RequestPtr &req = pkt->req;
 
        if (pkt->isLLSC()) {
            // it's a store conditional... have to check for matching
            // load locked.
            bool success = false;
 
            auto l = lockList.begin();
            while (!success && l != lockList.end()) {
                if (l->matches(pkt->req)) {
                    // it's a store conditional, and as far as the
                    // memory system can tell, the requesting
                    // context's lock is still valid.
                    success = true;
                    lockList.erase(l);
                } else {
                    ++l;
                }
            }
 
            req->setExtraData(success ? 1 : 0);
            // clear any intersected locks from other contexts (our LL
            // should already have cleared them)
            clearLoadLocks(req);
            return success;
        } else {
            // a normal write, if there is any lock not from this
            // context we clear the list, thus for a private cache we
            // never clear locks on normal writes
            clearLoadLocks(req);
            return true;
        }
    }
};
 
class TempCacheBlk final : public CacheBlk
{
  private:
    Addr _addr;
 
  public:
    TempCacheBlk(unsigned size) : CacheBlk()
    {
        data = new uint8_t[size];
    }
    TempCacheBlk(const TempCacheBlk&) = delete;
    TempCacheBlk& operator=(const TempCacheBlk&) = delete;
    ~TempCacheBlk() { delete [] data; };
 
    void invalidate() override {
        CacheBlk::invalidate();
 
        _addr = MaxAddr;
    }
 
    void insert(const Addr addr, const bool is_secure,
                const int src_requestor_ID=0, const uint32_t task_ID=0)
                override
    {
        // Make sure that the block has been properly invalidated
        assert(status == 0);
 
        // Set block address
        _addr = addr;
 
        // Set secure state
        if (is_secure) {
            setSecure();
        }
 
        // Validate block
        setValid();
    }
 
    Addr getAddr() const
    {
        return _addr;
    }
};
 
class CacheBlkPrintWrapper : public Printable
{
    CacheBlk *blk;
  public:
    CacheBlkPrintWrapper(CacheBlk *_blk) : blk(_blk) {}
    virtual ~CacheBlkPrintWrapper() {}
    void print(std::ostream &o, int verbosity = 0,
               const std::string &prefix = "") const;
};
 
#endif //__MEM_CACHE_CACHE_BLK_HH__