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gem5
v20.1.0.0
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Go to the source code of this file.
Namespaces | |
| SimClock | |
| These are variables that are set based on the simulator frequency. | |
| SimClock::Float | |
| SimClock::Int | |
| These variables equal the number of ticks in the unit of time they're named after in a 64 bit integer. | |
Functions | |
| Tick | curTick () |
| The universal simulation clock. More... | |
| void | fixClockFrequency () |
| bool | clockFrequencyFixed () |
| void | setClockFrequency (Tick ticksPerSecond) |
| Tick | getClockFrequency () |
| void | setOutputDir (const std::string &dir) |
| void | registerExitCallback (const std::function< void()> &callback) |
| Register an exit callback. More... | |
| void | doExitCleanup () |
| Do C++ simulator exit processing. More... | |
| bool clockFrequencyFixed | ( | ) |
Definition at line 109 of file core.cc.
Referenced by pybind_init_core(), sc_core::sc_set_default_time_unit(), and sc_core::sc_set_time_resolution().
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inline |
The universal simulation clock.
The current simulated tick.
Definition at line 45 of file core.hh.
References _curEventQueue, and EventQueue::getCurTick().
Referenced by Prefetcher::SBOOE::Sandbox::access(), Prefetcher::SBOOE::access(), DRAMSim2::accessAndRespond(), DRAMsim3::accessAndRespond(), MemCtrl::accessAndRespond(), FlashDevice::accessDevice(), SimpleCache::accessTiming(), FlashDevice::actionComplete(), O3ThreadContext< Impl >::activate(), SimpleThread::activate(), FullO3CPU< O3CPUImpl >::activateContext(), ElasticTrace::addDepTraceRecord(), MemCtrl::addToReadQueue(), MemCtrl::addToWriteQueue(), CacheMemory::allocate(), BaseTrafficGen::allocateWaitingRespSlot(), SwitchAllocator::arbitrate_inports(), SwitchAllocator::arbitrate_outports(), DefaultFetch< Impl >::buildInst(), NVMInterface::burstReady(), BaseXBar::calcPacketTiming(), DistIface::RecvScheduler::calcReceiveTick(), BaseCache::calculateAccessLatency(), Prefetcher::SBOOE::calculatePrefetch(), NetworkInterface::calculateVC(), ArmSemihosting::callClock(), ArmSemihosting::callElapsed32(), ArmSemihosting::callElapsed64(), ArmSemihosting::callTime(), VncInput::captureFrameBuffer(), Sinic::Device::changeConfig(), TraceCPU::checkAndSchedExitEvent(), UncoalescedTable::checkDeadlock(), FlashDevice::checkDrain(), DRAMInterface::Rank::checkDrainDone(), DRAMInterface::checkRefreshState(), NetworkInterface::checkReschedule(), NetworkInterface::checkStallQueue(), IGbE::chkInterrupt(), MemCtrl::chooseNextFRFCFS(), NVMInterface::chooseRead(), BaseCache::CacheResponsePort::clearBlocked(), UFSHostDevice::clearInterrupt(), Intel8254Timer::Counter::CounterEvent::clocksLeft(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), GPUCoalescer::completeHitCallback(), MemTest::completeRequest(), LSQUnit< Impl >::completeStore(), SMMUTranslationProcess::completeTransaction(), PowerState::computeStats(), DRAMInterface::Rank::computeStats(), BaseTags::computeStatsVisitor(), Sinic::Base::cpuInterrupt(), NSGigE::cpuInterrupt(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), IGbE::cpuPostInt(), CPUProgressEvent::CPUProgressEvent(), TraceCPU::dcacheRetryRecvd(), DefaultDecode< Impl >::decodeInsts(), PacketQueue::deferredPacketReady(), MSHR::delay(), Prefetcher::BOP::delayQueueEventWrapper(), MessageBuffer::dequeue(), SimpleMemory::dequeue(), Sinic::Device::devIntrChangeMask(), NSGigE::devIntrChangeMask(), Sinic::Device::devIntrPost(), NSGigE::devIntrPost(), Linux::devRandom(), GPUDispatcher::dispatch(), DefaultIEW< Impl >::dispatchInsts(), Shader::dispatchWorkgroups(), Pl111::dmaDone(), HSADevice::dmaVirt(), HSAPacketProcessor::dmaVirt(), SMMUProcess::doBroadcastSignal(), DRAMInterface::doBurstAccess(), NVMInterface::doBurstAccess(), IdeDisk::doDmaDataRead(), IdeDisk::doDmaDataWrite(), IdeDisk::doDmaRead(), IdeDisk::doDmaTransfer(), IdeDisk::doDmaWrite(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptorWrapper(), SMMUProcess::doSemaphoreUp(), doSimLoop(), ThermalModel::doStep(), StoreTrace::downgrade(), MemCtrl::drain(), PCEventQueue::dump(), Trace::TarmacParserRecord::dump(), EventQueue::dump(), CheckerCPU::dumpAndExit(), EtherDump::dumpPacket(), PseudoInst::dumpresetstats(), PseudoInst::dumpstats(), LdsState::earliestReturnTime(), RegisterFile::enqRegBusyEvent(), RegisterFile::enqRegFreeEvent(), EtherSwitch::Interface::enqueue(), TraceGen::enter(), Event::Event(), GlobalMemPipeline::exec(), GPUDispatcher::exec(), Shader::execScheduledAdds(), TraceCPU::ElasticDataGen::execute(), exitSimLoop(), DefaultFetch< Impl >::fetch(), IGbE::DescCache< iGbReg::RxDesc >::fetchDescriptors(), IGbE::DescCache< iGbReg::RxDesc >::fetchDescriptors1(), ElasticTrace::fetchReqTrace(), GoodbyeObject::fillBuffer(), UFSHostDevice::finalUTP(), Minor::LSQ::SplitDataRequest::finish(), DefaultFetch< Impl >::finishTranslation(), ArmISA::flattenIntRegModeIndex(), NetworkInterface::flitisizeMessage(), DRAMInterface::Rank::flushCmdList(), getElapsedTimeMicro(), getElapsedTimeNano(), Queue< WriteQueueEntry >::getNext(), BaseCache::getNextQueueEntry(), Prefetcher::Multi::getPacket(), PowerState::getWeights(), Stats::Global::Global(), MipsISA::haltThread(), MipsISA::handleLockedWrite(), RiscvISA::handleLockedWrite(), Checker< O3CPUImpl >::handlePendingInt(), MemTraceProbe::handleRequest(), DmaPort::handleResp(), SimpleCache::handleResponse(), MSHR::handleSnoop(), X86ISA::GpuTLB::handleTranslationReturn(), OutputUnit::has_credit(), OutputUnit::has_free_vc(), RubyPort::MemResponsePort::hitCallback(), RubyDirectedTester::hitCallback(), TraceCPU::icacheRetryRecvd(), NetworkInterface::incrementStats(), ComputeUnit::injectGlobalMemFence(), Prefetcher::Queued::insert(), CacheBlk::insert(), BaseTags::insertBlock(), Prefetcher::BOP::insertIntoDelayQueue(), GPUComputeDriver::ioctl(), Minor::Execute::issue(), LocalMemPipeline::issueRequest(), VIPERCoalescer::issueRequest(), GlobalMemPipeline::issueRequest(), Sequencer::issueRequest(), X86ISA::GpuTLB::issueTLBLookup(), EtherSwitch::Interface::learnSenderAddr(), BaseRemoteGDB::listen(), QoS::MemCtrl::logRequest(), QoS::MemCtrl::logResponse(), EtherSwitch::Interface::lookupDestPort(), UFSHostDevice::LUNSignal(), PseudoInst::m5checkpoint(), PseudoInst::m5exit(), PseudoInst::m5fail(), SMMUTranslationProcess::main(), GPUCoalescer::makeRequest(), RubySystem::memWriteback(), DRAMInterface::minBankPrep(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), TraceCPU::FixedRetryGen::nextExecute(), RandomGen::nextPacketTick(), LinearGen::nextPacketTick(), HybridGen::nextPacketTick(), TraceGen::nextPacketTick(), Shader::notifyCuSleep(), Prefetcher::SBOOE::notifyFill(), GPUDispatcher::notifyWgCompl(), BaseXBar::Layer< RequestPort, ResponsePort >::occupyLayer(), FreeBSD::onUDelay(), Linux::onUDelay(), Linux::openSpecialFile(), DistIface::packetOut(), ArmISA::TableWalker::pendingChange(), DVFSHandler::perfLevel(), Stats::periodicStatDump(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), DistIface::RecvScheduler::popPacket(), IGbE::postInterrupt(), BaseSimpleCPU::preExecute(), Stats::AvgStor::prepare(), Stats::AvgSampleStor::prepare(), Trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), Trace::TarmacTracerRecord::TraceInstEntry::print(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::print(), Trace::TarmacTracerRecord::TraceRegEntry::print(), Trace::TarmacTracerRecordV8::TraceMemEntryV8::print(), Trace::TarmacTracerRecord::TraceMemEntry::print(), Trace::TarmacParserRecord::printMismatchHeader(), MC146818::RTCEvent::process(), GlobalSimLoopExitEvent::process(), MC146818::RTCTickEvent::process(), CPUProgressEvent::process(), ArmISA::DumpStats::process(), Stats::StatEvent::process(), GlobalSyncEvent::process(), DistIface::SyncEvent::process(), DRAMInterface::Rank::processActivateEvent(), HelloObject::processEvent(), Uart8250::processIntrEvent(), ComputeUnit::DataPort::processMemRespEvent(), QoS::MemSinkCtrl::processNextReqEvent(), MemCtrl::processNextReqEvent(), DRAMInterface::Rank::processPowerEvent(), DRAMInterface::Rank::processPrechargeEvent(), TLBCoalescer::processProbeTLBEvent(), NVMInterface::processReadReadyEvent(), DRAMInterface::Rank::processRefreshEvent(), MemCtrl::processRespondEvent(), EtherLink::Link::processTxQueue(), DRAMInterface::Rank::processWakeUpEvent(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkAArch64(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), NVMInterface::processWriteRespondEvent(), MSHR::promoteDeferredTargets(), MemCtrl::pruneBurstTick(), MemChecker::ByteTracker::pruneTransactions(), EtherSwitch::Interface::PortFifo::push(), PowerDomain::pwrStateChangeCallback(), pybind_init_core(), QoS::MemCtrl::qosSchedule(), PseudoInst::quiesceNs(), PL031::read(), Sp804::Timer::read(), A9GlobalTimer::Timer::read(), CpuLocalTimer::Timer::read(), RealViewCtrl::read(), LSQUnit< Impl >::read(), UFSHostDevice::readCallback(), DRAMSim2::readComplete(), Pl111::readFramebuffer(), CheckerCPU::readMem(), X86ISA::Interrupts::readReg(), ElasticTrace::recordExecTick(), Sequencer::recordMissLatency(), ElasticTrace::recordToCommTick(), BaseCache::recvAtomic(), TLBCoalescer::MemSidePort::recvReqRetry(), StubSlavePort::recvTimingReq(), SimpleTimingPort::recvTimingReq(), RubyPort::MemResponsePort::recvTimingReq(), MemDelay::ResponsePort::recvTimingReq(), TLBCoalescer::CpuSidePort::recvTimingReq(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), SimpleMemory::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), QoS::MemSinkCtrl::recvTimingReq(), CommMonitor::recvTimingReq(), MemCtrl::recvTimingReq(), RubyPort::MemRequestPort::recvTimingResp(), MemDelay::RequestPort::recvTimingResp(), BaseTrafficGen::recvTimingResp(), RubyPort::PioRequestPort::recvTimingResp(), NoncoherentXBar::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), CommMonitor::recvTimingResp(), X86ISA::GpuTLB::MemSidePort::recvTimingResp(), CoherentXBar::recvTimingResp(), BaseCache::recvTimingResp(), ComputeUnit::DataPort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), MemDelay::ResponsePort::recvTimingSnoopResp(), CoherentXBar::recvTimingSnoopResp(), ElasticTrace::regEtraceListeners(), ElasticTrace::regProbeListeners(), UFSHostDevice::requestHandler(), BankedArray::reserve(), BIPRP::reset(), WeightedLRUPolicy::reset(), LRURP::reset(), MRURP::reset(), FIFORP::reset(), Stats::AvgStor::reset(), Clocked::resetClock(), PseudoInst::resetstats(), DRAMInterface::Rank::resetStats(), DRAMInterface::DRAMStats::resetStats(), DRAMInterface::respondEvent(), Sp804::Timer::restartCounter(), Sp805::restartCounter(), A9GlobalTimer::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), MipsISA::restoreThread(), Stats::AvgStor::result(), BasePixelPump::PixelEvent::resume(), DistIface::RecvScheduler::resumeRecvTicks(), SMMUTranslationProcess::resumeTransaction(), PL031::resyncMatch(), EtherTapBase::retransmit(), BaseTrafficGen::retryReq(), PseudoInst::rpns(), HTMSequencer::rubyHtmCallback(), StatTest::run(), DistIface::SyncNode::run(), DistIface::SyncSwitch::run(), Sinic::Device::rxKick(), NSGigE::rxKick(), CommMonitor::samplePeriodic(), HSAPacketProcessor::schedAQLProcessing(), TraceCPU::schedIcacheNext(), schedRelBreak(), PacketQueue::schedSendEvent(), PacketQueue::schedSendTiming(), Shader::ScheduleAdd(), GPUDispatcher::scheduleDispatch(), MC146818::RTCEvent::scheduleIntr(), Uart8250::scheduleIntr(), NetworkInterface::scheduleOutputPort(), DRAMInterface::Rank::schedulePowerEvent(), InstructionQueue< Impl >::scheduleReadyInsts(), BaseTrafficGen::scheduleUpdate(), DRAMInterface::Rank::scheduleWakeUpEvent(), HWScheduler::schedWakeup(), OutputUnit::select_free_vc(), Iris::ThreadContext::semihostingEvent(), EtherBus::send(), SwitchAllocator::send_allowed(), X86ISA::IntRequestPort< X86ISA::I82094AA >::sendMessage(), ComputeUnit::sendRequest(), DRAMSim2::sendResponse(), DRAMsim3::sendResponse(), EtherTapBase::sendSimulated(), Globals::serialize(), MC146818::serialize(), Intel8254Timer::Counter::serialize(), Sinic::Device::serialize(), NSGigE::serialize(), PowerState::set(), Stats::AvgStor::set(), Request::setAccessLatency(), CheckpointIn::setDir(), Pl011::setInterrupts(), CacheMemory::setMRU(), X86ISA::Interrupts::setReg(), Wavefront::setStatus(), Intel8254Timer::Counter::CounterEvent::setTo(), Request::setTranslateLatency(), Request::setVirt(), Event::setWhen(), simulate(), SMMUTranslationProcess::smmuTranslation(), DefaultRename< Impl >::sortInsts(), DistIface::SyncEvent::start(), IdeDisk::startDma(), sc_gem5::Kernel::startup(), CommMonitor::startup(), BaseKvmCPU::startup(), RubySystem::startup(), MC146818::startup(), ThermalModel::startup(), Intel8254Timer::Counter::startup(), DRAMSim2::startup(), DRAMsim3::startup(), DRAMInterface::Rank::startup(), MemCtrl::startup(), DRAMInterface::startup(), Stats::statElapsedTicks(), Stats::statFinalTick(), StoreTrace::store(), O3ThreadContext< Impl >::suspend(), SimpleThread::suspend(), BasePixelPump::PixelEvent::suspend(), takeCheckpoint(), CacheMemory::testCacheAccess(), GarnetSyntheticTraffic::tick(), AtomicSimpleCPU::tick(), IGbE::tick(), DRAMSim2::tick(), DRAMsim3::tick(), BaseKvmCPU::tick(), timesFunc(), Root::timeSync(), Root::timeSyncEnable(), WeightedLRUPolicy::touch(), LRURP::touch(), MRURP::touch(), BaseCPU::traceFunctionsInternal(), Trace::InstPBTrace::traceInst(), BaseTrafficGen::transition(), Prefetcher::Queued::translationComplete(), X86ISA::GpuTLB::translationReturn(), EtherLink::Link::transmit(), DistEtherLink::TxLink::transmit(), EtherSwitch::Interface::transmit(), NSGigE::transmit(), BankedArray::tryAccess(), CacheMemory::tryCacheAccess(), SerialLink::SerialLinkResponsePort::trySendTiming(), Bridge::BridgeResponsePort::trySendTiming(), SerialLink::SerialLinkRequestPort::trySendTiming(), Bridge::BridgeRequestPort::trySendTiming(), EtherLink::Link::txDone(), Sinic::Device::txKick(), NSGigE::txKick(), Sinic::Device::unserialize(), NSGigE::unserialize(), Clocked::update(), BaseTrafficGen::update(), ElasticTrace::updateCommitOrderDep(), Stats::updateEvents(), DefaultIEW< Impl >::updateExeInstStats(), VGic::updateIntState(), GicV2::updateIntState(), GPUDispatcher::updateInvCounter(), ElasticTrace::updateIssueOrderDep(), X86ISA::GpuTLB::updatePageFootprint(), TLBCoalescer::updatePhysAddresses(), DRAMInterface::Rank::updatePowerStats(), CommMonitor::MonitorStats::updateReqStats(), SystemCounter::updateTick(), SystemCounter::updateValue(), Checker< O3CPUImpl >::validateExecution(), Checker< O3CPUImpl >::validateInst(), Checker< O3CPUImpl >::validateState(), Checker< O3CPUImpl >::verify(), HDLcd::virtRefresh(), CrossbarSwitch::wakeup(), InputUnit::wakeup(), OutputUnit::wakeup(), NetworkLink::wakeup(), NetworkBridge::wakeup(), NetworkInterface::wakeup(), Router::wakeup(), RubyDirectedTester::wakeup(), RubyTester::wakeup(), GPUCoalescer::wakeup(), ArmISA::TableWalker::walk(), SystemCounter::whenValue(), System::workItemBegin(), System::workItemEnd(), Uart8250::write(), PL031::write(), EnergyCtrl::write(), UFSHostDevice::write(), IGbE::DescCache< iGbReg::RxDesc >::writeback(), IGbE::DescCache< iGbReg::RxDesc >::writeback1(), LSQUnit< Impl >::writebackStores(), DRAMSim2::writeComplete(), MC146818::writeData(), UFSHostDevice::writeDevice(), CheckerCPU::writeMem(), and MipsISA::yieldThread().
| void doExitCleanup | ( | ) |
Do C++ simulator exit processing.
Exported to Python to be invoked when simulator terminates via Python's atexit mechanism.
Definition at line 150 of file core.cc.
References exitCallbacks(), and CallbackQueue::process().
Referenced by pybind_init_core().
| void fixClockFrequency | ( | ) |
Definition at line 81 of file core.cc.
References cprintf(), SimClock::Frequency, SimClock::Float::GHz, SimClock::Float::Hz, SimClock::Float::kHz, SimClock::Float::MHz, SimClock::Int::ms, SimClock::Int::ns, SimClock::Int::ps, SimClock::Int::s, and SimClock::Int::us.
Referenced by sc_core::sc_time::from_value(), and pybind_init_core().
| Tick getClockFrequency | ( | ) |
Definition at line 118 of file core.cc.
Referenced by pybind_init_core().
| void registerExitCallback | ( | const std::function< void()> & | callback | ) |
| void setClockFrequency | ( | Tick | ticksPerSecond | ) |
Definition at line 112 of file core.cc.
References panic_if.
Referenced by pybind_init_core(), and sc_core::sc_set_time_resolution().
| void setOutputDir | ( | const std::string & | dir | ) |