gem5  v20.1.0.0
device.hh
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40 
41 /* @file
42  * Interface for devices using PCI configuration
43  */
44 
45 #ifndef __DEV_PCI_DEVICE_HH__
46 #define __DEV_PCI_DEVICE_HH__
47 
48 #include <cstring>
49 #include <vector>
50 
51 #include "dev/dma_device.hh"
52 #include "dev/pci/host.hh"
53 #include "dev/pci/pcireg.h"
54 #include "params/PciDevice.hh"
55 #include "sim/byteswap.hh"
56 
57 #define BAR_IO_MASK 0x3
58 #define BAR_MEM_MASK 0xF
59 #define BAR_IO_SPACE_BIT 0x1
60 #define BAR_IO_SPACE(x) ((x) & BAR_IO_SPACE_BIT)
61 #define BAR_NUMBER(x) (((x) - PCI0_BASE_ADDR0) >> 0x2);
62 
66 class PciDevice : public DmaDevice
67 {
68  protected:
70 
73 
77  const int PMCAP_BASE;
78  const int PMCAP_ID_OFFSET;
79  const int PMCAP_PC_OFFSET;
80  const int PMCAP_PMCS_OFFSET;
82 
83  const int MSICAP_BASE;
85 
86  const int MSIXCAP_BASE;
87  const int MSIXCAP_ID_OFFSET;
88  const int MSIXCAP_MXC_OFFSET;
96 
97  const int PXCAP_BASE;
104 
106  uint32_t BARSize[6];
107 
110 
112  bool legacyIO[6];
113 
117  bool
118  isLargeBAR(int bar) const
119  {
120  return bits(config.baseAddr[bar], 2, 1) == 0x2;
121  }
122 
127  bool
128  isBAR(Addr addr, int bar) const
129  {
130  assert(bar >= 0 && bar < 6);
131  return BARAddrs[bar] <= addr && addr < BARAddrs[bar] + BARSize[bar];
132  }
133 
138  int
140  {
141  for (int i = 0; i <= 5; ++i)
142  if (isBAR(addr, i))
143  return i;
144 
145  return -1;
146  }
147 
157  bool
158  getBAR(Addr addr, int &bar, Addr &offs)
159  {
160  int b = getBAR(addr);
161  if (b < 0)
162  return false;
163 
164  offs = addr - BARAddrs[b];
165  bar = b;
166  return true;
167  }
168 
169  public: // Host configuration interface
176  virtual Tick writeConfig(PacketPtr pkt);
177 
178 
185  virtual Tick readConfig(PacketPtr pkt);
186 
187  protected:
189 
192 
193  public:
194  Addr pciToDma(Addr pci_addr) const {
195  return hostInterface.dmaAddr(pci_addr);
196  }
197 
200 
201  uint8_t interruptLine() const { return letoh(config.interruptLine); }
202 
208  AddrRangeList getAddrRanges() const override;
209 
215  PciDevice(const PciDeviceParams *params);
216 
221  void serialize(CheckpointOut &cp) const override;
222 
228  void unserialize(CheckpointIn &cp) override;
229 
230  const PciBusAddr &busAddr() const { return _busAddr; }
231 };
232 #endif // __DEV_PCI_DEVICE_HH__
PciDevice::getAddrRanges
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
Definition: device.cc:273
PciDevice::MSICAP_BASE
const int MSICAP_BASE
Definition: device.hh:83
PciHost::DeviceInterface::postInt
void postInt()
Post a PCI interrupt to the CPU.
Definition: host.cc:102
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
PciDevice::writeConfig
virtual Tick writeConfig(PacketPtr pkt)
Write to the PCI config space data that is stored locally.
Definition: device.cc:284
PciDevice::PMCAP_PC_OFFSET
const int PMCAP_PC_OFFSET
Definition: device.hh:79
PCIConfig
Definition: pcireg.h:53
PciDevice::readConfig
virtual Tick readConfig(PacketPtr pkt)
Read from the PCI config space data that is stored locally.
Definition: device.cc:216
PciHost::DeviceInterface
Callback interface from PCI devices to the host.
Definition: host.hh:91
PciDevice::interruptLine
uint8_t interruptLine() const
Definition: device.hh:201
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
PciDevice::pxcap
PXCAP pxcap
Definition: device.hh:98
PciDevice::config
PCIConfig config
The current config space.
Definition: device.hh:72
PciDevice::_busAddr
const PciBusAddr _busAddr
Definition: device.hh:69
std::vector< MSIXTable >
PciDevice::intrClear
void intrClear()
Definition: device.hh:199
PciDevice::msixcap
MSIXCAP msixcap
Definition: device.hh:95
PCIConfig::interruptLine
uint8_t interruptLine
Definition: pcireg.h:79
PciDevice::msix_pba
std::vector< MSIXPbaEntry > msix_pba
Definition: device.hh:103
PciDevice::MSIXCAP_MTAB_OFFSET
const int MSIXCAP_MTAB_OFFSET
Definition: device.hh:89
PciDevice::PMCAP_PMCS_OFFSET
const int PMCAP_PMCS_OFFSET
Definition: device.hh:80
letoh
T letoh(T value)
Definition: byteswap.hh:141
PciDevice::PciDevice
PciDevice(const PciDeviceParams *params)
Constructor for PCI Dev.
Definition: device.cc:62
PciDevice::hostInterface
PciHost::DeviceInterface hostInterface
Definition: device.hh:188
cp
Definition: cprintf.cc:40
dma_device.hh
PciDevice::BARSize
uint32_t BARSize[6]
The size of the BARs.
Definition: device.hh:106
PciHost::DeviceInterface::clearInt
void clearInt()
Clear a posted PCI interrupt.
Definition: host.cc:110
PciBusAddr
Definition: types.hh:41
PciDevice::busAddr
const PciBusAddr & busAddr() const
Definition: device.hh:230
PciDevice::isBAR
bool isBAR(Addr addr, int bar) const
Does the given address lie within the space mapped by the given base address register?
Definition: device.hh:128
PMCAP
Definition: pcireg.h:205
PciDevice::msicap
MSICAP msicap
Definition: device.hh:84
PciDevice::MSIX_TABLE_OFFSET
int MSIX_TABLE_OFFSET
Definition: device.hh:91
PciDevice::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: device.cc:442
PciDevice::PMCAP_BASE
const int PMCAP_BASE
The capability list structures and base addresses.
Definition: device.hh:77
PciDevice::MSIXCAP_BASE
const int MSIXCAP_BASE
Definition: device.hh:86
PCIConfig::baseAddr
uint32_t baseAddr[6]
Definition: pcireg.h:69
PciDevice::MSIX_TABLE_END
int MSIX_TABLE_END
Definition: device.hh:92
PXCAP
Definition: pcireg.h:304
pcireg.h
PciDevice::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: device.cc:507
PciDevice::isLargeBAR
bool isLargeBAR(int bar) const
Does the given BAR represent 32 lower bits of a 64-bit address?
Definition: device.hh:118
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
PciDevice::MSIXCAP_MXC_OFFSET
const int MSIXCAP_MXC_OFFSET
Definition: device.hh:88
host.hh
PciDevice::configDelay
Tick configDelay
Definition: device.hh:191
MSIXCAP
Definition: pcireg.h:265
DmaDevice
Definition: dma_device.hh:165
PciDevice::msix_table
std::vector< MSIXTable > msix_table
MSIX Table and PBA Structures.
Definition: device.hh:102
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
MSICAP
Definition: pcireg.h:238
PioDevice::params
const Params * params() const
Definition: io_device.hh:136
PciDevice::PXCAP_BASE
const int PXCAP_BASE
Definition: device.hh:97
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
PciDevice::MSIX_PBA_OFFSET
int MSIX_PBA_OFFSET
Definition: device.hh:93
addr
ip6_addr_t addr
Definition: inet.hh:423
PciDevice::pmcap
PMCAP pmcap
Definition: device.hh:81
PciDevice::pioDelay
Tick pioDelay
Definition: device.hh:190
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
PciDevice::intrPost
void intrPost()
Definition: device.hh:198
PciDevice::MSIXCAP_MPBA_OFFSET
const int MSIXCAP_MPBA_OFFSET
Definition: device.hh:90
std::list< AddrRange >
PciDevice::PMCAP_ID_OFFSET
const int PMCAP_ID_OFFSET
Definition: device.hh:78
PciDevice::MSIX_PBA_END
int MSIX_PBA_END
Definition: device.hh:94
PciDevice::BARAddrs
Addr BARAddrs[6]
The current address mapping of the BARs.
Definition: device.hh:109
CheckpointIn
Definition: serialize.hh:67
PciDevice::MSIXCAP_ID_OFFSET
const int MSIXCAP_ID_OFFSET
Definition: device.hh:87
PciDevice::getBAR
int getBAR(Addr addr)
Which base address register (if any) maps the given address?
Definition: device.hh:139
PciDevice::legacyIO
bool legacyIO[6]
Whether the BARs are really hardwired legacy IO locations.
Definition: device.hh:112
PciHost::DeviceInterface::dmaAddr
Addr dmaAddr(Addr addr) const
Calculate the physical address of a prefetchable memory location in the PCI address space.
Definition: host.hh:146
PciDevice
PCI device, base implementation is only config space.
Definition: device.hh:66
PciDevice::getBAR
bool getBAR(Addr addr, int &bar, Addr &offs)
Which base address register (if any) maps the given address?
Definition: device.hh:158
PciDevice::pciToDma
Addr pciToDma(Addr pci_addr) const
Definition: device.hh:194
byteswap.hh
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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