Go to the documentation of this file.
44 #ifndef __CPU_TRAFFIC_GEN_DRAM_GEN_HH__
45 #define __CPU_TRAFFIC_GEN_DRAM_GEN_HH__
49 #include "enums/AddrMap.hh"
88 Addr _blocksize,
Addr cacheline_size,
90 uint8_t read_percent,
Addr data_limit,
91 unsigned int num_seq_pkts,
unsigned int page_size,
92 unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
93 Enums::AddrMap addr_mapping,
94 unsigned int nbr_of_ranks);
104 void genStartAddr(
unsigned int new_bank ,
unsigned int new_rank);
const unsigned int nbrOfBanksDRAM
Number of banks in DRAM.
PacketPtr getNextPacket()
Get the next generated packet.
const unsigned int numSeqPkts
Number of sequential DRAM packets to be generated per cpu request.
uint64_t Tick
Tick count type.
DRAM specific generator is for issuing request with variable page hit length and bank utilization.
unsigned int countNumSeqPkts
Track number of sequential packets generated for a request
const unsigned int blockBits
Number of block bits in DRAM address.
const unsigned int rankBits
Number of rank bits in DRAM address.
const unsigned int bankBits
Number of bank bits in DRAM address.
const unsigned int pageBits
Number of page bits in DRAM address.
void genStartAddr(unsigned int new_bank, unsigned int new_rank)
Insert bank, rank, and column bits into packed address to create address for 1st command in a series.
const unsigned int nbrOfRanks
Number of ranks to be utilized for a given configuration.
Addr addr
Address of request.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
DramGen(SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, Enums::AddrMap addr_mapping, unsigned int nbr_of_ranks)
Create a DRAM address sequence generator.
The random generator is similar to the linear one, but does not generate sequential addresses.
bool isRead
Remember type of requests to be generated in series.
const unsigned int nbrOfBanksUtil
Number of banks to be utilized for a given configuration.
const unsigned int pageSize
Page size of DRAM.
Enums::AddrMap addrMapping
Address mapping to be used.
Abstract superclass for simulation objects.
Generated on Wed Sep 30 2020 14:02:09 for gem5 by doxygen 1.8.17