gem5  v20.1.0.0
dram_gen.cc
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37 
38 #include "cpu/testers/traffic_gen/dram_gen.hh"
39 
40 #include <algorithm>
41 
42 #include "base/random.hh"
43 #include "base/trace.hh"
44 #include "debug/TrafficGen.hh"
45 #include "enums/AddrMap.hh"
46 
47 DramGen::DramGen(SimObject &obj,
48  RequestorID requestor_id, Tick _duration,
49  Addr start_addr, Addr end_addr,
50  Addr _blocksize, Addr cacheline_size,
51  Tick min_period, Tick max_period,
52  uint8_t read_percent, Addr data_limit,
53  unsigned int num_seq_pkts, unsigned int page_size,
54  unsigned int nbr_of_banks_DRAM,
55  unsigned int nbr_of_banks_util,
56  Enums::AddrMap addr_mapping,
57  unsigned int nbr_of_ranks)
58  : RandomGen(obj, requestor_id, _duration, start_addr, end_addr,
59  _blocksize, cacheline_size, min_period, max_period,
60  read_percent, data_limit),
61  numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
62  isRead(true), pageSize(page_size),
63  pageBits(floorLog2(page_size / _blocksize)),
64  bankBits(floorLog2(nbr_of_banks_DRAM)),
65  blockBits(floorLog2(_blocksize)),
66  nbrOfBanksDRAM(nbr_of_banks_DRAM),
67  nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping),
68  rankBits(floorLog2(nbr_of_ranks)),
69  nbrOfRanks(nbr_of_ranks)
70 {
71  if (nbr_of_banks_util > nbr_of_banks_DRAM)
72  fatal("Attempting to use more banks (%d) than "
73  "what is available (%d)\n",
74  nbr_of_banks_util, nbr_of_banks_DRAM);
75 }
76 
77 PacketPtr
78 DramGen::getNextPacket()
79 {
80  // if this is the first of the packets in series to be generated,
81  // start counting again
82  if (countNumSeqPkts == 0) {
83  countNumSeqPkts = numSeqPkts;
84 
85  // choose if we generate a read or a write here
86  isRead = readPercent != 0 &&
87  (readPercent == 100 || random_mt.random(0, 100) < readPercent);
88 
89  assert((readPercent == 0 && !isRead) ||
90  (readPercent == 100 && isRead) ||
91  readPercent != 100);
92 
93  // pick a random bank
94  unsigned int new_bank =
95  random_mt.random<unsigned int>(0, nbrOfBanksUtil - 1);
96 
97  // pick a random rank
98  unsigned int new_rank =
99  random_mt.random<unsigned int>(0, nbrOfRanks - 1);
100 
101  // Generate the start address of the command series
102  // routine will update addr variable with bank, rank, and col
103  // bits updated for random traffic mode
104  genStartAddr(new_bank, new_rank);
105 
106  } else {
107  // increment the column by one
108  if (addrMapping == Enums::RoRaBaCoCh ||
109  addrMapping == Enums::RoRaBaChCo)
110  // Simply increment addr by blocksize to increment
111  // the column by one
112  addr += blocksize;
113 
114  else if (addrMapping == Enums::RoCoRaBaCh) {
115  // Explicity increment the column bits
116  unsigned int new_col = ((addr / blocksize /
117  nbrOfBanksDRAM / nbrOfRanks) %
118  (pageSize / blocksize)) + 1;
119  replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
120  blockBits + bankBits + rankBits, new_col);
121  }
122  }
123 
124  DPRINTF(TrafficGen, "DramGen::getNextPacket: %c to addr %x, "
125  "size %d, countNumSeqPkts: %d, numSeqPkts: %d\n",
126  isRead ? 'r' : 'w', addr, blocksize, countNumSeqPkts, numSeqPkts);
127 
128  // create a new request packet
129  PacketPtr pkt = getPacket(addr, blocksize,
130  isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
131 
132  // add the amount of data manipulated to the total
133  dataManipulated += blocksize;
134 
135  // subtract the number of packets remained to be generated
136  --countNumSeqPkts;
137 
138  // return the generated packet
139  return pkt;
140 }
141 
142 void
143 DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
144 {
145  // start by picking a random address in the range
146  addr = random_mt.random<Addr>(startAddr, endAddr - 1);
147 
148  // round down to start address of a block, i.e. a DRAM burst
149  addr -= addr % blocksize;
150 
151  // insert the bank bits at the right spot, and align the
152  // address to achieve the required hit length, this involves
153  // finding the appropriate start address such that all
154  // sequential packets target successive columns in the same
155  // page
156 
157  // for example, if we have a stride size of 192B, which means
158  // for LPDDR3 where burstsize = 32B we have numSeqPkts = 6,
159  // the address generated previously can be such that these
160  // 192B cross the page boundary, hence it needs to be aligned
161  // so that they all belong to the same page for page hit
162  unsigned int columns_per_page = pageSize / blocksize;
163 
164  // pick a random column, but ensure that there is room for
165  // numSeqPkts sequential columns in the same page
166  unsigned int new_col =
167  random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
168 
169  if (addrMapping == Enums::RoRaBaCoCh ||
170  addrMapping == Enums::RoRaBaChCo) {
171  // Block bits, then page bits, then bank bits, then rank bits
172  replaceBits(addr, blockBits + pageBits + bankBits - 1,
173  blockBits + pageBits, new_bank);
174  replaceBits(addr, blockBits + pageBits - 1, blockBits, new_col);
175  if (rankBits != 0) {
176  replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
177  blockBits + pageBits + bankBits, new_rank);
178  }
179  } else if (addrMapping == Enums::RoCoRaBaCh) {
180  // Block bits, then bank bits, then rank bits, then page bits
181  replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
182  replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,
183  blockBits + bankBits + rankBits, new_col);
184  if (rankBits != 0) {
185  replaceBits(addr, blockBits + bankBits + rankBits - 1,
186  blockBits + bankBits, new_rank);
187  }
188  }
189 }
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:183
replaceBits
void replaceBits(T &val, int first, int last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:179
DramGen::nbrOfBanksDRAM
const unsigned int nbrOfBanksDRAM
Number of banks in DRAM.
Definition: dram_gen.hh:133
dram_gen.hh
DramGen::getNextPacket
PacketPtr getNextPacket()
Get the next generated packet.
Definition: dram_gen.cc:78
random.hh
DramGen::numSeqPkts
const unsigned int numSeqPkts
Number of sequential DRAM packets to be generated per cpu request.
Definition: dram_gen.hh:109
MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:82
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
DramGen::countNumSeqPkts
unsigned int countNumSeqPkts
Track number of sequential packets generated for a request
Definition: dram_gen.hh:112
DramGen::blockBits
const unsigned int blockBits
Number of block bits in DRAM address.
Definition: dram_gen.hh:130
DramGen::rankBits
const unsigned int rankBits
Number of rank bits in DRAM address.
Definition: dram_gen.hh:142
floorLog2
std::enable_if< std::is_integral< T >::value, int >::type floorLog2(T x)
Definition: intmath.hh:63
DramGen::bankBits
const unsigned int bankBits
Number of bank bits in DRAM address.
Definition: dram_gen.hh:127
StochasticGen::readPercent
const uint8_t readPercent
Percent of generated transactions that should be reads.
Definition: base_gen.hh:162
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:85
random_mt
Random random_mt
Definition: random.cc:96
RequestorID
uint16_t RequestorID
Definition: request.hh:85
DramGen::pageBits
const unsigned int pageBits
Number of page bits in DRAM address.
Definition: dram_gen.hh:124
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
DramGen::genStartAddr
void genStartAddr(unsigned int new_bank, unsigned int new_rank)
Insert bank, rank, and column bits into packed address to create address for 1st command in a series.
Definition: dram_gen.cc:143
DramGen::nbrOfRanks
const unsigned int nbrOfRanks
Number of ranks to be utilized for a given configuration.
Definition: dram_gen.hh:145
DramGen::addr
Addr addr
Address of request.
Definition: dram_gen.hh:115
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
BaseGen::getPacket
PacketPtr getPacket(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
Generate a new request and associated packet.
Definition: base_gen.cc:56
RandomGen::dataManipulated
Addr dataManipulated
Counter to determine the amount of data manipulated.
Definition: random_gen.hh:103
StochasticGen::blocksize
const Addr blocksize
Blocksize and address increment.
Definition: base_gen.hh:150
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
addr
ip6_addr_t addr
Definition: inet.hh:423
DramGen::DramGen
DramGen(SimObject &obj, RequestorID requestor_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, Enums::AddrMap addr_mapping, unsigned int nbr_of_ranks)
Create a DRAM address sequence generator.
Definition: dram_gen.cc:47
Random::random
std::enable_if< std::is_integral< T >::value, T >::type random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:86
RandomGen
The random generator is similar to the linear one, but does not generate sequential addresses.
Definition: random_gen.hh:57
trace.hh
StochasticGen::endAddr
const Addr endAddr
End of address range.
Definition: base_gen.hh:147
DramGen::isRead
bool isRead
Remember type of requests to be generated in series.
Definition: dram_gen.hh:118
DramGen::nbrOfBanksUtil
const unsigned int nbrOfBanksUtil
Number of banks to be utilized for a given configuration.
Definition: dram_gen.hh:136
TrafficGen
The traffic generator is a module that generates stimuli for the memory system, based on a collection...
Definition: traffic_gen.hh:67
StochasticGen::startAddr
const Addr startAddr
Start of address range.
Definition: base_gen.hh:144
DramGen::pageSize
const unsigned int pageSize
Page size of DRAM.
Definition: dram_gen.hh:121
DramGen::addrMapping
Enums::AddrMap addrMapping
Address mapping to be used.
Definition: dram_gen.hh:139
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:92
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