gem5
v20.1.0.0
arch
arm
isa_device.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2014,2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/arm/isa_device.hh
"
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#include "
base/logging.hh
"
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namespace
ArmISA
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{
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BaseISADevice::BaseISADevice
()
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: isa(nullptr)
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{
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}
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void
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BaseISADevice::setISA
(
ISA
*_isa)
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{
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assert(_isa);
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isa
= _isa;
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}
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void
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DummyISADevice::setMiscReg
(
int
misc_reg,
RegVal
val
)
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{
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warn
(
"Ignoring write of 0x%lx to miscreg %s\n"
,
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val
,
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miscRegName
[misc_reg]);
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}
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RegVal
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DummyISADevice::readMiscReg
(
int
misc_reg)
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{
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warn
(
"Returning zero for read from miscreg %s\n"
,
miscRegName
[misc_reg]);
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return
0;
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}
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}
isa_device.hh
warn
#define warn(...)
Definition:
logging.hh:239
ArmISA::BaseISADevice::BaseISADevice
BaseISADevice()
Definition:
isa_device.cc:45
ArmISA::BaseISADevice::isa
ISA * isa
Definition:
isa_device.hh:84
ArmISA::ISA
Definition:
isa.hh:65
ArmISA::DummyISADevice::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Write to a system register belonging to this device.
Definition:
isa_device.cc:59
ArmISA::miscRegName
const char *const miscRegName[]
Definition:
miscregs.hh:1159
ArmISA
Definition:
ccregs.hh:41
X86ISA::val
Bitfield< 63 > val
Definition:
misc.hh:769
logging.hh
ArmISA::BaseISADevice::setISA
virtual void setISA(ISA *isa)
Definition:
isa_device.cc:51
RegVal
uint64_t RegVal
Definition:
types.hh:168
ArmISA::DummyISADevice::readMiscReg
RegVal readMiscReg(int misc_reg) override
Read a system register belonging to this device.
Definition:
isa_device.cc:67
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