gem5
v20.1.0.0
arch
x86
insts
microfpop.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_INSTS_MICROFPOP_HH__
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#define __ARCH_X86_INSTS_MICROFPOP_HH__
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#include "
arch/x86/insts/microop.hh
"
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namespace
X86ISA
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{
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class
FpOp
:
public
X86MicroopBase
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{
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protected
:
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const
RegIndex
src1
;
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const
RegIndex
src2
;
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const
RegIndex
dest
;
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const
uint8_t
dataSize
;
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const
int8_t
spm
;
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// Constructor
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FpOp
(
ExtMachInst
_machInst,
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const
char
*mnem,
const
char
*_instMnem,
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uint64_t setFlags,
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InstRegIndex
_src1,
InstRegIndex
_src2,
InstRegIndex
_dest,
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uint8_t _dataSize, int8_t _spm,
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OpClass __opClass) :
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X86MicroopBase
(_machInst, mnem, _instMnem, setFlags,
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__opClass),
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src1
(_src1.
index
()),
src2
(_src2.
index
()),
dest
(_dest.
index
()),
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dataSize
(_dataSize),
spm
(_spm)
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{}
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/*
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//Figure out what the condition code flags should be.
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uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
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uint64_t _dest, uint64_t _src1, uint64_t _src2,
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bool subtract = false) const;
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bool checkCondition(uint64_t flags) const;*/
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std::string
generateDisassembly
(
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Addr
pc
,
const
Loader::SymbolTable
*symtab)
const override
;
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};
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}
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#endif //__ARCH_X86_INSTS_MICROFPOP_HH__
X86ISA::FpOp::dest
const RegIndex dest
Definition:
microfpop.hh:54
X86ISA::X86MicroopBase
Definition:
microop.hh:88
Loader::SymbolTable
Definition:
symtab.hh:59
microop.hh
X86ISA::InstRegIndex
Class for register indices passed to instruction constructors.
Definition:
static_inst.hh:52
X86ISA::FpOp::spm
const int8_t spm
Definition:
microfpop.hh:56
X86ISA::index
Bitfield< 5, 3 > index
Definition:
types.hh:93
StaticInst::ExtMachInst
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
Definition:
static_inst.hh:89
X86ISA
This is exposed globally, independent of the ISA.
Definition:
acpi.hh:55
X86ISA::FpOp::FpOp
FpOp(ExtMachInst _machInst, const char *mnem, const char *_instMnem, uint64_t setFlags, InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm, OpClass __opClass)
Definition:
microfpop.hh:59
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:142
X86ISA::FpOp::src2
const RegIndex src2
Definition:
microfpop.hh:53
X86ISA::FpOp::dataSize
const uint8_t dataSize
Definition:
microfpop.hh:55
RegIndex
uint16_t RegIndex
Definition:
types.hh:52
X86ISA::FpOp
Base classes for FpOps which provides a generateDisassembly method.
Definition:
microfpop.hh:49
X86ISA::FpOp::src1
const RegIndex src1
Definition:
microfpop.hh:52
X86ISA::FpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition:
microfpop.cc:55
X86ISA::pc
Bitfield< 19 > pc
Definition:
misc.hh:805
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