gem5  v20.1.0.0
static_inst.hh
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37 
38 #ifndef __ARCH_X86_INSTS_STATICINST_HH__
39 #define __ARCH_X86_INSTS_STATICINST_HH__
40 
41 #include "base/trace.hh"
42 #include "cpu/static_inst.hh"
43 #include "debug/X86.hh"
44 
45 namespace X86ISA
46 {
52  struct InstRegIndex : public RegId
53  {
54  explicit InstRegIndex(RegIndex _idx) :
55  RegId(computeRegClass(_idx), _idx) {}
56 
57  private:
58  // TODO: As X86 register index definition is highly built on the
59  // unified space concept, it is easier for the moment to rely on
60  // an helper function to compute the RegClass. It would be nice
61  // to fix those definition and get rid of this.
63  if (_idx < FP_Reg_Base) {
64  return IntRegClass;
65  } else if (_idx < CC_Reg_Base) {
66  return FloatRegClass;
67  } else if (_idx < Misc_Reg_Base) {
68  return CCRegClass;
69  } else {
70  return MiscRegClass;
71  }
72  }
73  };
74 
79  class X86StaticInst : public StaticInst
80  {
81  protected:
82  // Constructor.
83  X86StaticInst(const char *mnem,
84  ExtMachInst _machInst, OpClass __opClass)
85  : StaticInst(mnem, _machInst, __opClass)
86  {
87  }
88 
89  std::string generateDisassembly(
90  Addr pc, const Loader::SymbolTable *symtab) const override;
91 
92  void printMnemonic(std::ostream &os, const char * mnemonic) const;
93  void printMnemonic(std::ostream &os, const char * instMnemonic,
94  const char * mnemonic) const;
95 
96  void printSegment(std::ostream &os, int segment) const;
97 
98  void printReg(std::ostream &os, RegId reg, int size) const;
99  void printSrcReg(std::ostream &os, int reg, int size) const;
100  void printDestReg(std::ostream &os, int reg, int size) const;
101  void printMem(std::ostream &os, uint8_t segment,
102  uint8_t scale, RegIndex index, RegIndex base,
103  uint64_t disp, uint8_t addressSize, bool rip) const;
104 
105  inline uint64_t merge(uint64_t into, uint64_t val, int size) const
106  {
107  X86IntReg reg = into;
108  if (_destRegIdx[0].index() & IntFoldBit)
109  {
110  reg.H = val;
111  return reg;
112  }
113  switch(size)
114  {
115  case 1:
116  reg.L = val;
117  break;
118  case 2:
119  reg.X = val;
120  break;
121  case 4:
122  //XXX Check if this should be zeroed or sign extended
123  reg = 0;
124  reg.E = val;
125  break;
126  case 8:
127  reg.R = val;
128  break;
129  default:
130  panic("Tried to merge with unrecognized size %d.\n", size);
131  }
132  return reg;
133  }
134 
135  inline uint64_t pick(uint64_t from, int idx, int size) const
136  {
137  X86IntReg reg = from;
138  DPRINTF(X86, "Picking with size %d\n", size);
139  if (_srcRegIdx[idx].index() & IntFoldBit)
140  return reg.H;
141  switch(size)
142  {
143  case 1:
144  return reg.L;
145  case 2:
146  return reg.X;
147  case 4:
148  return reg.E;
149  case 8:
150  return reg.R;
151  default:
152  panic("Tried to pick with unrecognized size %d.\n", size);
153  }
154  }
155 
156  inline int64_t signedPick(uint64_t from, int idx, int size) const
157  {
158  X86IntReg reg = from;
159  DPRINTF(X86, "Picking with size %d\n", size);
160  if (_srcRegIdx[idx].index() & IntFoldBit)
161  return reg.SH;
162  switch(size)
163  {
164  case 1:
165  return reg.SL;
166  case 2:
167  return reg.SX;
168  case 4:
169  return reg.SE;
170  case 8:
171  return reg.SR;
172  default:
173  panic("Tried to pick with unrecognized size %d.\n", size);
174  }
175  }
176 
177  void
178  advancePC(PCState &pcState) const override
179  {
180  pcState.advance();
181  }
182  };
183 }
184 
185 #endif //__ARCH_X86_INSTS_STATICINST_HH__
X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:151
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:85
X86ISA::X86StaticInst::merge
uint64_t merge(uint64_t into, uint64_t val, int size) const
Definition: static_inst.hh:105
Loader::SymbolTable
Definition: symtab.hh:59
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
X86ISA::X86StaticInst::printDestReg
void printDestReg(std::ostream &os, int reg, int size) const
Definition: static_inst.cc:114
X86ISA::CC_Reg_Base
@ CC_Reg_Base
Definition: registers.hh:72
X86ISA::X86StaticInst::advancePC
void advancePC(PCState &pcState) const override
Definition: static_inst.hh:178
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
X86ISA::scale
scale
Definition: types.hh:92
X86ISA::X86StaticInst::printReg
void printReg(std::ostream &os, RegId reg, int size) const
Definition: static_inst.cc:121
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
X86ISA::FP_Reg_Base
@ FP_Reg_Base
Definition: registers.hh:71
X86ISA::InstRegIndex
Class for register indices passed to instruction constructors.
Definition: static_inst.hh:52
FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:54
X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:93
X86ISA::Misc_Reg_Base
@ Misc_Reg_Base
Definition: registers.hh:73
X86ISA::InstRegIndex::computeRegClass
RegClass computeRegClass(RegIndex _idx)
Definition: static_inst.hh:62
X86ISA::X86StaticInst::X86StaticInst
X86StaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:83
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
StaticInst::_srcRegIdx
RegId _srcRegIdx[MaxInstSrcRegs]
See srcRegIdx().
Definition: static_inst.hh:250
StaticInst::_destRegIdx
RegId _destRegIdx[MaxInstDestRegs]
See destRegIdx().
Definition: static_inst.hh:248
RegClass
RegClass
Enumerate the classes of registers.
Definition: reg_class.hh:52
X86ISA::X86StaticInst::printSegment
void printSegment(std::ostream &os, int segment) const
Definition: static_inst.cc:58
X86ISA::X86StaticInst::printMnemonic
void printMnemonic(std::ostream &os, const char *mnemonic) const
Definition: static_inst.cc:46
X86ISA::X86StaticInst::printMem
void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip) const
Definition: static_inst.cc:229
X86ISA::PCState
Definition: types.hh:287
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
static_inst.hh
StaticInst::ExtMachInst
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
Definition: static_inst.hh:89
X86ISA::InstRegIndex::InstRegIndex
InstRegIndex(RegIndex _idx)
Definition: static_inst.hh:54
X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:268
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:53
X86ISA::X86StaticInst
Base class for all X86 static instructions.
Definition: static_inst.hh:79
CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:60
X86ISA::PCState::advance
void advance()
Definition: types.hh:323
MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:61
X86ISA::X86StaticInst::pick
uint64_t pick(uint64_t from, int idx, int size) const
Definition: static_inst.hh:135
RegIndex
uint16_t RegIndex
Definition: types.hh:52
X86ISA::X86StaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg, int size) const
Definition: static_inst.cc:107
trace.hh
X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
X86ISA::X86StaticInst::signedPick
int64_t signedPick(uint64_t from, int idx, int size) const
Definition: static_inst.hh:156
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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