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38 #ifndef __ARCH_ARM_INSTS_MISC64_HH__
39 #define __ARCH_ARM_INSTS_MISC64_HH__
49 OpClass __opClass, uint64_t _imm) :
127 OpClass __opClass,
bool misc_read) :
137 uint32_t &immediate)
const;
141 uint32_t &immediate)
const;
145 uint32_t &immediate)
const;
220 uint32_t _imm,
const std::string full_mnem,
222 MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2, uint64_t _imm)
ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint64_t _imm)
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, bool misc_read)
MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, uint32_t _imm)
MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst, ArmISA::MiscRegIndex misc_reg, bool misc_read, uint32_t _imm, const std::string full_mnem, bool _warning)
RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, uint64_t _imm1, int64_t _imm2)
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::shared_ptr< FaultBase > Fault
RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::MiscRegIndex _op1, uint32_t _imm)
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
ArmISA::MiscRegIndex dest
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
RegNone(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest)
const std::string fullMnemonic
MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, ArmISA::IntRegIndex _op1, uint32_t _imm)
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, uint32_t immediate) const
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
const ArmISA::MiscRegIndex miscReg
ArmISA::MiscRegIndex dest
bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
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