gem5  v20.1.0.0
misc64.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_MISC64_HH__
39 #define __ARCH_ARM_INSTS_MISC64_HH__
40 
42 
44 {
45  protected:
46  uint64_t imm;
47 
48  ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
49  OpClass __opClass, uint64_t _imm) :
50  ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
51  {}
52 
53  std::string generateDisassembly(
54  Addr pc, const Loader::SymbolTable *symtab) const override;
55 };
56 
58 {
59  protected:
62  uint64_t imm1;
63  uint64_t imm2;
64 
65  RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
66  OpClass __opClass, ArmISA::IntRegIndex _dest,
67  ArmISA::IntRegIndex _op1, uint64_t _imm1,
68  int64_t _imm2) :
69  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
70  dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
71  {}
72 
73  std::string generateDisassembly(
74  Addr pc, const Loader::SymbolTable *symtab) const override;
75 };
76 
78 {
79  protected:
83  uint64_t imm;
84 
85  RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
86  OpClass __opClass, ArmISA::IntRegIndex _dest,
88  uint64_t _imm) :
89  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
90  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
91  {}
92 
93  std::string generateDisassembly(
94  Addr pc, const Loader::SymbolTable *symtab) const override;
95 };
96 
98 {
99  protected:
100 
101  UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
102  OpClass __opClass) :
103  ArmISA::ArmStaticInst(mnem, _machInst, __opClass)
104  {}
105 
106  std::string generateDisassembly(
107  Addr pc, const Loader::SymbolTable *symtab) const override;
108 };
109 
122 {
123  protected:
124  bool miscRead;
125 
126  MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
127  OpClass __opClass, bool misc_read) :
128  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
129  miscRead(misc_read)
130  {}
131 
133  ArmISA::ExceptionLevel el, uint32_t immediate) const;
134  private:
135  bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
137  uint32_t &immediate) const;
138 
139  bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
141  uint32_t &immediate) const;
142 
143  bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
145  uint32_t &immediate) const;
146 
147 };
148 
150 {
151  protected:
153  uint32_t imm;
154 
155  MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
156  OpClass __opClass, ArmISA::MiscRegIndex _dest,
157  uint32_t _imm) :
158  MiscRegOp64(mnem, _machInst, __opClass, false),
159  dest(_dest), imm(_imm)
160  {}
161 
167  RegVal miscRegImm() const;
168 
169  std::string generateDisassembly(
170  Addr pc, const Loader::SymbolTable *symtab) const override;
171 };
172 
174 {
175  protected:
178  uint32_t imm;
179 
180  MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
181  OpClass __opClass, ArmISA::MiscRegIndex _dest,
182  ArmISA::IntRegIndex _op1, uint32_t _imm) :
183  MiscRegOp64(mnem, _machInst, __opClass, false),
184  dest(_dest), op1(_op1), imm(_imm)
185  {}
186 
187  std::string generateDisassembly(
188  Addr pc, const Loader::SymbolTable *symtab) const override;
189 };
190 
192 {
193  protected:
196  uint32_t imm;
197 
198  RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
199  OpClass __opClass, ArmISA::IntRegIndex _dest,
200  ArmISA::MiscRegIndex _op1, uint32_t _imm) :
201  MiscRegOp64(mnem, _machInst, __opClass, true),
202  dest(_dest), op1(_op1), imm(_imm)
203  {}
204 
205  std::string generateDisassembly(
206  Addr pc, const Loader::SymbolTable *symtab) const override;
207 };
208 
210 {
211  protected:
212  const std::string fullMnemonic;
214  const uint32_t imm;
215  const bool warning;
216 
217  public:
218  MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst,
219  ArmISA::MiscRegIndex misc_reg, bool misc_read,
220  uint32_t _imm, const std::string full_mnem,
221  bool _warning) :
222  MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
223  fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
224  warning(_warning)
225  {
227  }
228 
229  protected:
231  Trace::InstRecord *traceData) const override;
232 
233  std::string generateDisassembly(
234  Addr pc, const Loader::SymbolTable *symtab) const override;
235 };
236 
238 {
239  protected:
241 
242  RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
243  OpClass __opClass, ArmISA::IntRegIndex _dest) :
244  ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
245  dest(_dest)
246  {}
247 
248  std::string generateDisassembly(
249  Addr pc, const Loader::SymbolTable *symtab) const;
250 };
251 
252 #endif
MiscRegImplDefined64::imm
const uint32_t imm
Definition: misc64.hh:214
RegRegRegImmOp64::RegRegRegImmOp64
RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2, uint64_t _imm)
Definition: misc64.hh:85
ImmOp64
Definition: misc64.hh:43
RegMiscRegImmOp64::op1
ArmISA::MiscRegIndex op1
Definition: misc64.hh:195
MiscRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:153
RegRegRegImmOp64::op2
ArmISA::IntRegIndex op2
Definition: misc64.hh:82
ImmOp64::ImmOp64
ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint64_t _imm)
Definition: misc64.hh:48
MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:121
MiscRegImplDefined64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:868
RegRegRegImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:80
UnknownOp64
Definition: misc64.hh:97
MiscRegOp64::MiscRegOp64
MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, bool misc_read)
Definition: misc64.hh:126
RegRegRegImmOp64
Definition: misc64.hh:77
MiscRegRegImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:177
MiscRegImmOp64::MiscRegImmOp64
MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, uint32_t _imm)
Definition: misc64.hh:155
Loader::SymbolTable
Definition: symtab.hh:59
ArmISA::IntRegIndex
IntRegIndex
Definition: intregs.hh:51
Trace::InstRecord
Definition: insttracer.hh:55
RegRegRegImmOp64::imm
uint64_t imm
Definition: misc64.hh:83
RegRegImmImmOp64::imm1
uint64_t imm1
Definition: misc64.hh:62
RegRegImmImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:61
MiscRegImplDefined64::MiscRegImplDefined64
MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst, ArmISA::MiscRegIndex misc_reg, bool misc_read, uint32_t _imm, const std::string full_mnem, bool _warning)
Definition: misc64.hh:218
ArmISA
Definition: ccregs.hh:41
ArmISA::ec
ec
Definition: miscregs_types.hh:663
RegRegImmImmOp64::RegRegImmImmOp64
RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, uint64_t _imm1, int64_t _imm2)
Definition: misc64.hh:65
ArmISA::ArmStaticInst
Definition: static_inst.hh:60
ImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:44
RegNone::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: misc64.cc:875
MiscRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:809
ImmOp64::imm
uint64_t imm
Definition: misc64.hh:46
MiscRegRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:178
MiscRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:821
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
RegNone::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:240
MiscRegOp64::checkEL3Trap
bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:642
RegMiscRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:833
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
RegMiscRegImmOp64::RegMiscRegImmOp64
RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::MiscRegIndex _op1, uint32_t _imm)
Definition: misc64.hh:198
RegRegRegImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:81
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:70
RegRegImmImmOp64
Definition: misc64.hh:57
RegNone
Definition: misc64.hh:237
UnknownOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:81
RegRegImmImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:60
MiscRegRegImmOp64::dest
ArmISA::MiscRegIndex dest
Definition: misc64.hh:176
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: miscregs.hh:1069
RegMiscRegImmOp64
Definition: misc64.hh:191
RegNone::RegNone
RegNone(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest)
Definition: misc64.hh:242
MiscRegImplDefined64::fullMnemonic
const std::string fullMnemonic
Definition: misc64.hh:212
MiscRegRegImmOp64::MiscRegRegImmOp64
MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, ArmISA::IntRegIndex _op1, uint32_t _imm)
Definition: misc64.hh:180
MiscRegImmOp64
Definition: misc64.hh:149
RegMiscRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:196
MiscRegOp64::trap
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, uint32_t immediate) const
Definition: misc64.cc:88
MiscRegOp64::miscRead
bool miscRead
Definition: misc64.hh:124
MiscRegImplDefined64::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc64.cc:845
MiscRegImplDefined64::warning
const bool warning
Definition: misc64.hh:215
MiscRegImmOp64::miscRegImm
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
Definition: misc64.cc:797
static_inst.hh
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:648
MiscRegImplDefined64::miscReg
const ArmISA::MiscRegIndex miscReg
Definition: misc64.hh:213
MiscRegImmOp64::dest
ArmISA::MiscRegIndex dest
Definition: misc64.hh:152
MiscRegOp64::checkEL1Trap
bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:114
RegMiscRegImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:194
RegRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:66
RegRegImmImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:53
ArmISA::ArmStaticInst::ArmStaticInst
ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:147
MiscRegRegImmOp64
Definition: misc64.hh:173
MiscRegImplDefined64
Definition: misc64.hh:209
MiscRegOp64::checkEL2Trap
bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:179
RegVal
uint64_t RegVal
Definition: types.hh:168
UnknownOp64::UnknownOp64
UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
Definition: misc64.hh:101
RegRegImmImmOp64::imm2
uint64_t imm2
Definition: misc64.hh:63
MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:39

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