gem5  v20.1.0.0
misc64.cc
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1 /*
2  * Copyright (c) 2011-2013,2017-2020 ARM Limited
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4  *
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31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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36  */
37 
38 #include "arch/arm/insts/misc64.hh"
39 #include "arch/arm/isa.hh"
40 
41 using namespace ArmISA;
42 
43 std::string
45 {
46  std::stringstream ss;
47  printMnemonic(ss, "", false);
48  ccprintf(ss, "#0x%x", imm);
49  return ss.str();
50 }
51 
52 std::string
54  Addr pc, const Loader::SymbolTable *symtab) const
55 {
56  std::stringstream ss;
57  printMnemonic(ss, "", false);
58  printIntReg(ss, dest);
59  ss << ", ";
60  printIntReg(ss, op1);
61  ccprintf(ss, ", #%d, #%d", imm1, imm2);
62  return ss.str();
63 }
64 
65 std::string
67  Addr pc, const Loader::SymbolTable *symtab) const
68 {
69  std::stringstream ss;
70  printMnemonic(ss, "", false);
71  printIntReg(ss, dest);
72  ss << ", ";
73  printIntReg(ss, op1);
74  ss << ", ";
75  printIntReg(ss, op2);
76  ccprintf(ss, ", #%d", imm);
77  return ss.str();
78 }
79 
80 std::string
82  Addr pc, const Loader::SymbolTable *symtab) const
83 {
84  return csprintf("%-10s (inst %#08x)", "unknown", encoding());
85 }
86 
87 Fault
89  ExceptionLevel el, uint32_t immediate) const
90 {
92 
93  // Check for traps to supervisor (FP/SIMD regs)
94  if (el <= EL1 && checkEL1Trap(tc, misc_reg, el, ec, immediate)) {
95  return std::make_shared<SupervisorTrap>(machInst, immediate, ec);
96  }
97 
98  // Check for traps to hypervisor
99  if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
100  checkEL2Trap(tc, misc_reg, el, ec, immediate)) {
101  return std::make_shared<HypervisorTrap>(machInst, immediate, ec);
102  }
103 
104  // Check for traps to secure monitor
105  if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
106  checkEL3Trap(tc, misc_reg, el, ec, immediate)) {
107  return std::make_shared<SecureMonitorTrap>(machInst, immediate, ec);
108  }
109 
110  return NoFault;
111 }
112 
113 bool
116  uint32_t &immediate) const
117 {
118  const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
119  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
120  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
121  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
122 
123  bool trap_to_sup = false;
124  switch (misc_reg) {
125  case MISCREG_DAIF:
126  trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
127  trap_to_sup = trap_to_sup ||
128  (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
129  break;
130  case MISCREG_DC_ZVA_Xt:
131  // In syscall-emulation mode, this test is skipped and DCZVA is always
132  // allowed at EL0
133  trap_to_sup = el == EL0 && !sctlr.dze && FullSystem;
134  break;
135  case MISCREG_DC_CIVAC_Xt:
136  case MISCREG_DC_CVAC_Xt:
137  trap_to_sup = el == EL0 && !sctlr.uci;
138  break;
139  case MISCREG_FPCR:
140  case MISCREG_FPSR:
141  case MISCREG_FPEXC32_EL2:
142  if ((el == EL0 && cpacr.fpen != 0x3) ||
143  (el == EL1 && !(cpacr.fpen & 0x1))) {
144  trap_to_sup = true;
146  immediate = 0x1E00000;
147  }
148  break;
149  case MISCREG_DC_CVAU_Xt:
150  trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
151  el == EL0;
152  break;
153  case MISCREG_CTR_EL0:
154  trap_to_sup = el == EL0 && !sctlr.uct &&
155  (!hcr.tge || (!scr.ns && !scr.eel2));
156  break;
157  case MISCREG_MDCCSR_EL0:
158  {
159  DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
160  trap_to_sup = el == EL0 && mdscr.tdcc &&
161  (hcr.tge == 0x0 || ( scr.ns == 0x0));
162  }
163  break;
164  case MISCREG_ZCR_EL1:
165  trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
166  break;
167  // Generic Timer
169  trap_to_sup = el == EL0 &&
170  isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
171  break;
172  default:
173  break;
174  }
175  return trap_to_sup;
176 }
177 
178 bool
181  uint32_t &immediate) const
182 {
183  const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
184  const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
185  const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
186  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
187  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
188  const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
189 
190  bool trap_to_hyp = false;
191 
192  switch (misc_reg) {
194  trap_to_hyp = EL2Enabled(tc) && hcr.tidcp && el == EL1;
195  break;
196  // GICv3 regs
198  {
199  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
200  if (isa->haveGICv3CpuIfc())
201  trap_to_hyp = EL2Enabled(tc) && hcr.fmo && el == EL1;
202  }
203  break;
206  {
207  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
208  if (isa->haveGICv3CpuIfc())
209  trap_to_hyp = EL2Enabled(tc) && hcr.imo && el == EL1;
210  }
211  break;
212  case MISCREG_FPCR:
213  case MISCREG_FPSR:
214  case MISCREG_FPEXC32_EL2:
215  {
216  bool from_el2 = (el == EL2) && (scr.ns || scr.eel2) &&
217  ELIs64(tc,EL2) &&
218  ((!hcr.e2h && cptr.tfp) ||
219  (hcr.e2h && (cptr.fpen == 0x0 ||
220  cptr.fpen == 0xa)));
221  bool from_el1 = (el == EL1) && hcr.nv &&
222  (!hcr.e2h || (hcr.e2h && !hcr.tge));
223  trap_to_hyp = from_el2 || from_el1;
225  immediate = 0x1E00000;
226  }
227  break;
228  case MISCREG_CPACR_EL1:
229  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && cptr.tcpac;
230  break;
231  case MISCREG_SCTLR_EL1:
232  case MISCREG_TTBR0_EL1:
233  case MISCREG_TTBR1_EL1:
234  case MISCREG_TCR_EL1:
235  case MISCREG_ESR_EL1:
236  case MISCREG_FAR_EL1:
237  case MISCREG_AFSR0_EL1:
238  case MISCREG_AFSR1_EL1:
239  case MISCREG_MAIR_EL1:
240  case MISCREG_AMAIR_EL1:
242  {
243  bool tvm = miscRead? hcr.trvm: hcr.tvm;
244  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && tvm;
245  }
246  break;
247  case MISCREG_CPACR_EL12:
248  case MISCREG_SCTLR_EL12:
249  case MISCREG_TTBR0_EL12:
250  case MISCREG_TTBR1_EL12:
251  case MISCREG_TCR_EL12:
252  case MISCREG_ESR_EL12:
253  case MISCREG_FAR_EL12:
254  case MISCREG_AFSR0_EL12:
255  case MISCREG_AFSR1_EL12:
256  case MISCREG_MAIR_EL12:
257  case MISCREG_AMAIR_EL12:
259  case MISCREG_SPSR_EL12:
260  case MISCREG_ELR_EL12:
261  case MISCREG_VBAR_EL12:
262  trap_to_hyp = EL2Enabled(tc) && (el == EL1) &&
263  (hcr.nv && (hcr.nv1 || !hcr.nv2));
264  break;
271 // case MISCREG_TLBI_RVAE1:
272 // case MISCREG_TLBI_RVAAE1:
273 // case MISCREG_TLBI_RVALE1:
274 // case MISCREG_TLBI_RVAALE1:
281 // case MISCREG_TLBI_RVAE1IS:
282 // case MISCREG_TLBI_RVAAE1IS:
283 // case MISCREG_TLBI_RVALE1IS:
284 // case MISCREG_TLBI_RVAALE1IS:
285 // case MISCREG_TLBI_VMALLE1OS:
286 // case MISCREG_TLBI_VAE1OS:
287 // case MISCREG_TLBI_ASIDE1OS:
288 // case MISCREG_TLBI_VAAE1OS:
289 // case MISCREG_TLBI_VALE1OS:
290 // case MISCREG_TLBI_VAALE1OS:
291 // case MISCREG_TLBI_RVAE1OS:
292 // case MISCREG_TLBI_RVAAE1OS:
293 // case MISCREG_TLBI_RVALE1OS:
294 // case MISCREG_TLBI_RVAALE1OS:
295  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.ttlb;
296  break;
297  case MISCREG_IC_IVAU_Xt:
298  case MISCREG_ICIALLU:
299  case MISCREG_ICIALLUIS:
300  trap_to_hyp = (el == EL1) && EL2Enabled(tc) && hcr.tpu;
301  break;
302  case MISCREG_DC_CVAU_Xt:
303  {
304  const bool el2_en = EL2Enabled(tc);
305  if (el == EL0 && el2_en) {
306  const bool in_host = hcr.e2h && hcr.tge;
307  const bool general_trap = el2_en && !in_host && hcr.tge &&
308  !sctlr.uci;
309  const bool tpu_trap = el2_en && !in_host && hcr.tpu;
310  const bool host_trap = el2_en && in_host && !sctlr2.uci;
311  trap_to_hyp = general_trap || tpu_trap || host_trap;
312  }
313  else if (el == EL1 && el2_en) {
314  trap_to_hyp = hcr.tpu;
315  }
316  }
317  break;
318  case MISCREG_DC_IVAC_Xt:
319  trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tpc;
320  break;
321  case MISCREG_DC_CVAC_Xt:
322 // case MISCREG_DC_CVAP_Xt:
323  case MISCREG_DC_CIVAC_Xt:
324  {
325  const bool el2_en = EL2Enabled(tc);
326  if (el == EL0 && el2_en) {
327 
328  const bool in_host = hcr.e2h && hcr.tge;
329  const bool general_trap = el2_en && !in_host && hcr.tge &&
330  !sctlr.uci;
331  const bool tpc_trap = el2_en && !in_host && hcr.tpc;
332  const bool host_trap = el2_en && in_host && !sctlr2.uci;
333  trap_to_hyp = general_trap || tpc_trap || host_trap;
334  } else if (el == EL1 && el2_en) {
335  trap_to_hyp = hcr.tpc;
336  }
337  }
338  break;
339  case MISCREG_DC_ISW_Xt:
340  case MISCREG_DC_CSW_Xt:
341  case MISCREG_DC_CISW_Xt:
342  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tsw;
343  break;
344  case MISCREG_ACTLR_EL1:
345  trap_to_hyp = EL2Enabled (tc) && (el == EL1) && hcr.tacr;
346  break;
357  trap_to_hyp = EL2Enabled(tc) && el == EL1 && !hcr.apk;
358  break;
359  case MISCREG_ID_PFR0_EL1:
360  case MISCREG_ID_PFR1_EL1:
361  //case MISCREG_ID_PFR2_EL1:
362  case MISCREG_ID_DFR0_EL1:
363  case MISCREG_ID_AFR0_EL1:
368  //case MISCREG_ID_MMFR4_EL1:
375  case MISCREG_MVFR0_EL1:
376  case MISCREG_MVFR1_EL1:
377  case MISCREG_MVFR2_EL1:
389  trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tid3;
390  break;
391  case MISCREG_CTR_EL0:
392  {
393  const bool el2_en = EL2Enabled(tc);
394  if (el == EL0 && el2_en) {
395  const bool in_host = hcr.e2h && hcr.tge;
396  const bool general_trap = el2_en && !in_host && hcr.tge &&
397  !sctlr.uct;
398  const bool tid_trap = el2_en && !in_host && hcr.tid2;
399  const bool host_trap = el2_en && in_host && !sctlr2.uct;
400  trap_to_hyp = general_trap || tid_trap || host_trap;
401  } else if (el == EL1 && el2_en) {
402  trap_to_hyp = hcr.tid2;
403  }
404  }
405  break;
406  case MISCREG_CCSIDR_EL1:
407 // case MISCREG_CCSIDR2_EL1:
408  case MISCREG_CLIDR_EL1:
409  case MISCREG_CSSELR_EL1:
410  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tid2;
411  break;
412  case MISCREG_AIDR_EL1:
413  case MISCREG_REVIDR_EL1:
414  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tid1;
415  break;
416  // Generic Timer
418  trap_to_hyp = el <= EL1 &&
419  isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
420  break;
421  case MISCREG_DAIF:
422  trap_to_hyp = EL2Enabled(tc) && el == EL0 &&
423  (hcr.tge && (hcr.e2h || !sctlr.uma));
424  break;
425  case MISCREG_SPSR_EL1:
426  case MISCREG_ELR_EL1:
427  case MISCREG_VBAR_EL1:
428  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv1 && !hcr.nv2;
429  break;
430  case MISCREG_HCR_EL2:
431  case MISCREG_HSTR_EL2:
432  case MISCREG_SP_EL1:
433  case MISCREG_TPIDR_EL2:
434  case MISCREG_VTCR_EL2:
435  case MISCREG_VTTBR_EL2:
436  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv && !hcr.nv2;
437  break;
438 // case MISCREG_AT_S1E1WP_Xt:
439 // case MISCREG_AT_S1E1RP_Xt:
440  case MISCREG_AT_S1E1R_Xt:
441  case MISCREG_AT_S1E1W_Xt:
442  case MISCREG_AT_S1E0W_Xt:
443  case MISCREG_AT_S1E0R_Xt:
444  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.at;
445  break;
446  case MISCREG_ACTLR_EL2:
447  case MISCREG_AFSR0_EL2:
448  case MISCREG_AFSR1_EL2:
449  case MISCREG_AMAIR_EL2:
451  case MISCREG_CPTR_EL2:
452  case MISCREG_DACR32_EL2:
453  case MISCREG_ESR_EL2:
454  case MISCREG_FAR_EL2:
455  case MISCREG_HACR_EL2:
456  case MISCREG_HPFAR_EL2:
457  case MISCREG_MAIR_EL2:
458 // case MISCREG_RMR_EL2:
459  case MISCREG_SCTLR_EL2:
460  case MISCREG_TCR_EL2:
461  case MISCREG_TTBR0_EL2:
462  case MISCREG_TTBR1_EL2:
463  case MISCREG_VBAR_EL2:
464  case MISCREG_VMPIDR_EL2:
465  case MISCREG_VPIDR_EL2:
466  case MISCREG_TLBI_ALLE1:
468 // case MISCREG_TLBI_ALLE1OS:
469  case MISCREG_TLBI_ALLE2:
471 // case MISCREG_TLBI_ALLE2OS:
474 // case MISCREG_TLBI_IPAS2E1OS:
477 // case MISCREG_TLBI_IPAS2LE1OS:
478 // case MISCREG_TLBI_RIPAS2E1:
479 // case MISCREG_TLBI_RIPAS2E1IS:
480 // case MISCREG_TLBI_RIPAS2E1OS:
481 // case MISCREG_TLBI_RIPAS2LE1:
482 // case MISCREG_TLBI_RIPAS2LE1IS:
483 // case MISCREG_TLBI_RIPAS2LE1OS:
484 // case MISCREG_TLBI_RVAE2:
485 // case MISCREG_TLBI_RVAE2IS:
486 // case MISCREG_TLBI_RVAE2OS:
487 // case MISCREG_TLBI_RVALE2:
488 // case MISCREG_TLBI_RVALE2IS:
489 // case MISCREG_TLBI_RVALE2OS:
492 // case MISCREG_TLBI_VAE2OS:
495 // case MISCREG_TLBI_VALE2OS:
498 // case MISCREG_TLBI_VMALLS12E1OS:
499  case MISCREG_AT_S1E2W_Xt:
500  case MISCREG_AT_S1E2R_Xt:
505  case MISCREG_SPSR_UND:
506  case MISCREG_SPSR_IRQ:
507  case MISCREG_SPSR_FIQ:
508  case MISCREG_SPSR_ABT:
509  case MISCREG_SPSR_EL2:
510  case MISCREG_ELR_EL2:
511  case MISCREG_IFSR32_EL2:
513  case MISCREG_MDCR_EL2:
514  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv;
515  break;
516 // case MISCREG_VSTTBR_EL2:
517 // case MISCREG_VSTCR_EL2:
518 // trap_to_hyp = (el == EL1) && !scr.ns && scr.eel2 && ELIs64(tc,EL2)
519 // && !hcr.nv2 && hcr.nv && (!hcr.e2h|| (hcr.e2h && !hcr.tge));
520 // break;
521 
522  //case MISCREG_LORC_EL1:
523  //case MISCREG_LOREA_EL1:
524  //case MISCREG_LORID_EL1:
525  //case MISCREG_LORN_EL1:
526  //case MISCREG_LORSA_EL1:
527  // trap_to_hyp = (el == EL1) && (scr.ns || scr.eel2) && ELIs64(tc,EL2)
528  // && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
529  // break;
530 
531  case MISCREG_DC_ZVA_Xt:
532  {
533  const bool el2_en = EL2Enabled(tc);
534  if (el == EL0 && el2_en) {
535  const bool in_host = hcr.e2h && hcr.tge;
536  const bool general_trap = el2_en && !in_host && hcr.tge &&
537  !sctlr.dze;
538  const bool tdz_trap = el2_en && !in_host && hcr.tdz;
539  const bool host_trap = el2_en && in_host && !sctlr2.dze;
540  trap_to_hyp = general_trap || tdz_trap || host_trap;
541  } else if (el == EL1 && el2_en) {
542  trap_to_hyp = hcr.tdz;
543  }
544  }
545  break;
546  case MISCREG_DBGBVR0_EL1:
547  case MISCREG_DBGBVR1_EL1:
548  case MISCREG_DBGBVR2_EL1:
549  case MISCREG_DBGBVR3_EL1:
550  case MISCREG_DBGBVR4_EL1:
551  case MISCREG_DBGBVR5_EL1:
552  case MISCREG_DBGBVR6_EL1:
553  case MISCREG_DBGBVR7_EL1:
554  case MISCREG_DBGBVR8_EL1:
555  case MISCREG_DBGBVR9_EL1:
562  case MISCREG_DBGBCR0_EL1:
563  case MISCREG_DBGBCR1_EL1:
564  case MISCREG_DBGBCR2_EL1:
565  case MISCREG_DBGBCR3_EL1:
566  case MISCREG_DBGBCR4_EL1:
567  case MISCREG_DBGBCR5_EL1:
568  case MISCREG_DBGBCR6_EL1:
569  case MISCREG_DBGBCR7_EL1:
570  case MISCREG_DBGBCR8_EL1:
571  case MISCREG_DBGBCR9_EL1:
578  case MISCREG_DBGWVR0_EL1:
579  case MISCREG_DBGWVR1_EL1:
580  case MISCREG_DBGWVR2_EL1:
581  case MISCREG_DBGWVR3_EL1:
582  case MISCREG_DBGWVR4_EL1:
583  case MISCREG_DBGWVR5_EL1:
584  case MISCREG_DBGWVR6_EL1:
585  case MISCREG_DBGWVR7_EL1:
586  case MISCREG_DBGWVR8_EL1:
587  case MISCREG_DBGWVR9_EL1:
594  case MISCREG_DBGWCR0_EL1:
595  case MISCREG_DBGWCR1_EL1:
596  case MISCREG_DBGWCR2_EL1:
597  case MISCREG_DBGWCR3_EL1:
598  case MISCREG_DBGWCR4_EL1:
599  case MISCREG_DBGWCR5_EL1:
600  case MISCREG_DBGWCR6_EL1:
601  case MISCREG_DBGWCR7_EL1:
602  case MISCREG_DBGWCR8_EL1:
603  case MISCREG_DBGWCR9_EL1:
610  case MISCREG_MDCCINT_EL1:
611  trap_to_hyp = EL2Enabled(tc) && (el == EL1) && mdcr.tda;
612  break;
613  case MISCREG_ZCR_EL1:
614  {
615  bool from_el1 = (el == EL1) && EL2Enabled(tc) &&
616  ELIs64(tc, EL2) && ((!hcr.e2h && cptr.tz) ||
617  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
618  bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
619  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
620  trap_to_hyp = from_el1 || from_el2;
621  }
622  ec = EC_TRAPPED_SVE;
623  immediate = 0;
624  break;
625  case MISCREG_ZCR_EL2:
626  {
627  bool from_el1 = (el == EL1) && EL2Enabled(tc) && hcr.nv;
628  bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
629  (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
630  trap_to_hyp = from_el1 || from_el2;
632  }
633  immediate = 0;
634  break;
635  default:
636  break;
637  }
638  return trap_to_hyp;
639 }
640 
641 bool
644  uint32_t &immediate) const
645 {
646  const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
647  const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
648  const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
649  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
650  bool trap_to_mon = false;
651 
652  switch (misc_reg) {
653  // FP/SIMD regs
654  case MISCREG_FPCR:
655  case MISCREG_FPSR:
656  case MISCREG_FPEXC32_EL2:
657  trap_to_mon = cptr.tfp && ELIs64(tc, EL3);
659  immediate = 0x1E00000;
660  break;
661  // CPACR, CPTR
662  case MISCREG_CPACR_EL12:
663  trap_to_mon = ((el == EL2 && cptr.tcpac && ELIs64(tc, EL3)) ||
664  (el == EL1 && cptr.tcpac && ELIs64(tc, EL3) &&
665  (!hcr.nv2 || hcr.nv1 || !hcr.nv))) ;
666  break;
667  case MISCREG_CPACR_EL1:
668  trap_to_mon = el <= EL2 && cptr.tcpac && ELIs64(tc, EL3);
669  break;
670  case MISCREG_CPTR_EL2:
671  if (el == EL2) {
672  trap_to_mon = cptr.tcpac;
673  }
674  break;
675 // case MISCREG_LORC_EL1:
676 // case MISCREG_LOREA_EL1:
677 // case MISCREG_LORID_EL1:
678 // case MISCREG_LORN_EL1:
679 // case MISCREG_LORSA_EL1:
680 // trap_to_mon = (el <= EL2) && scr.ns && ELIs64(tc,EL3)
681 // && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
682 // break;
683  case MISCREG_MDCCSR_EL0:
684  trap_to_mon = (el <= EL2) && ELIs64(tc, EL3) && mdcr.tda == 0x1;
685  break;
696  trap_to_mon = (el == EL1 || el == EL2) && scr.apk == 0 &&
697  ELIs64(tc, EL3);
698  break;
699  // Generic Timer
701  trap_to_mon = el == EL1 &&
702  isGenericTimerSystemAccessTrapEL3(misc_reg, tc);
703  break;
704  case MISCREG_DBGBVR0_EL1:
705  case MISCREG_DBGBVR1_EL1:
706  case MISCREG_DBGBVR2_EL1:
707  case MISCREG_DBGBVR3_EL1:
708  case MISCREG_DBGBVR4_EL1:
709  case MISCREG_DBGBVR5_EL1:
710  case MISCREG_DBGBVR6_EL1:
711  case MISCREG_DBGBVR7_EL1:
712  case MISCREG_DBGBVR8_EL1:
713  case MISCREG_DBGBVR9_EL1:
720  case MISCREG_DBGBCR0_EL1:
721  case MISCREG_DBGBCR1_EL1:
722  case MISCREG_DBGBCR2_EL1:
723  case MISCREG_DBGBCR3_EL1:
724  case MISCREG_DBGBCR4_EL1:
725  case MISCREG_DBGBCR5_EL1:
726  case MISCREG_DBGBCR6_EL1:
727  case MISCREG_DBGBCR7_EL1:
728  case MISCREG_DBGBCR8_EL1:
729  case MISCREG_DBGBCR9_EL1:
737  case MISCREG_DBGWVR0_EL1:
738  case MISCREG_DBGWVR1_EL1:
739  case MISCREG_DBGWVR2_EL1:
740  case MISCREG_DBGWVR3_EL1:
741  case MISCREG_DBGWVR4_EL1:
742  case MISCREG_DBGWVR5_EL1:
743  case MISCREG_DBGWVR6_EL1:
744  case MISCREG_DBGWVR7_EL1:
745  case MISCREG_DBGWVR8_EL1:
746  case MISCREG_DBGWVR9_EL1:
753  case MISCREG_DBGWCR0_EL1:
754  case MISCREG_DBGWCR1_EL1:
755  case MISCREG_DBGWCR2_EL1:
756  case MISCREG_DBGWCR3_EL1:
757  case MISCREG_DBGWCR4_EL1:
758  case MISCREG_DBGWCR5_EL1:
759  case MISCREG_DBGWCR6_EL1:
760  case MISCREG_DBGWCR7_EL1:
761  case MISCREG_DBGWCR8_EL1:
762  case MISCREG_DBGWCR9_EL1:
769  case MISCREG_MDCCINT_EL1:
770  case MISCREG_MDCR_EL2:
771  trap_to_mon = ELIs64(tc, EL3) && mdcr.tda && (el == EL2);
772  break;
773  case MISCREG_ZCR_EL1:
774  trap_to_mon = !cptr.ez && ((el == EL3) ||
775  ((el <= EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
776  ec = EC_TRAPPED_SVE;
777  immediate = 0;
778  break;
779  case MISCREG_ZCR_EL2:
780  trap_to_mon = !cptr.ez && ((el == EL3) ||
781  ((el == EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
782  ec = EC_TRAPPED_SVE;
783  immediate = 0;
784  break;
785  case MISCREG_ZCR_EL3:
786  trap_to_mon = !cptr.ez && (el == EL3);
787  ec = EC_TRAPPED_SVE;
788  immediate = 0;
789  break;
790  default:
791  break;
792  }
793  return trap_to_mon;
794 }
795 
796 RegVal
798 {
799  if (dest == MISCREG_SPSEL) {
800  return imm & 0x1;
801  } else if (dest == MISCREG_PAN) {
802  return (imm & 0x1) << 22;
803  } else {
804  panic("Not a valid PSTATE field register\n");
805  }
806 }
807 
808 std::string
810  Addr pc, const Loader::SymbolTable *symtab) const
811 {
812  std::stringstream ss;
813  printMnemonic(ss);
814  printMiscReg(ss, dest);
815  ss << ", ";
816  ccprintf(ss, "#0x%x", imm);
817  return ss.str();
818 }
819 
820 std::string
822  Addr pc, const Loader::SymbolTable *symtab) const
823 {
824  std::stringstream ss;
825  printMnemonic(ss);
826  printMiscReg(ss, dest);
827  ss << ", ";
828  printIntReg(ss, op1);
829  return ss.str();
830 }
831 
832 std::string
834  Addr pc, const Loader::SymbolTable *symtab) const
835 {
836  std::stringstream ss;
837  printMnemonic(ss);
838  printIntReg(ss, dest);
839  ss << ", ";
840  printMiscReg(ss, op1);
841  return ss.str();
842 }
843 
844 Fault
846  Trace::InstRecord *traceData) const
847 {
848  auto tc = xc->tcBase();
849  const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
850  const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
851 
852  Fault fault = trap(tc, miscReg, el, imm);
853 
854  if (fault != NoFault) {
855  return fault;
856 
857  } else if (warning) {
858  warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
859  return NoFault;
860 
861  } else {
862  return std::make_shared<UndefinedInstruction>(machInst, false,
863  mnemonic);
864  }
865 }
866 
867 std::string
869  Addr pc, const Loader::SymbolTable *symtab) const
870 {
871  return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
872 }
873 
874 std::string
876  Addr pc, const Loader::SymbolTable *symtab) const
877 {
878  std::stringstream ss;
879  printMnemonic(ss);
880  printIntReg(ss, dest);
881  return ss.str();
882 }
ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: miscregs.hh:644
MiscRegImplDefined64::imm
const uint32_t imm
Definition: misc64.hh:214
ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: miscregs.hh:552
ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: miscregs.hh:471
ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: miscregs.hh:603
ArmISA::isGenericTimerSystemAccessTrapEL3
bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1205
ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: miscregs.hh:814
ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: miscregs.hh:630
ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: miscregs.hh:826
ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: miscregs.hh:490
ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:369
ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: miscregs.hh:682
ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: miscregs.hh:558
ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: miscregs.hh:661
ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: miscregs.hh:461
ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: miscregs.hh:550
ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: miscregs.hh:470
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:560
ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: miscregs.hh:504
ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: miscregs.hh:454
ArmISA::EL2
@ EL2
Definition: types.hh:624
RegMiscRegImmOp64::op1
ArmISA::MiscRegIndex op1
Definition: misc64.hh:195
MiscRegImmOp64::imm
uint32_t imm
Definition: misc64.hh:153
ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: miscregs.hh:1048
ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: miscregs.hh:628
ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: miscregs.hh:507
ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: miscregs.hh:567
ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: miscregs.hh:660
ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: miscregs.hh:658
ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: miscregs.hh:737
ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: miscregs.hh:65
ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: miscregs.hh:509
ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: miscregs.hh:500
ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: miscregs.hh:675
ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: miscregs.hh:820
ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: miscregs.hh:511
warn_once
#define warn_once(...)
Definition: logging.hh:243
ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: miscregs.hh:559
ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: miscregs.hh:570
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:745
MiscRegImplDefined64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:868
ArmISA::EL0
@ EL0
Definition: types.hh:622
ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: miscregs.hh:514
ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: miscregs.hh:673
ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: miscregs.hh:452
ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: miscregs.hh:483
ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: miscregs.hh:502
ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: miscregs.hh:515
ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: miscregs.hh:286
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:614
ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: miscregs.hh:589
ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: miscregs.hh:291
ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: miscregs.hh:597
ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: miscregs.hh:612
ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: miscregs.hh:489
ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: miscregs.hh:676
ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: miscregs.hh:473
ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: miscregs.hh:695
ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: miscregs.hh:551
ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: miscregs.hh:496
ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: miscregs.hh:656
MiscRegRegImmOp64::op1
ArmISA::IntRegIndex op1
Definition: misc64.hh:177
Loader::SymbolTable
Definition: symtab.hh:59
ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: miscregs.hh:819
Trace::InstRecord
Definition: insttracer.hh:55
ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: miscregs.hh:588
ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: miscregs.hh:520
ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: miscregs.hh:672
ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: miscregs.hh:491
ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: miscregs.hh:683
ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: miscregs.hh:654
ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:296
ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: miscregs.hh:564
ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: miscregs.hh:487
ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: miscregs.hh:512
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: miscregs.hh:618
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: miscregs.hh:821
ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: miscregs.hh:631
ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: miscregs.hh:596
ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: miscregs.hh:547
ArmISA::ISA
Definition: isa.hh:65
ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: miscregs.hh:447
ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: miscregs.hh:606
ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: miscregs.hh:575
ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: miscregs.hh:1050
ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: miscregs.hh:513
ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: miscregs.hh:652
ArmISA
Definition: ccregs.hh:41
ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: miscregs.hh:687
ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: miscregs.hh:667
ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: miscregs.hh:742
ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: miscregs.hh:566
ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:170
ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: miscregs.hh:548
ArmISA::ec
ec
Definition: miscregs_types.hh:663
ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: miscregs.hh:482
ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: miscregs.hh:561
ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: miscregs.hh:635
ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: miscregs.hh:505
ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: miscregs.hh:557
ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: miscregs.hh:485
ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: miscregs.hh:498
ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: miscregs.hh:659
ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: miscregs.hh:499
ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: miscregs.hh:540
ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:377
ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: miscregs.hh:556
ImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:44
ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: miscregs.hh:649
ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: miscregs.hh:732
ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: miscregs.hh:549
ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: miscregs.hh:664
ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: miscregs.hh:634
ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: miscregs.hh:469
ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: miscregs.hh:468
ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: miscregs.hh:720
RegNone::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Internal function to generate disassembly string.
Definition: misc64.cc:875
MiscRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:809
ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: miscregs.hh:488
ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: miscregs.hh:854
ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: miscregs.hh:657
ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: miscregs.hh:458
ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: miscregs.hh:541
MiscRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:821
ArmISA::EC_TRAPPED_SVE
@ EC_TRAPPED_SVE
Definition: types.hh:672
misc64.hh
ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: miscregs.hh:546
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:553
ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: miscregs.hh:642
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:161
ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: miscregs.hh:650
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: miscregs.hh:636
RegNone::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:240
ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: miscregs.hh:503
ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: miscregs.hh:572
ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: miscregs.hh:723
MiscRegOp64::checkEL3Trap
bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:642
RegMiscRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:833
ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: miscregs.hh:449
ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: miscregs.hh:544
ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: miscregs.hh:539
ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: miscregs.hh:809
ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: miscregs.hh:627
ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: miscregs.hh:671
ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: miscregs.hh:493
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:141
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: miscregs.hh:581
ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: miscregs.hh:666
ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: miscregs.hh:538
ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: miscregs.hh:852
ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: miscregs.hh:825
ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: miscregs.hh:562
isa.hh
ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: miscregs.hh:728
ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: miscregs.hh:663
ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: miscregs.hh:466
ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: miscregs.hh:653
ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: miscregs.hh:486
ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: miscregs.hh:495
ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: miscregs.hh:818
ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: miscregs.hh:484
ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: miscregs.hh:822
ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: miscregs.hh:60
ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: miscregs.hh:593
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::ArmStaticInst::printMiscReg
void printMiscReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:367
ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: miscregs.hh:63
ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:70
ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: miscregs.hh:555
ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: miscregs.hh:492
ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: miscregs.hh:577
ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: miscregs.hh:477
ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: miscregs.hh:688
ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: miscregs.hh:455
ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: miscregs.hh:641
ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: miscregs.hh:679
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: miscregs.hh:462
ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: miscregs.hh:729
ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: miscregs.hh:637
ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: miscregs.hh:595
ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: miscregs.hh:670
UnknownOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:81
ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: miscregs.hh:780
ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: miscregs.hh:721
ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: miscregs.hh:692
ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: miscregs.hh:633
ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: miscregs.hh:506
ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: miscregs.hh:479
ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: miscregs.hh:594
ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: miscregs.hh:510
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:578
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: miscregs.hh:465
ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: miscregs.hh:591
ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: miscregs.hh:535
MiscRegRegImmOp64::dest
ArmISA::MiscRegIndex dest
Definition: misc64.hh:176
ArmISA::EL1
@ EL1
Definition: types.hh:623
ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: miscregs.hh:605
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: miscregs.hh:824
ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: miscregs.hh:1069
ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: miscregs.hh:823
ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: miscregs.hh:651
ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: miscregs.hh:481
ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: miscregs.hh:1047
ArmISA::EC_TRAPPED_MSR_MRS_64
@ EC_TRAPPED_MSR_MRS_64
Definition: types.hh:671
ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: miscregs.hh:719
ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: miscregs.hh:619
ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: miscregs.hh:738
ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: miscregs.hh:573
ArmISA::isGenericTimerSystemAccessTrapEL1
bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:975
ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: miscregs.hh:1085
ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: miscregs.hh:694
ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: miscregs.hh:582
MiscRegImplDefined64::fullMnemonic
const std::string fullMnemonic
Definition: misc64.hh:212
ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: miscregs.hh:475
ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: miscregs.hh:677
ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: miscregs.hh:456
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:585
ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: miscregs.hh:580
ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: miscregs.hh:817
ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: miscregs.hh:609
MiscRegOp64::trap
Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, uint32_t immediate) const
Definition: misc64.cc:88
ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
MiscRegImplDefined64::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc64.cc:845
ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: miscregs.hh:467
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: miscregs.hh:674
ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: miscregs.hh:472
ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: miscregs.hh:607
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:613
ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: miscregs.hh:662
ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: miscregs.hh:563
ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: miscregs.hh:629
ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: miscregs.hh:459
MiscRegImplDefined64::warning
const bool warning
Definition: misc64.hh:215
StaticInst::machInst
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:243
MiscRegImmOp64::miscRegImm
RegVal miscRegImm() const
Returns the "register view" of the immediate field.
Definition: misc64.cc:797
ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: miscregs.hh:684
ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: miscregs.hh:686
ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: miscregs.hh:536
ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: miscregs.hh:545
ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: miscregs.hh:579
ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: miscregs.hh:853
ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: miscregs.hh:722
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: miscregs.hh:464
ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: miscregs.hh:681
ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:374
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ArmISA::ExceptionClass
ExceptionClass
Definition: types.hh:648
ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:135
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: miscregs.hh:508
ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: miscregs.hh:474
MiscRegImplDefined64::miscReg
const ArmISA::MiscRegIndex miscReg
Definition: misc64.hh:213
MiscRegImmOp64::dest
ArmISA::MiscRegIndex dest
Definition: misc64.hh:152
ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: miscregs.hh:632
ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: miscregs.hh:494
ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: miscregs.hh:457
ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: miscregs.hh:569
ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: miscregs.hh:463
MiscRegOp64::checkEL1Trap
bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:114
ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: miscregs.hh:689
ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: miscregs.hh:592
ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: miscregs.hh:718
ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: miscregs.hh:565
RegMiscRegImmOp64::dest
ArmISA::IntRegIndex dest
Definition: misc64.hh:194
RegRegRegImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:66
ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: miscregs.hh:598
ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: miscregs.hh:812
ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: miscregs.hh:537
RegRegImmImmOp64::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc64.cc:53
ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: miscregs.hh:543
ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: miscregs.hh:665
ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: miscregs.hh:516
ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: miscregs.hh:693
ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: miscregs.hh:497
ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: miscregs.hh:574
ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: miscregs.hh:480
ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: miscregs.hh:643
ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: miscregs.hh:542
ArmISA::encoding
Bitfield< 27, 25 > encoding
Definition: types.hh:99
ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: miscregs.hh:691
ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: miscregs.hh:690
ArmISA::EC_TRAPPED_SIMD_FP
@ EC_TRAPPED_SIMD_FP
Definition: types.hh:657
ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: miscregs.hh:476
ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: miscregs.hh:680
ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: miscregs.hh:478
ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: miscregs.hh:655
ArmISA::tvm
Bitfield< 26 > tvm
Definition: miscregs_types.hh:254
ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: miscregs.hh:587
ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: miscregs.hh:617
ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: miscregs.hh:576
ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: miscregs.hh:554
csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:158
ArmISA::isGenericTimerSystemAccessTrapEL2
bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:1035
ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: miscregs.hh:501
ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: miscregs.hh:460
ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: miscregs.hh:59
MiscRegOp64::checkEL2Trap
bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg, ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec, uint32_t &immediate) const
Definition: misc64.cc:179
ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: miscregs.hh:685
ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: miscregs.hh:453
RegVal
uint64_t RegVal
Definition: types.hh:168
ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: miscregs.hh:590
ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: miscregs.hh:571
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: miscregs.hh:678
ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: miscregs.hh:604

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