gem5  v20.1.0.0
miscregs.cc
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37 
38 #include "arch/arm/miscregs.hh"
39 
40 #include <tuple>
41 
42 #include "arch/arm/isa.hh"
43 #include "base/logging.hh"
44 #include "cpu/thread_context.hh"
45 #include "sim/full_system.hh"
46 
47 namespace ArmISA
48 {
49 
50 MiscRegIndex
51 decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
52 {
53  switch(crn) {
54  case 0:
55  switch (opc1) {
56  case 0:
57  switch (opc2) {
58  case 0:
59  switch (crm) {
60  case 0:
61  return MISCREG_DBGDIDR;
62  case 1:
63  return MISCREG_DBGDSCRint;
64  case 7:
65  return MISCREG_DBGVCR;
66  }
67  break;
68  case 2:
69  switch (crm) {
70  case 0:
71  return MISCREG_DBGDTRRXext;
72  case 2:
73  return MISCREG_DBGDSCRext;
74  case 3:
75  return MISCREG_DBGDTRTXext;
76  case 6:
77  return MISCREG_DBGOSECCR;
78  }
79  break;
80  case 4:
81  switch (crm) {
82  case 0:
83  return MISCREG_DBGBVR0;
84  case 1:
85  return MISCREG_DBGBVR1;
86  case 2:
87  return MISCREG_DBGBVR2;
88  case 3:
89  return MISCREG_DBGBVR3;
90  case 4:
91  return MISCREG_DBGBVR4;
92  case 5:
93  return MISCREG_DBGBVR5;
94  case 6:
95  return MISCREG_DBGBVR6;
96  case 7:
97  return MISCREG_DBGBVR7;
98  case 8:
99  return MISCREG_DBGBVR8;
100  case 9:
101  return MISCREG_DBGBVR9;
102  case 10:
103  return MISCREG_DBGBVR10;
104  case 11:
105  return MISCREG_DBGBVR11;
106  case 12:
107  return MISCREG_DBGBVR12;
108  case 13:
109  return MISCREG_DBGBVR13;
110  case 14:
111  return MISCREG_DBGBVR14;
112  case 15:
113  return MISCREG_DBGBVR15;
114  }
115  break;
116  case 5:
117  switch (crm) {
118  case 0:
119  return MISCREG_DBGBCR0;
120  case 1:
121  return MISCREG_DBGBCR1;
122  case 2:
123  return MISCREG_DBGBCR2;
124  case 3:
125  return MISCREG_DBGBCR3;
126  case 4:
127  return MISCREG_DBGBCR4;
128  case 5:
129  return MISCREG_DBGBCR5;
130  case 6:
131  return MISCREG_DBGBCR6;
132  case 7:
133  return MISCREG_DBGBCR7;
134  case 8:
135  return MISCREG_DBGBCR8;
136  case 9:
137  return MISCREG_DBGBCR9;
138  case 10:
139  return MISCREG_DBGBCR10;
140  case 11:
141  return MISCREG_DBGBCR11;
142  case 12:
143  return MISCREG_DBGBCR12;
144  case 13:
145  return MISCREG_DBGBCR13;
146  case 14:
147  return MISCREG_DBGBCR14;
148  case 15:
149  return MISCREG_DBGBCR15;
150  }
151  break;
152  case 6:
153  switch (crm) {
154  case 0:
155  return MISCREG_DBGWVR0;
156  case 1:
157  return MISCREG_DBGWVR1;
158  case 2:
159  return MISCREG_DBGWVR2;
160  case 3:
161  return MISCREG_DBGWVR3;
162  case 4:
163  return MISCREG_DBGWVR4;
164  case 5:
165  return MISCREG_DBGWVR5;
166  case 6:
167  return MISCREG_DBGWVR6;
168  case 7:
169  return MISCREG_DBGWVR7;
170  case 8:
171  return MISCREG_DBGWVR8;
172  case 9:
173  return MISCREG_DBGWVR9;
174  case 10:
175  return MISCREG_DBGWVR10;
176  case 11:
177  return MISCREG_DBGWVR11;
178  case 12:
179  return MISCREG_DBGWVR12;
180  case 13:
181  return MISCREG_DBGWVR13;
182  case 14:
183  return MISCREG_DBGWVR14;
184  case 15:
185  return MISCREG_DBGWVR15;
186  break;
187  }
188  break;
189  case 7:
190  switch (crm) {
191  case 0:
192  return MISCREG_DBGWCR0;
193  case 1:
194  return MISCREG_DBGWCR1;
195  case 2:
196  return MISCREG_DBGWCR2;
197  case 3:
198  return MISCREG_DBGWCR3;
199  case 4:
200  return MISCREG_DBGWCR4;
201  case 5:
202  return MISCREG_DBGWCR5;
203  case 6:
204  return MISCREG_DBGWCR6;
205  case 7:
206  return MISCREG_DBGWCR7;
207  case 8:
208  return MISCREG_DBGWCR8;
209  case 9:
210  return MISCREG_DBGWCR9;
211  case 10:
212  return MISCREG_DBGWCR10;
213  case 11:
214  return MISCREG_DBGWCR11;
215  case 12:
216  return MISCREG_DBGWCR12;
217  case 13:
218  return MISCREG_DBGWCR13;
219  case 14:
220  return MISCREG_DBGWCR14;
221  case 15:
222  return MISCREG_DBGWCR15;
223  }
224  break;
225  }
226  break;
227  case 7:
228  switch (opc2) {
229  case 0:
230  switch (crm) {
231  case 0:
232  return MISCREG_JIDR;
233  }
234  break;
235  }
236  break;
237  }
238  break;
239  case 1:
240  switch (opc1) {
241  case 0:
242  switch(opc2) {
243  case 1:
244  switch(crm) {
245  case 0:
246  return MISCREG_DBGBXVR0;
247  case 1:
248  return MISCREG_DBGBXVR1;
249  case 2:
250  return MISCREG_DBGBXVR2;
251  case 3:
252  return MISCREG_DBGBXVR3;
253  case 4:
254  return MISCREG_DBGBXVR4;
255  case 5:
256  return MISCREG_DBGBXVR5;
257  case 6:
258  return MISCREG_DBGBXVR6;
259  case 7:
260  return MISCREG_DBGBXVR7;
261  case 8:
262  return MISCREG_DBGBXVR8;
263  case 9:
264  return MISCREG_DBGBXVR9;
265  case 10:
266  return MISCREG_DBGBXVR10;
267  case 11:
268  return MISCREG_DBGBXVR11;
269  case 12:
270  return MISCREG_DBGBXVR12;
271  case 13:
272  return MISCREG_DBGBXVR13;
273  case 14:
274  return MISCREG_DBGBXVR14;
275  case 15:
276  return MISCREG_DBGBXVR15;
277  }
278  break;
279  case 4:
280  switch (crm) {
281  case 0:
282  return MISCREG_DBGOSLAR;
283  case 1:
284  return MISCREG_DBGOSLSR;
285  case 3:
286  return MISCREG_DBGOSDLR;
287  case 4:
288  return MISCREG_DBGPRCR;
289  }
290  break;
291  }
292  break;
293  case 6:
294  switch (crm) {
295  case 0:
296  switch (opc2) {
297  case 0:
298  return MISCREG_TEEHBR;
299  }
300  break;
301  }
302  break;
303  case 7:
304  switch (crm) {
305  case 0:
306  switch (opc2) {
307  case 0:
308  return MISCREG_JOSCR;
309  }
310  break;
311  }
312  break;
313  }
314  break;
315  case 2:
316  switch (opc1) {
317  case 7:
318  switch (crm) {
319  case 0:
320  switch (opc2) {
321  case 0:
322  return MISCREG_JMCR;
323  }
324  break;
325  }
326  break;
327  }
328  break;
329  }
330  // If we get here then it must be a register that we haven't implemented
331  warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
332  crn, opc1, crm, opc2);
333  return MISCREG_CP14_UNIMPL;
334 }
335 
336 using namespace std;
337 
338 MiscRegIndex
339 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
340 {
341  switch (crn) {
342  case 0:
343  switch (opc1) {
344  case 0:
345  switch (crm) {
346  case 0:
347  switch (opc2) {
348  case 1:
349  return MISCREG_CTR;
350  case 2:
351  return MISCREG_TCMTR;
352  case 3:
353  return MISCREG_TLBTR;
354  case 5:
355  return MISCREG_MPIDR;
356  case 6:
357  return MISCREG_REVIDR;
358  default:
359  return MISCREG_MIDR;
360  }
361  break;
362  case 1:
363  switch (opc2) {
364  case 0:
365  return MISCREG_ID_PFR0;
366  case 1:
367  return MISCREG_ID_PFR1;
368  case 2:
369  return MISCREG_ID_DFR0;
370  case 3:
371  return MISCREG_ID_AFR0;
372  case 4:
373  return MISCREG_ID_MMFR0;
374  case 5:
375  return MISCREG_ID_MMFR1;
376  case 6:
377  return MISCREG_ID_MMFR2;
378  case 7:
379  return MISCREG_ID_MMFR3;
380  }
381  break;
382  case 2:
383  switch (opc2) {
384  case 0:
385  return MISCREG_ID_ISAR0;
386  case 1:
387  return MISCREG_ID_ISAR1;
388  case 2:
389  return MISCREG_ID_ISAR2;
390  case 3:
391  return MISCREG_ID_ISAR3;
392  case 4:
393  return MISCREG_ID_ISAR4;
394  case 5:
395  return MISCREG_ID_ISAR5;
396  case 6:
397  case 7:
398  return MISCREG_RAZ; // read as zero
399  }
400  break;
401  default:
402  return MISCREG_RAZ; // read as zero
403  }
404  break;
405  case 1:
406  if (crm == 0) {
407  switch (opc2) {
408  case 0:
409  return MISCREG_CCSIDR;
410  case 1:
411  return MISCREG_CLIDR;
412  case 7:
413  return MISCREG_AIDR;
414  }
415  }
416  break;
417  case 2:
418  if (crm == 0 && opc2 == 0) {
419  return MISCREG_CSSELR;
420  }
421  break;
422  case 4:
423  if (crm == 0) {
424  if (opc2 == 0)
425  return MISCREG_VPIDR;
426  else if (opc2 == 5)
427  return MISCREG_VMPIDR;
428  }
429  break;
430  }
431  break;
432  case 1:
433  if (opc1 == 0) {
434  if (crm == 0) {
435  switch (opc2) {
436  case 0:
437  return MISCREG_SCTLR;
438  case 1:
439  return MISCREG_ACTLR;
440  case 0x2:
441  return MISCREG_CPACR;
442  }
443  } else if (crm == 1) {
444  switch (opc2) {
445  case 0:
446  return MISCREG_SCR;
447  case 1:
448  return MISCREG_SDER;
449  case 2:
450  return MISCREG_NSACR;
451  }
452  } else if (crm == 3) {
453  if ( opc2 == 1)
454  return MISCREG_SDCR;
455  }
456  } else if (opc1 == 4) {
457  if (crm == 0) {
458  if (opc2 == 0)
459  return MISCREG_HSCTLR;
460  else if (opc2 == 1)
461  return MISCREG_HACTLR;
462  } else if (crm == 1) {
463  switch (opc2) {
464  case 0:
465  return MISCREG_HCR;
466  case 1:
467  return MISCREG_HDCR;
468  case 2:
469  return MISCREG_HCPTR;
470  case 4:
471  return MISCREG_HCR2;
472  case 3:
473  return MISCREG_HSTR;
474  case 7:
475  return MISCREG_HACR;
476  }
477  }
478  }
479  break;
480  case 2:
481  if (opc1 == 0 && crm == 0) {
482  switch (opc2) {
483  case 0:
484  return MISCREG_TTBR0;
485  case 1:
486  return MISCREG_TTBR1;
487  case 2:
488  return MISCREG_TTBCR;
489  }
490  } else if (opc1 == 4) {
491  if (crm == 0 && opc2 == 2)
492  return MISCREG_HTCR;
493  else if (crm == 1 && opc2 == 2)
494  return MISCREG_VTCR;
495  }
496  break;
497  case 3:
498  if (opc1 == 0 && crm == 0 && opc2 == 0) {
499  return MISCREG_DACR;
500  }
501  break;
502  case 4:
503  if (opc1 == 0 && crm == 6 && opc2 == 0) {
504  return MISCREG_ICC_PMR;
505  }
506  break;
507  case 5:
508  if (opc1 == 0) {
509  if (crm == 0) {
510  if (opc2 == 0) {
511  return MISCREG_DFSR;
512  } else if (opc2 == 1) {
513  return MISCREG_IFSR;
514  }
515  } else if (crm == 1) {
516  if (opc2 == 0) {
517  return MISCREG_ADFSR;
518  } else if (opc2 == 1) {
519  return MISCREG_AIFSR;
520  }
521  }
522  } else if (opc1 == 4) {
523  if (crm == 1) {
524  if (opc2 == 0)
525  return MISCREG_HADFSR;
526  else if (opc2 == 1)
527  return MISCREG_HAIFSR;
528  } else if (crm == 2 && opc2 == 0) {
529  return MISCREG_HSR;
530  }
531  }
532  break;
533  case 6:
534  if (opc1 == 0 && crm == 0) {
535  switch (opc2) {
536  case 0:
537  return MISCREG_DFAR;
538  case 2:
539  return MISCREG_IFAR;
540  }
541  } else if (opc1 == 4 && crm == 0) {
542  switch (opc2) {
543  case 0:
544  return MISCREG_HDFAR;
545  case 2:
546  return MISCREG_HIFAR;
547  case 4:
548  return MISCREG_HPFAR;
549  }
550  }
551  break;
552  case 7:
553  if (opc1 == 0) {
554  switch (crm) {
555  case 0:
556  if (opc2 == 4) {
557  return MISCREG_NOP;
558  }
559  break;
560  case 1:
561  switch (opc2) {
562  case 0:
563  return MISCREG_ICIALLUIS;
564  case 6:
565  return MISCREG_BPIALLIS;
566  }
567  break;
568  case 2:
569  switch (opc2) {
570  case 7:
571  return MISCREG_DBGDEVID0;
572  }
573  break;
574  case 4:
575  if (opc2 == 0) {
576  return MISCREG_PAR;
577  }
578  break;
579  case 5:
580  switch (opc2) {
581  case 0:
582  return MISCREG_ICIALLU;
583  case 1:
584  return MISCREG_ICIMVAU;
585  case 4:
586  return MISCREG_CP15ISB;
587  case 6:
588  return MISCREG_BPIALL;
589  case 7:
590  return MISCREG_BPIMVA;
591  }
592  break;
593  case 6:
594  if (opc2 == 1) {
595  return MISCREG_DCIMVAC;
596  } else if (opc2 == 2) {
597  return MISCREG_DCISW;
598  }
599  break;
600  case 8:
601  switch (opc2) {
602  case 0:
603  return MISCREG_ATS1CPR;
604  case 1:
605  return MISCREG_ATS1CPW;
606  case 2:
607  return MISCREG_ATS1CUR;
608  case 3:
609  return MISCREG_ATS1CUW;
610  case 4:
611  return MISCREG_ATS12NSOPR;
612  case 5:
613  return MISCREG_ATS12NSOPW;
614  case 6:
615  return MISCREG_ATS12NSOUR;
616  case 7:
617  return MISCREG_ATS12NSOUW;
618  }
619  break;
620  case 10:
621  switch (opc2) {
622  case 1:
623  return MISCREG_DCCMVAC;
624  case 2:
625  return MISCREG_DCCSW;
626  case 4:
627  return MISCREG_CP15DSB;
628  case 5:
629  return MISCREG_CP15DMB;
630  }
631  break;
632  case 11:
633  if (opc2 == 1) {
634  return MISCREG_DCCMVAU;
635  }
636  break;
637  case 13:
638  if (opc2 == 1) {
639  return MISCREG_NOP;
640  }
641  break;
642  case 14:
643  if (opc2 == 1) {
644  return MISCREG_DCCIMVAC;
645  } else if (opc2 == 2) {
646  return MISCREG_DCCISW;
647  }
648  break;
649  }
650  } else if (opc1 == 4 && crm == 8) {
651  if (opc2 == 0)
652  return MISCREG_ATS1HR;
653  else if (opc2 == 1)
654  return MISCREG_ATS1HW;
655  }
656  break;
657  case 8:
658  if (opc1 == 0) {
659  switch (crm) {
660  case 3:
661  switch (opc2) {
662  case 0:
663  return MISCREG_TLBIALLIS;
664  case 1:
665  return MISCREG_TLBIMVAIS;
666  case 2:
667  return MISCREG_TLBIASIDIS;
668  case 3:
669  return MISCREG_TLBIMVAAIS;
670  case 5:
671  return MISCREG_TLBIMVALIS;
672  case 7:
673  return MISCREG_TLBIMVAALIS;
674  }
675  break;
676  case 5:
677  switch (opc2) {
678  case 0:
679  return MISCREG_ITLBIALL;
680  case 1:
681  return MISCREG_ITLBIMVA;
682  case 2:
683  return MISCREG_ITLBIASID;
684  }
685  break;
686  case 6:
687  switch (opc2) {
688  case 0:
689  return MISCREG_DTLBIALL;
690  case 1:
691  return MISCREG_DTLBIMVA;
692  case 2:
693  return MISCREG_DTLBIASID;
694  }
695  break;
696  case 7:
697  switch (opc2) {
698  case 0:
699  return MISCREG_TLBIALL;
700  case 1:
701  return MISCREG_TLBIMVA;
702  case 2:
703  return MISCREG_TLBIASID;
704  case 3:
705  return MISCREG_TLBIMVAA;
706  case 5:
707  return MISCREG_TLBIMVAL;
708  case 7:
709  return MISCREG_TLBIMVAAL;
710  }
711  break;
712  }
713  } else if (opc1 == 4) {
714  if (crm == 0) {
715  switch (opc2) {
716  case 1:
717  return MISCREG_TLBIIPAS2IS;
718  case 5:
719  return MISCREG_TLBIIPAS2LIS;
720  }
721  } else if (crm == 3) {
722  switch (opc2) {
723  case 0:
724  return MISCREG_TLBIALLHIS;
725  case 1:
726  return MISCREG_TLBIMVAHIS;
727  case 4:
728  return MISCREG_TLBIALLNSNHIS;
729  case 5:
730  return MISCREG_TLBIMVALHIS;
731  }
732  } else if (crm == 4) {
733  switch (opc2) {
734  case 1:
735  return MISCREG_TLBIIPAS2;
736  case 5:
737  return MISCREG_TLBIIPAS2L;
738  }
739  } else if (crm == 7) {
740  switch (opc2) {
741  case 0:
742  return MISCREG_TLBIALLH;
743  case 1:
744  return MISCREG_TLBIMVAH;
745  case 4:
746  return MISCREG_TLBIALLNSNH;
747  case 5:
748  return MISCREG_TLBIMVALH;
749  }
750  }
751  }
752  break;
753  case 9:
754  // Every cop register with CRn = 9 and CRm in
755  // {0-2}, {5-8} is implementation defined regardless
756  // of opc1 and opc2.
757  switch (crm) {
758  case 0:
759  case 1:
760  case 2:
761  case 5:
762  case 6:
763  case 7:
764  case 8:
765  return MISCREG_IMPDEF_UNIMPL;
766  }
767  if (opc1 == 0) {
768  switch (crm) {
769  case 12:
770  switch (opc2) {
771  case 0:
772  return MISCREG_PMCR;
773  case 1:
774  return MISCREG_PMCNTENSET;
775  case 2:
776  return MISCREG_PMCNTENCLR;
777  case 3:
778  return MISCREG_PMOVSR;
779  case 4:
780  return MISCREG_PMSWINC;
781  case 5:
782  return MISCREG_PMSELR;
783  case 6:
784  return MISCREG_PMCEID0;
785  case 7:
786  return MISCREG_PMCEID1;
787  }
788  break;
789  case 13:
790  switch (opc2) {
791  case 0:
792  return MISCREG_PMCCNTR;
793  case 1:
794  // Selector is PMSELR.SEL
795  return MISCREG_PMXEVTYPER_PMCCFILTR;
796  case 2:
797  return MISCREG_PMXEVCNTR;
798  }
799  break;
800  case 14:
801  switch (opc2) {
802  case 0:
803  return MISCREG_PMUSERENR;
804  case 1:
805  return MISCREG_PMINTENSET;
806  case 2:
807  return MISCREG_PMINTENCLR;
808  case 3:
809  return MISCREG_PMOVSSET;
810  }
811  break;
812  }
813  } else if (opc1 == 1) {
814  switch (crm) {
815  case 0:
816  switch (opc2) {
817  case 2: // L2CTLR, L2 Control Register
818  return MISCREG_L2CTLR;
819  case 3:
820  return MISCREG_L2ECTLR;
821  }
822  break;
823  break;
824  }
825  }
826  break;
827  case 10:
828  if (opc1 == 0) {
829  // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
830  if (crm < 2) {
831  return MISCREG_IMPDEF_UNIMPL;
832  } else if (crm == 2) { // TEX Remap Registers
833  if (opc2 == 0) {
834  // Selector is TTBCR.EAE
835  return MISCREG_PRRR_MAIR0;
836  } else if (opc2 == 1) {
837  // Selector is TTBCR.EAE
838  return MISCREG_NMRR_MAIR1;
839  }
840  } else if (crm == 3) {
841  if (opc2 == 0) {
842  return MISCREG_AMAIR0;
843  } else if (opc2 == 1) {
844  return MISCREG_AMAIR1;
845  }
846  }
847  } else if (opc1 == 4) {
848  // crm 0, 1, 4, and 8, with op2 0 - 7, reserved for TLB lockdown
849  if (crm == 2) {
850  if (opc2 == 0)
851  return MISCREG_HMAIR0;
852  else if (opc2 == 1)
853  return MISCREG_HMAIR1;
854  } else if (crm == 3) {
855  if (opc2 == 0)
856  return MISCREG_HAMAIR0;
857  else if (opc2 == 1)
858  return MISCREG_HAMAIR1;
859  }
860  }
861  break;
862  case 11:
863  if (opc1 <=7) {
864  switch (crm) {
865  case 0:
866  case 1:
867  case 2:
868  case 3:
869  case 4:
870  case 5:
871  case 6:
872  case 7:
873  case 8:
874  case 15:
875  // Reserved for DMA operations for TCM access
876  return MISCREG_IMPDEF_UNIMPL;
877  default:
878  break;
879  }
880  }
881  break;
882  case 12:
883  if (opc1 == 0) {
884  if (crm == 0) {
885  if (opc2 == 0) {
886  return MISCREG_VBAR;
887  } else if (opc2 == 1) {
888  return MISCREG_MVBAR;
889  }
890  } else if (crm == 1) {
891  if (opc2 == 0) {
892  return MISCREG_ISR;
893  }
894  } else if (crm == 8) {
895  switch (opc2) {
896  case 0:
897  return MISCREG_ICC_IAR0;
898  case 1:
899  return MISCREG_ICC_EOIR0;
900  case 2:
901  return MISCREG_ICC_HPPIR0;
902  case 3:
903  return MISCREG_ICC_BPR0;
904  case 4:
905  return MISCREG_ICC_AP0R0;
906  case 5:
907  return MISCREG_ICC_AP0R1;
908  case 6:
909  return MISCREG_ICC_AP0R2;
910  case 7:
911  return MISCREG_ICC_AP0R3;
912  }
913  } else if (crm == 9) {
914  switch (opc2) {
915  case 0:
916  return MISCREG_ICC_AP1R0;
917  case 1:
918  return MISCREG_ICC_AP1R1;
919  case 2:
920  return MISCREG_ICC_AP1R2;
921  case 3:
922  return MISCREG_ICC_AP1R3;
923  }
924  } else if (crm == 11) {
925  switch (opc2) {
926  case 1:
927  return MISCREG_ICC_DIR;
928  case 3:
929  return MISCREG_ICC_RPR;
930  }
931  } else if (crm == 12) {
932  switch (opc2) {
933  case 0:
934  return MISCREG_ICC_IAR1;
935  case 1:
936  return MISCREG_ICC_EOIR1;
937  case 2:
938  return MISCREG_ICC_HPPIR1;
939  case 3:
940  return MISCREG_ICC_BPR1;
941  case 4:
942  return MISCREG_ICC_CTLR;
943  case 5:
944  return MISCREG_ICC_SRE;
945  case 6:
946  return MISCREG_ICC_IGRPEN0;
947  case 7:
948  return MISCREG_ICC_IGRPEN1;
949  }
950  }
951  } else if (opc1 == 4) {
952  if (crm == 0 && opc2 == 0) {
953  return MISCREG_HVBAR;
954  } else if (crm == 8) {
955  switch (opc2) {
956  case 0:
957  return MISCREG_ICH_AP0R0;
958  case 1:
959  return MISCREG_ICH_AP0R1;
960  case 2:
961  return MISCREG_ICH_AP0R2;
962  case 3:
963  return MISCREG_ICH_AP0R3;
964  }
965  } else if (crm == 9) {
966  switch (opc2) {
967  case 0:
968  return MISCREG_ICH_AP1R0;
969  case 1:
970  return MISCREG_ICH_AP1R1;
971  case 2:
972  return MISCREG_ICH_AP1R2;
973  case 3:
974  return MISCREG_ICH_AP1R3;
975  case 5:
976  return MISCREG_ICC_HSRE;
977  }
978  } else if (crm == 11) {
979  switch (opc2) {
980  case 0:
981  return MISCREG_ICH_HCR;
982  case 1:
983  return MISCREG_ICH_VTR;
984  case 2:
985  return MISCREG_ICH_MISR;
986  case 3:
987  return MISCREG_ICH_EISR;
988  case 5:
989  return MISCREG_ICH_ELRSR;
990  case 7:
991  return MISCREG_ICH_VMCR;
992  }
993  } else if (crm == 12) {
994  switch (opc2) {
995  case 0:
996  return MISCREG_ICH_LR0;
997  case 1:
998  return MISCREG_ICH_LR1;
999  case 2:
1000  return MISCREG_ICH_LR2;
1001  case 3:
1002  return MISCREG_ICH_LR3;
1003  case 4:
1004  return MISCREG_ICH_LR4;
1005  case 5:
1006  return MISCREG_ICH_LR5;
1007  case 6:
1008  return MISCREG_ICH_LR6;
1009  case 7:
1010  return MISCREG_ICH_LR7;
1011  }
1012  } else if (crm == 13) {
1013  switch (opc2) {
1014  case 0:
1015  return MISCREG_ICH_LR8;
1016  case 1:
1017  return MISCREG_ICH_LR9;
1018  case 2:
1019  return MISCREG_ICH_LR10;
1020  case 3:
1021  return MISCREG_ICH_LR11;
1022  case 4:
1023  return MISCREG_ICH_LR12;
1024  case 5:
1025  return MISCREG_ICH_LR13;
1026  case 6:
1027  return MISCREG_ICH_LR14;
1028  case 7:
1029  return MISCREG_ICH_LR15;
1030  }
1031  } else if (crm == 14) {
1032  switch (opc2) {
1033  case 0:
1034  return MISCREG_ICH_LRC0;
1035  case 1:
1036  return MISCREG_ICH_LRC1;
1037  case 2:
1038  return MISCREG_ICH_LRC2;
1039  case 3:
1040  return MISCREG_ICH_LRC3;
1041  case 4:
1042  return MISCREG_ICH_LRC4;
1043  case 5:
1044  return MISCREG_ICH_LRC5;
1045  case 6:
1046  return MISCREG_ICH_LRC6;
1047  case 7:
1048  return MISCREG_ICH_LRC7;
1049  }
1050  } else if (crm == 15) {
1051  switch (opc2) {
1052  case 0:
1053  return MISCREG_ICH_LRC8;
1054  case 1:
1055  return MISCREG_ICH_LRC9;
1056  case 2:
1057  return MISCREG_ICH_LRC10;
1058  case 3:
1059  return MISCREG_ICH_LRC11;
1060  case 4:
1061  return MISCREG_ICH_LRC12;
1062  case 5:
1063  return MISCREG_ICH_LRC13;
1064  case 6:
1065  return MISCREG_ICH_LRC14;
1066  case 7:
1067  return MISCREG_ICH_LRC15;
1068  }
1069  }
1070  } else if (opc1 == 6) {
1071  if (crm == 12) {
1072  switch (opc2) {
1073  case 4:
1074  return MISCREG_ICC_MCTLR;
1075  case 5:
1076  return MISCREG_ICC_MSRE;
1077  case 7:
1078  return MISCREG_ICC_MGRPEN1;
1079  }
1080  }
1081  }
1082  break;
1083  case 13:
1084  if (opc1 == 0) {
1085  if (crm == 0) {
1086  switch (opc2) {
1087  case 0:
1088  return MISCREG_FCSEIDR;
1089  case 1:
1090  return MISCREG_CONTEXTIDR;
1091  case 2:
1092  return MISCREG_TPIDRURW;
1093  case 3:
1094  return MISCREG_TPIDRURO;
1095  case 4:
1096  return MISCREG_TPIDRPRW;
1097  }
1098  }
1099  } else if (opc1 == 4) {
1100  if (crm == 0 && opc2 == 2)
1101  return MISCREG_HTPIDR;
1102  }
1103  break;
1104  case 14:
1105  if (opc1 == 0) {
1106  switch (crm) {
1107  case 0:
1108  if (opc2 == 0)
1109  return MISCREG_CNTFRQ;
1110  break;
1111  case 1:
1112  if (opc2 == 0)
1113  return MISCREG_CNTKCTL;
1114  break;
1115  case 2:
1116  if (opc2 == 0)
1117  return MISCREG_CNTP_TVAL;
1118  else if (opc2 == 1)
1119  return MISCREG_CNTP_CTL;
1120  break;
1121  case 3:
1122  if (opc2 == 0)
1123  return MISCREG_CNTV_TVAL;
1124  else if (opc2 == 1)
1125  return MISCREG_CNTV_CTL;
1126  break;
1127  }
1128  } else if (opc1 == 4) {
1129  if (crm == 1 && opc2 == 0) {
1130  return MISCREG_CNTHCTL;
1131  } else if (crm == 2) {
1132  if (opc2 == 0)
1133  return MISCREG_CNTHP_TVAL;
1134  else if (opc2 == 1)
1135  return MISCREG_CNTHP_CTL;
1136  }
1137  }
1138  break;
1139  case 15:
1140  // Implementation defined
1141  return MISCREG_IMPDEF_UNIMPL;
1142  }
1143  // Unrecognized register
1144  return MISCREG_CP15_UNIMPL;
1145 }
1146 
1147 MiscRegIndex
1148 decodeCP15Reg64(unsigned crm, unsigned opc1)
1149 {
1150  switch (crm) {
1151  case 2:
1152  switch (opc1) {
1153  case 0:
1154  return MISCREG_TTBR0;
1155  case 1:
1156  return MISCREG_TTBR1;
1157  case 4:
1158  return MISCREG_HTTBR;
1159  case 6:
1160  return MISCREG_VTTBR;
1161  }
1162  break;
1163  case 7:
1164  if (opc1 == 0)
1165  return MISCREG_PAR;
1166  break;
1167  case 14:
1168  switch (opc1) {
1169  case 0:
1170  return MISCREG_CNTPCT;
1171  case 1:
1172  return MISCREG_CNTVCT;
1173  case 2:
1174  return MISCREG_CNTP_CVAL;
1175  case 3:
1176  return MISCREG_CNTV_CVAL;
1177  case 4:
1178  return MISCREG_CNTVOFF;
1179  case 6:
1180  return MISCREG_CNTHP_CVAL;
1181  }
1182  break;
1183  case 12:
1184  switch (opc1) {
1185  case 0:
1186  return MISCREG_ICC_SGI1R;
1187  case 1:
1188  return MISCREG_ICC_ASGI1R;
1189  case 2:
1190  return MISCREG_ICC_SGI0R;
1191  default:
1192  break;
1193  }
1194  break;
1195  case 15:
1196  if (opc1 == 0)
1197  return MISCREG_CPUMERRSR;
1198  else if (opc1 == 1)
1199  return MISCREG_L2MERRSR;
1200  break;
1201  }
1202  // Unrecognized register
1203  return MISCREG_CP15_UNIMPL;
1204 }
1205 
1206 std::tuple<bool, bool>
1207 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1208 {
1209  bool secure = !scr.ns;
1210  bool canRead = false;
1211  bool undefined = false;
1212 
1213  switch (cpsr.mode) {
1214  case MODE_USER:
1215  canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1216  miscRegInfo[reg][MISCREG_USR_NS_RD];
1217  break;
1218  case MODE_FIQ:
1219  case MODE_IRQ:
1220  case MODE_SVC:
1221  case MODE_ABORT:
1222  case MODE_UNDEFINED:
1223  case MODE_SYSTEM:
1224  canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1225  miscRegInfo[reg][MISCREG_PRI_NS_RD];
1226  break;
1227  case MODE_MON:
1228  canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1229  miscRegInfo[reg][MISCREG_MON_NS1_RD];
1230  break;
1231  case MODE_HYP:
1232  canRead = miscRegInfo[reg][MISCREG_HYP_RD];
1233  break;
1234  default:
1235  undefined = true;
1236  }
1237 
1238  switch (reg) {
1239  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1240  if (!undefined)
1241  undefined = AArch32isUndefinedGenericTimer(reg, tc);
1242  break;
1243  default:
1244  break;
1245  }
1246 
1247  // can't do permissions checkes on the root of a banked pair of regs
1248  assert(!miscRegInfo[reg][MISCREG_BANKED]);
1249  return std::make_tuple(canRead, undefined);
1250 }
1251 
1252 std::tuple<bool, bool>
1253 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1254 {
1255  bool secure = !scr.ns;
1256  bool canWrite = false;
1257  bool undefined = false;
1258 
1259  switch (cpsr.mode) {
1260  case MODE_USER:
1261  canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1262  miscRegInfo[reg][MISCREG_USR_NS_WR];
1263  break;
1264  case MODE_FIQ:
1265  case MODE_IRQ:
1266  case MODE_SVC:
1267  case MODE_ABORT:
1268  case MODE_UNDEFINED:
1269  case MODE_SYSTEM:
1270  canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1271  miscRegInfo[reg][MISCREG_PRI_NS_WR];
1272  break;
1273  case MODE_MON:
1274  canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1275  miscRegInfo[reg][MISCREG_MON_NS1_WR];
1276  break;
1277  case MODE_HYP:
1278  canWrite = miscRegInfo[reg][MISCREG_HYP_WR];
1279  break;
1280  default:
1281  undefined = true;
1282  }
1283 
1284  switch (reg) {
1285  case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
1286  if (!undefined)
1287  undefined = AArch32isUndefinedGenericTimer(reg, tc);
1288  break;
1289  default:
1290  break;
1291  }
1292 
1293  // can't do permissions checkes on the root of a banked pair of regs
1294  assert(!miscRegInfo[reg][MISCREG_BANKED]);
1295  return std::make_tuple(canWrite, undefined);
1296 }
1297 
1298 bool
1299 AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
1300 {
1301  if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
1302  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1303  bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
1304  if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
1305  return true;
1306  }
1307  return false;
1308 }
1309 
1310 int
1311 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
1312 {
1313  SCR scr = tc->readMiscReg(MISCREG_SCR);
1314  return snsBankedIndex(reg, tc, scr.ns);
1315 }
1316 
1317 int
1318 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
1319 {
1320  int reg_as_int = static_cast<int>(reg);
1321  if (miscRegInfo[reg][MISCREG_BANKED]) {
1322  reg_as_int += (ArmSystem::haveSecurity(tc) &&
1323  !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
1324  }
1325  return reg_as_int;
1326 }
1327 
1328 int
1329 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
1330 {
1331  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
1332  SCR scr = tc->readMiscReg(MISCREG_SCR);
1333  return isa->snsBankedIndex64(reg, scr.ns);
1334 }
1335 
1344 int unflattenResultMiscReg[NUM_MISCREGS];
1345 
1346 void
1347 preUnflattenMiscReg()
1348 {
1349  int reg = -1;
1350  for (int i = 0 ; i < NUM_MISCREGS; i++){
1351  if (miscRegInfo[i][MISCREG_BANKED])
1352  reg = i;
1353  if (miscRegInfo[i][MISCREG_BANKED_CHILD])
1354  unflattenResultMiscReg[i] = reg;
1355  else
1356  unflattenResultMiscReg[i] = i;
1357  // if this assert fails, no parent was found, and something is broken
1358  assert(unflattenResultMiscReg[i] > -1);
1359  }
1360 }
1361 
1362 int
1363 unflattenMiscReg(int reg)
1364 {
1365  return unflattenResultMiscReg[reg];
1366 }
1367 
1368 bool
1369 canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1370  ThreadContext *tc)
1371 {
1372  // Check for SP_EL0 access while SPSEL == 0
1373  if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1374  return false;
1375 
1376  // Check for RVBAR access
1377  if (reg == MISCREG_RVBAR_EL1) {
1378  ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1379  if (highest_el == EL2 || highest_el == EL3)
1380  return false;
1381  }
1382  if (reg == MISCREG_RVBAR_EL2) {
1383  ExceptionLevel highest_el = ArmSystem::highestEL(tc);
1384  if (highest_el == EL3)
1385  return false;
1386  }
1387 
1388  bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1389  bool el2_host = EL2Enabled(tc) && hcr.e2h;
1390 
1391  switch (currEL(cpsr)) {
1392  case EL0:
1393  return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
1394  miscRegInfo[reg][MISCREG_USR_NS_RD];
1395  case EL1:
1396  return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
1397  miscRegInfo[reg][MISCREG_PRI_NS_RD];
1398  case EL2:
1399  return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_RD] :
1400  miscRegInfo[reg][MISCREG_HYP_RD];
1401  case EL3:
1402  return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
1403  secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
1404  miscRegInfo[reg][MISCREG_MON_NS1_RD];
1405  default:
1406  panic("Invalid exception level");
1407  }
1408 }
1409 
1410 bool
1411 canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1412  ThreadContext *tc)
1413 {
1414  // Check for SP_EL0 access while SPSEL == 0
1415  if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
1416  return false;
1417  ExceptionLevel el = currEL(cpsr);
1418 
1419  bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
1420  bool el2_host = EL2Enabled(tc) && hcr.e2h;
1421 
1422  switch (el) {
1423  case EL0:
1424  return secure ? miscRegInfo[reg][MISCREG_USR_S_WR] :
1425  miscRegInfo[reg][MISCREG_USR_NS_WR];
1426  case EL1:
1427  return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
1428  miscRegInfo[reg][MISCREG_PRI_NS_WR];
1429  case EL2:
1430  return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
1431  miscRegInfo[reg][MISCREG_HYP_WR];
1432  case EL3:
1433  return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
1434  secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
1435  miscRegInfo[reg][MISCREG_MON_NS1_WR];
1436  default:
1437  panic("Invalid exception level");
1438  }
1439 }
1440 
1441 MiscRegIndex
1442 decodeAArch64SysReg(unsigned op0, unsigned op1,
1443  unsigned crn, unsigned crm,
1444  unsigned op2)
1445 {
1446  switch (op0) {
1447  case 1:
1448  switch (crn) {
1449  case 7:
1450  switch (op1) {
1451  case 0:
1452  switch (crm) {
1453  case 1:
1454  switch (op2) {
1455  case 0:
1456  return MISCREG_IC_IALLUIS;
1457  }
1458  break;
1459  case 5:
1460  switch (op2) {
1461  case 0:
1462  return MISCREG_IC_IALLU;
1463  }
1464  break;
1465  case 6:
1466  switch (op2) {
1467  case 1:
1468  return MISCREG_DC_IVAC_Xt;
1469  case 2:
1470  return MISCREG_DC_ISW_Xt;
1471  }
1472  break;
1473  case 8:
1474  switch (op2) {
1475  case 0:
1476  return MISCREG_AT_S1E1R_Xt;
1477  case 1:
1478  return MISCREG_AT_S1E1W_Xt;
1479  case 2:
1480  return MISCREG_AT_S1E0R_Xt;
1481  case 3:
1482  return MISCREG_AT_S1E0W_Xt;
1483  }
1484  break;
1485  case 10:
1486  switch (op2) {
1487  case 2:
1488  return MISCREG_DC_CSW_Xt;
1489  }
1490  break;
1491  case 14:
1492  switch (op2) {
1493  case 2:
1494  return MISCREG_DC_CISW_Xt;
1495  }
1496  break;
1497  }
1498  break;
1499  case 3:
1500  switch (crm) {
1501  case 4:
1502  switch (op2) {
1503  case 1:
1504  return MISCREG_DC_ZVA_Xt;
1505  }
1506  break;
1507  case 5:
1508  switch (op2) {
1509  case 1:
1510  return MISCREG_IC_IVAU_Xt;
1511  }
1512  break;
1513  case 10:
1514  switch (op2) {
1515  case 1:
1516  return MISCREG_DC_CVAC_Xt;
1517  }
1518  break;
1519  case 11:
1520  switch (op2) {
1521  case 1:
1522  return MISCREG_DC_CVAU_Xt;
1523  }
1524  break;
1525  case 14:
1526  switch (op2) {
1527  case 1:
1528  return MISCREG_DC_CIVAC_Xt;
1529  }
1530  break;
1531  }
1532  break;
1533  case 4:
1534  switch (crm) {
1535  case 8:
1536  switch (op2) {
1537  case 0:
1538  return MISCREG_AT_S1E2R_Xt;
1539  case 1:
1540  return MISCREG_AT_S1E2W_Xt;
1541  case 4:
1542  return MISCREG_AT_S12E1R_Xt;
1543  case 5:
1544  return MISCREG_AT_S12E1W_Xt;
1545  case 6:
1546  return MISCREG_AT_S12E0R_Xt;
1547  case 7:
1548  return MISCREG_AT_S12E0W_Xt;
1549  }
1550  break;
1551  }
1552  break;
1553  case 6:
1554  switch (crm) {
1555  case 8:
1556  switch (op2) {
1557  case 0:
1558  return MISCREG_AT_S1E3R_Xt;
1559  case 1:
1560  return MISCREG_AT_S1E3W_Xt;
1561  }
1562  break;
1563  }
1564  break;
1565  }
1566  break;
1567  case 8:
1568  switch (op1) {
1569  case 0:
1570  switch (crm) {
1571  case 3:
1572  switch (op2) {
1573  case 0:
1574  return MISCREG_TLBI_VMALLE1IS;
1575  case 1:
1576  return MISCREG_TLBI_VAE1IS_Xt;
1577  case 2:
1578  return MISCREG_TLBI_ASIDE1IS_Xt;
1579  case 3:
1580  return MISCREG_TLBI_VAAE1IS_Xt;
1581  case 5:
1582  return MISCREG_TLBI_VALE1IS_Xt;
1583  case 7:
1584  return MISCREG_TLBI_VAALE1IS_Xt;
1585  }
1586  break;
1587  case 7:
1588  switch (op2) {
1589  case 0:
1590  return MISCREG_TLBI_VMALLE1;
1591  case 1:
1592  return MISCREG_TLBI_VAE1_Xt;
1593  case 2:
1594  return MISCREG_TLBI_ASIDE1_Xt;
1595  case 3:
1596  return MISCREG_TLBI_VAAE1_Xt;
1597  case 5:
1598  return MISCREG_TLBI_VALE1_Xt;
1599  case 7:
1600  return MISCREG_TLBI_VAALE1_Xt;
1601  }
1602  break;
1603  }
1604  break;
1605  case 4:
1606  switch (crm) {
1607  case 0:
1608  switch (op2) {
1609  case 1:
1610  return MISCREG_TLBI_IPAS2E1IS_Xt;
1611  case 5:
1612  return MISCREG_TLBI_IPAS2LE1IS_Xt;
1613  }
1614  break;
1615  case 3:
1616  switch (op2) {
1617  case 0:
1618  return MISCREG_TLBI_ALLE2IS;
1619  case 1:
1620  return MISCREG_TLBI_VAE2IS_Xt;
1621  case 4:
1622  return MISCREG_TLBI_ALLE1IS;
1623  case 5:
1624  return MISCREG_TLBI_VALE2IS_Xt;
1625  case 6:
1626  return MISCREG_TLBI_VMALLS12E1IS;
1627  }
1628  break;
1629  case 4:
1630  switch (op2) {
1631  case 1:
1632  return MISCREG_TLBI_IPAS2E1_Xt;
1633  case 5:
1634  return MISCREG_TLBI_IPAS2LE1_Xt;
1635  }
1636  break;
1637  case 7:
1638  switch (op2) {
1639  case 0:
1640  return MISCREG_TLBI_ALLE2;
1641  case 1:
1642  return MISCREG_TLBI_VAE2_Xt;
1643  case 4:
1644  return MISCREG_TLBI_ALLE1;
1645  case 5:
1646  return MISCREG_TLBI_VALE2_Xt;
1647  case 6:
1648  return MISCREG_TLBI_VMALLS12E1;
1649  }
1650  break;
1651  }
1652  break;
1653  case 6:
1654  switch (crm) {
1655  case 3:
1656  switch (op2) {
1657  case 0:
1658  return MISCREG_TLBI_ALLE3IS;
1659  case 1:
1660  return MISCREG_TLBI_VAE3IS_Xt;
1661  case 5:
1662  return MISCREG_TLBI_VALE3IS_Xt;
1663  }
1664  break;
1665  case 7:
1666  switch (op2) {
1667  case 0:
1668  return MISCREG_TLBI_ALLE3;
1669  case 1:
1670  return MISCREG_TLBI_VAE3_Xt;
1671  case 5:
1672  return MISCREG_TLBI_VALE3_Xt;
1673  }
1674  break;
1675  }
1676  break;
1677  }
1678  break;
1679  case 11:
1680  case 15:
1681  // SYS Instruction with CRn = { 11, 15 }
1682  // (Trappable by HCR_EL2.TIDCP)
1683  return MISCREG_IMPDEF_UNIMPL;
1684  }
1685  break;
1686  case 2:
1687  switch (crn) {
1688  case 0:
1689  switch (op1) {
1690  case 0:
1691  switch (crm) {
1692  case 0:
1693  switch (op2) {
1694  case 2:
1695  return MISCREG_OSDTRRX_EL1;
1696  case 4:
1697  return MISCREG_DBGBVR0_EL1;
1698  case 5:
1699  return MISCREG_DBGBCR0_EL1;
1700  case 6:
1701  return MISCREG_DBGWVR0_EL1;
1702  case 7:
1703  return MISCREG_DBGWCR0_EL1;
1704  }
1705  break;
1706  case 1:
1707  switch (op2) {
1708  case 4:
1709  return MISCREG_DBGBVR1_EL1;
1710  case 5:
1711  return MISCREG_DBGBCR1_EL1;
1712  case 6:
1713  return MISCREG_DBGWVR1_EL1;
1714  case 7:
1715  return MISCREG_DBGWCR1_EL1;
1716  }
1717  break;
1718  case 2:
1719  switch (op2) {
1720  case 0:
1721  return MISCREG_MDCCINT_EL1;
1722  case 2:
1723  return MISCREG_MDSCR_EL1;
1724  case 4:
1725  return MISCREG_DBGBVR2_EL1;
1726  case 5:
1727  return MISCREG_DBGBCR2_EL1;
1728  case 6:
1729  return MISCREG_DBGWVR2_EL1;
1730  case 7:
1731  return MISCREG_DBGWCR2_EL1;
1732  }
1733  break;
1734  case 3:
1735  switch (op2) {
1736  case 2:
1737  return MISCREG_OSDTRTX_EL1;
1738  case 4:
1739  return MISCREG_DBGBVR3_EL1;
1740  case 5:
1741  return MISCREG_DBGBCR3_EL1;
1742  case 6:
1743  return MISCREG_DBGWVR3_EL1;
1744  case 7:
1745  return MISCREG_DBGWCR3_EL1;
1746  }
1747  break;
1748  case 4:
1749  switch (op2) {
1750  case 4:
1751  return MISCREG_DBGBVR4_EL1;
1752  case 5:
1753  return MISCREG_DBGBCR4_EL1;
1754  case 6:
1755  return MISCREG_DBGWVR4_EL1;
1756  case 7:
1757  return MISCREG_DBGWCR4_EL1;
1758  }
1759  break;
1760  case 5:
1761  switch (op2) {
1762  case 4:
1763  return MISCREG_DBGBVR5_EL1;
1764  case 5:
1765  return MISCREG_DBGBCR5_EL1;
1766  case 6:
1767  return MISCREG_DBGWVR5_EL1;
1768  case 7:
1769  return MISCREG_DBGWCR5_EL1;
1770  }
1771  break;
1772  case 6:
1773  switch (op2) {
1774  case 2:
1775  return MISCREG_OSECCR_EL1;
1776  case 4:
1777  return MISCREG_DBGBVR6_EL1;
1778  case 5:
1779  return MISCREG_DBGBCR6_EL1;
1780  case 6:
1781  return MISCREG_DBGWVR6_EL1;
1782  case 7:
1783  return MISCREG_DBGWCR6_EL1;
1784  }
1785  break;
1786  case 7:
1787  switch (op2) {
1788  case 4:
1789  return MISCREG_DBGBVR7_EL1;
1790  case 5:
1791  return MISCREG_DBGBCR7_EL1;
1792  case 6:
1793  return MISCREG_DBGWVR7_EL1;
1794  case 7:
1795  return MISCREG_DBGWCR7_EL1;
1796  }
1797  break;
1798  case 8:
1799  switch (op2) {
1800  case 4:
1801  return MISCREG_DBGBVR8_EL1;
1802  case 5:
1803  return MISCREG_DBGBCR8_EL1;
1804  case 6:
1805  return MISCREG_DBGWVR8_EL1;
1806  case 7:
1807  return MISCREG_DBGWCR8_EL1;
1808  }
1809  break;
1810  case 9:
1811  switch (op2) {
1812  case 4:
1813  return MISCREG_DBGBVR9_EL1;
1814  case 5:
1815  return MISCREG_DBGBCR9_EL1;
1816  case 6:
1817  return MISCREG_DBGWVR9_EL1;
1818  case 7:
1819  return MISCREG_DBGWCR9_EL1;
1820  }
1821  break;
1822  case 10:
1823  switch (op2) {
1824  case 4:
1825  return MISCREG_DBGBVR10_EL1;
1826  case 5:
1827  return MISCREG_DBGBCR10_EL1;
1828  case 6:
1829  return MISCREG_DBGWVR10_EL1;
1830  case 7:
1831  return MISCREG_DBGWCR10_EL1;
1832  }
1833  break;
1834  case 11:
1835  switch (op2) {
1836  case 4:
1837  return MISCREG_DBGBVR11_EL1;
1838  case 5:
1839  return MISCREG_DBGBCR11_EL1;
1840  case 6:
1841  return MISCREG_DBGWVR11_EL1;
1842  case 7:
1843  return MISCREG_DBGWCR11_EL1;
1844  }
1845  break;
1846  case 12:
1847  switch (op2) {
1848  case 4:
1849  return MISCREG_DBGBVR12_EL1;
1850  case 5:
1851  return MISCREG_DBGBCR12_EL1;
1852  case 6:
1853  return MISCREG_DBGWVR12_EL1;
1854  case 7:
1855  return MISCREG_DBGWCR12_EL1;
1856  }
1857  break;
1858  case 13:
1859  switch (op2) {
1860  case 4:
1861  return MISCREG_DBGBVR13_EL1;
1862  case 5:
1863  return MISCREG_DBGBCR13_EL1;
1864  case 6:
1865  return MISCREG_DBGWVR13_EL1;
1866  case 7:
1867  return MISCREG_DBGWCR13_EL1;
1868  }
1869  break;
1870  case 14:
1871  switch (op2) {
1872  case 4:
1873  return MISCREG_DBGBVR14_EL1;
1874  case 5:
1875  return MISCREG_DBGBCR14_EL1;
1876  case 6:
1877  return MISCREG_DBGWVR14_EL1;
1878  case 7:
1879  return MISCREG_DBGWCR14_EL1;
1880  }
1881  break;
1882  case 15:
1883  switch (op2) {
1884  case 4:
1885  return MISCREG_DBGBVR15_EL1;
1886  case 5:
1887  return MISCREG_DBGBCR15_EL1;
1888  case 6:
1889  return MISCREG_DBGWVR15_EL1;
1890  case 7:
1891  return MISCREG_DBGWCR15_EL1;
1892  }
1893  break;
1894  }
1895  break;
1896  case 2:
1897  switch (crm) {
1898  case 0:
1899  switch (op2) {
1900  case 0:
1901  return MISCREG_TEECR32_EL1;
1902  }
1903  break;
1904  }
1905  break;
1906  case 3:
1907  switch (crm) {
1908  case 1:
1909  switch (op2) {
1910  case 0:
1911  return MISCREG_MDCCSR_EL0;
1912  }
1913  break;
1914  case 4:
1915  switch (op2) {
1916  case 0:
1917  return MISCREG_MDDTR_EL0;
1918  }
1919  break;
1920  case 5:
1921  switch (op2) {
1922  case 0:
1923  return MISCREG_MDDTRRX_EL0;
1924  }
1925  break;
1926  }
1927  break;
1928  case 4:
1929  switch (crm) {
1930  case 7:
1931  switch (op2) {
1932  case 0:
1933  return MISCREG_DBGVCR32_EL2;
1934  }
1935  break;
1936  }
1937  break;
1938  }
1939  break;
1940  case 1:
1941  switch (op1) {
1942  case 0:
1943  switch (crm) {
1944  case 0:
1945  switch (op2) {
1946  case 0:
1947  return MISCREG_MDRAR_EL1;
1948  case 4:
1949  return MISCREG_OSLAR_EL1;
1950  }
1951  break;
1952  case 1:
1953  switch (op2) {
1954  case 4:
1955  return MISCREG_OSLSR_EL1;
1956  }
1957  break;
1958  case 3:
1959  switch (op2) {
1960  case 4:
1961  return MISCREG_OSDLR_EL1;
1962  }
1963  break;
1964  case 4:
1965  switch (op2) {
1966  case 4:
1967  return MISCREG_DBGPRCR_EL1;
1968  }
1969  break;
1970  }
1971  break;
1972  case 2:
1973  switch (crm) {
1974  case 0:
1975  switch (op2) {
1976  case 0:
1977  return MISCREG_TEEHBR32_EL1;
1978  }
1979  break;
1980  }
1981  break;
1982  }
1983  break;
1984  case 7:
1985  switch (op1) {
1986  case 0:
1987  switch (crm) {
1988  case 8:
1989  switch (op2) {
1990  case 6:
1991  return MISCREG_DBGCLAIMSET_EL1;
1992  }
1993  break;
1994  case 9:
1995  switch (op2) {
1996  case 6:
1997  return MISCREG_DBGCLAIMCLR_EL1;
1998  }
1999  break;
2000  case 14:
2001  switch (op2) {
2002  case 6:
2003  return MISCREG_DBGAUTHSTATUS_EL1;
2004  }
2005  break;
2006  }
2007  break;
2008  }
2009  break;
2010  }
2011  break;
2012  case 3:
2013  switch (crn) {
2014  case 0:
2015  switch (op1) {
2016  case 0:
2017  switch (crm) {
2018  case 0:
2019  switch (op2) {
2020  case 0:
2021  return MISCREG_MIDR_EL1;
2022  case 5:
2023  return MISCREG_MPIDR_EL1;
2024  case 6:
2025  return MISCREG_REVIDR_EL1;
2026  }
2027  break;
2028  case 1:
2029  switch (op2) {
2030  case 0:
2031  return MISCREG_ID_PFR0_EL1;
2032  case 1:
2033  return MISCREG_ID_PFR1_EL1;
2034  case 2:
2035  return MISCREG_ID_DFR0_EL1;
2036  case 3:
2037  return MISCREG_ID_AFR0_EL1;
2038  case 4:
2039  return MISCREG_ID_MMFR0_EL1;
2040  case 5:
2041  return MISCREG_ID_MMFR1_EL1;
2042  case 6:
2043  return MISCREG_ID_MMFR2_EL1;
2044  case 7:
2045  return MISCREG_ID_MMFR3_EL1;
2046  }
2047  break;
2048  case 2:
2049  switch (op2) {
2050  case 0:
2051  return MISCREG_ID_ISAR0_EL1;
2052  case 1:
2053  return MISCREG_ID_ISAR1_EL1;
2054  case 2:
2055  return MISCREG_ID_ISAR2_EL1;
2056  case 3:
2057  return MISCREG_ID_ISAR3_EL1;
2058  case 4:
2059  return MISCREG_ID_ISAR4_EL1;
2060  case 5:
2061  return MISCREG_ID_ISAR5_EL1;
2062  }
2063  break;
2064  case 3:
2065  switch (op2) {
2066  case 0:
2067  return MISCREG_MVFR0_EL1;
2068  case 1:
2069  return MISCREG_MVFR1_EL1;
2070  case 2:
2071  return MISCREG_MVFR2_EL1;
2072  case 3 ... 7:
2073  return MISCREG_RAZ;
2074  }
2075  break;
2076  case 4:
2077  switch (op2) {
2078  case 0:
2079  return MISCREG_ID_AA64PFR0_EL1;
2080  case 1:
2081  return MISCREG_ID_AA64PFR1_EL1;
2082  case 2 ... 3:
2083  return MISCREG_RAZ;
2084  case 4:
2085  return MISCREG_ID_AA64ZFR0_EL1;
2086  case 5 ... 7:
2087  return MISCREG_RAZ;
2088  }
2089  break;
2090  case 5:
2091  switch (op2) {
2092  case 0:
2093  return MISCREG_ID_AA64DFR0_EL1;
2094  case 1:
2095  return MISCREG_ID_AA64DFR1_EL1;
2096  case 4:
2097  return MISCREG_ID_AA64AFR0_EL1;
2098  case 5:
2099  return MISCREG_ID_AA64AFR1_EL1;
2100  case 2:
2101  case 3:
2102  case 6:
2103  case 7:
2104  return MISCREG_RAZ;
2105  }
2106  break;
2107  case 6:
2108  switch (op2) {
2109  case 0:
2110  return MISCREG_ID_AA64ISAR0_EL1;
2111  case 1:
2112  return MISCREG_ID_AA64ISAR1_EL1;
2113  case 2 ... 7:
2114  return MISCREG_RAZ;
2115  }
2116  break;
2117  case 7:
2118  switch (op2) {
2119  case 0:
2120  return MISCREG_ID_AA64MMFR0_EL1;
2121  case 1:
2122  return MISCREG_ID_AA64MMFR1_EL1;
2123  case 2:
2124  return MISCREG_ID_AA64MMFR2_EL1;
2125  case 3 ... 7:
2126  return MISCREG_RAZ;
2127  }
2128  break;
2129  }
2130  break;
2131  case 1:
2132  switch (crm) {
2133  case 0:
2134  switch (op2) {
2135  case 0:
2136  return MISCREG_CCSIDR_EL1;
2137  case 1:
2138  return MISCREG_CLIDR_EL1;
2139  case 7:
2140  return MISCREG_AIDR_EL1;
2141  }
2142  break;
2143  }
2144  break;
2145  case 2:
2146  switch (crm) {
2147  case 0:
2148  switch (op2) {
2149  case 0:
2150  return MISCREG_CSSELR_EL1;
2151  }
2152  break;
2153  }
2154  break;
2155  case 3:
2156  switch (crm) {
2157  case 0:
2158  switch (op2) {
2159  case 1:
2160  return MISCREG_CTR_EL0;
2161  case 7:
2162  return MISCREG_DCZID_EL0;
2163  }
2164  break;
2165  }
2166  break;
2167  case 4:
2168  switch (crm) {
2169  case 0:
2170  switch (op2) {
2171  case 0:
2172  return MISCREG_VPIDR_EL2;
2173  case 5:
2174  return MISCREG_VMPIDR_EL2;
2175  }
2176  break;
2177  }
2178  break;
2179  }
2180  break;
2181  case 1:
2182  switch (op1) {
2183  case 0:
2184  switch (crm) {
2185  case 0:
2186  switch (op2) {
2187  case 0:
2188  return MISCREG_SCTLR_EL1;
2189  case 1:
2190  return MISCREG_ACTLR_EL1;
2191  case 2:
2192  return MISCREG_CPACR_EL1;
2193  }
2194  break;
2195  case 2:
2196  switch (op2) {
2197  case 0:
2198  return MISCREG_ZCR_EL1;
2199  }
2200  break;
2201  }
2202  break;
2203  case 4:
2204  switch (crm) {
2205  case 0:
2206  switch (op2) {
2207  case 0:
2208  return MISCREG_SCTLR_EL2;
2209  case 1:
2210  return MISCREG_ACTLR_EL2;
2211  }
2212  break;
2213  case 1:
2214  switch (op2) {
2215  case 0:
2216  return MISCREG_HCR_EL2;
2217  case 1:
2218  return MISCREG_MDCR_EL2;
2219  case 2:
2220  return MISCREG_CPTR_EL2;
2221  case 3:
2222  return MISCREG_HSTR_EL2;
2223  case 7:
2224  return MISCREG_HACR_EL2;
2225  }
2226  break;
2227  case 2:
2228  switch (op2) {
2229  case 0:
2230  return MISCREG_ZCR_EL2;
2231  }
2232  break;
2233  }
2234  break;
2235  case 5:
2236  /* op0: 3 Crn:1 op1:5 */
2237  switch (crm) {
2238  case 0:
2239  switch (op2) {
2240  case 0:
2241  return MISCREG_SCTLR_EL12;
2242  case 2:
2243  return MISCREG_CPACR_EL12;
2244  }
2245  break;
2246  case 2:
2247  switch (op2) {
2248  case 0:
2249  return MISCREG_ZCR_EL12;
2250  }
2251  break;
2252  }
2253  break;
2254  case 6:
2255  switch (crm) {
2256  case 0:
2257  switch (op2) {
2258  case 0:
2259  return MISCREG_SCTLR_EL3;
2260  case 1:
2261  return MISCREG_ACTLR_EL3;
2262  }
2263  break;
2264  case 1:
2265  switch (op2) {
2266  case 0:
2267  return MISCREG_SCR_EL3;
2268  case 1:
2269  return MISCREG_SDER32_EL3;
2270  case 2:
2271  return MISCREG_CPTR_EL3;
2272  }
2273  break;
2274  case 2:
2275  switch (op2) {
2276  case 0:
2277  return MISCREG_ZCR_EL3;
2278  }
2279  break;
2280  case 3:
2281  switch (op2) {
2282  case 1:
2283  return MISCREG_MDCR_EL3;
2284  }
2285  break;
2286  }
2287  break;
2288  }
2289  break;
2290  case 2:
2291  switch (op1) {
2292  case 0:
2293  switch (crm) {
2294  case 0:
2295  switch (op2) {
2296  case 0:
2297  return MISCREG_TTBR0_EL1;
2298  case 1:
2299  return MISCREG_TTBR1_EL1;
2300  case 2:
2301  return MISCREG_TCR_EL1;
2302  }
2303  break;
2304  case 0x1:
2305  switch (op2) {
2306  case 0x0:
2307  return MISCREG_APIAKeyLo_EL1;
2308  case 0x1:
2309  return MISCREG_APIAKeyHi_EL1;
2310  case 0x2:
2311  return MISCREG_APIBKeyLo_EL1;
2312  case 0x3:
2313  return MISCREG_APIBKeyHi_EL1;
2314  }
2315  break;
2316  case 0x2:
2317  switch (op2) {
2318  case 0x0:
2319  return MISCREG_APDAKeyLo_EL1;
2320  case 0x1:
2321  return MISCREG_APDAKeyHi_EL1;
2322  case 0x2:
2323  return MISCREG_APDBKeyLo_EL1;
2324  case 0x3:
2325  return MISCREG_APDBKeyHi_EL1;
2326  }
2327  break;
2328 
2329  case 0x3:
2330  switch (op2) {
2331  case 0x0:
2332  return MISCREG_APGAKeyLo_EL1;
2333  case 0x1:
2334  return MISCREG_APGAKeyHi_EL1;
2335  }
2336  break;
2337  }
2338  break;
2339  case 4:
2340  switch (crm) {
2341  case 0:
2342  switch (op2) {
2343  case 0:
2344  return MISCREG_TTBR0_EL2;
2345  case 1:
2346  return MISCREG_TTBR1_EL2;
2347  case 2:
2348  return MISCREG_TCR_EL2;
2349  }
2350  break;
2351  case 1:
2352  switch (op2) {
2353  case 0:
2354  return MISCREG_VTTBR_EL2;
2355  case 2:
2356  return MISCREG_VTCR_EL2;
2357  }
2358  break;
2359  case 6:
2360  switch (op2) {
2361  case 0:
2362  return MISCREG_VSTTBR_EL2;
2363  case 2:
2364  return MISCREG_VSTCR_EL2;
2365  }
2366  break;
2367  }
2368  break;
2369  case 5:
2370  /* op0: 3 Crn:2 op1:5 */
2371  switch (crm) {
2372  case 0:
2373  switch (op2) {
2374  case 0:
2375  return MISCREG_TTBR0_EL12;
2376  case 1:
2377  return MISCREG_TTBR1_EL12;
2378  case 2:
2379  return MISCREG_TCR_EL12;
2380  }
2381  break;
2382  }
2383  break;
2384  case 6:
2385  switch (crm) {
2386  case 0:
2387  switch (op2) {
2388  case 0:
2389  return MISCREG_TTBR0_EL3;
2390  case 2:
2391  return MISCREG_TCR_EL3;
2392  }
2393  break;
2394  }
2395  break;
2396  }
2397  break;
2398  case 3:
2399  switch (op1) {
2400  case 4:
2401  switch (crm) {
2402  case 0:
2403  switch (op2) {
2404  case 0:
2405  return MISCREG_DACR32_EL2;
2406  }
2407  break;
2408  }
2409  break;
2410  }
2411  break;
2412  case 4:
2413  switch (op1) {
2414  case 0:
2415  switch (crm) {
2416  case 0:
2417  switch (op2) {
2418  case 0:
2419  return MISCREG_SPSR_EL1;
2420  case 1:
2421  return MISCREG_ELR_EL1;
2422  }
2423  break;
2424  case 1:
2425  switch (op2) {
2426  case 0:
2427  return MISCREG_SP_EL0;
2428  }
2429  break;
2430  case 2:
2431  switch (op2) {
2432  case 0:
2433  return MISCREG_SPSEL;
2434  case 2:
2435  return MISCREG_CURRENTEL;
2436  case 3:
2437  return MISCREG_PAN;
2438  }
2439  break;
2440  case 6:
2441  switch (op2) {
2442  case 0:
2443  return MISCREG_ICC_PMR_EL1;
2444  }
2445  break;
2446  }
2447  break;
2448  case 3:
2449  switch (crm) {
2450  case 2:
2451  switch (op2) {
2452  case 0:
2453  return MISCREG_NZCV;
2454  case 1:
2455  return MISCREG_DAIF;
2456  }
2457  break;
2458  case 4:
2459  switch (op2) {
2460  case 0:
2461  return MISCREG_FPCR;
2462  case 1:
2463  return MISCREG_FPSR;
2464  }
2465  break;
2466  case 5:
2467  switch (op2) {
2468  case 0:
2469  return MISCREG_DSPSR_EL0;
2470  case 1:
2471  return MISCREG_DLR_EL0;
2472  }
2473  break;
2474  }
2475  break;
2476  case 4:
2477  switch (crm) {
2478  case 0:
2479  switch (op2) {
2480  case 0:
2481  return MISCREG_SPSR_EL2;
2482  case 1:
2483  return MISCREG_ELR_EL2;
2484  }
2485  break;
2486  case 1:
2487  switch (op2) {
2488  case 0:
2489  return MISCREG_SP_EL1;
2490  }
2491  break;
2492  case 3:
2493  switch (op2) {
2494  case 0:
2495  return MISCREG_SPSR_IRQ_AA64;
2496  case 1:
2497  return MISCREG_SPSR_ABT_AA64;
2498  case 2:
2499  return MISCREG_SPSR_UND_AA64;
2500  case 3:
2501  return MISCREG_SPSR_FIQ_AA64;
2502  }
2503  break;
2504  }
2505  break;
2506  case 5:
2507  switch (crm) {
2508  case 0:
2509  switch (op2) {
2510  case 0:
2511  return MISCREG_SPSR_EL12;
2512  case 1:
2513  return MISCREG_ELR_EL12;
2514  }
2515  break;
2516  }
2517  break;
2518  case 6:
2519  switch (crm) {
2520  case 0:
2521  switch (op2) {
2522  case 0:
2523  return MISCREG_SPSR_EL3;
2524  case 1:
2525  return MISCREG_ELR_EL3;
2526  }
2527  break;
2528  case 1:
2529  switch (op2) {
2530  case 0:
2531  return MISCREG_SP_EL2;
2532  }
2533  break;
2534  }
2535  break;
2536  }
2537  break;
2538  case 5:
2539  switch (op1) {
2540  case 0:
2541  switch (crm) {
2542  case 1:
2543  switch (op2) {
2544  case 0:
2545  return MISCREG_AFSR0_EL1;
2546  case 1:
2547  return MISCREG_AFSR1_EL1;
2548  }
2549  break;
2550  case 2:
2551  switch (op2) {
2552  case 0:
2553  return MISCREG_ESR_EL1;
2554  }
2555  break;
2556  case 3:
2557  switch (op2) {
2558  case 0:
2559  return MISCREG_ERRIDR_EL1;
2560  case 1:
2561  return MISCREG_ERRSELR_EL1;
2562  }
2563  break;
2564  case 4:
2565  switch (op2) {
2566  case 0:
2567  return MISCREG_ERXFR_EL1;
2568  case 1:
2569  return MISCREG_ERXCTLR_EL1;
2570  case 2:
2571  return MISCREG_ERXSTATUS_EL1;
2572  case 3:
2573  return MISCREG_ERXADDR_EL1;
2574  }
2575  break;
2576  case 5:
2577  switch (op2) {
2578  case 0:
2579  return MISCREG_ERXMISC0_EL1;
2580  case 1:
2581  return MISCREG_ERXMISC1_EL1;
2582  }
2583  break;
2584  }
2585  break;
2586  case 4:
2587  switch (crm) {
2588  case 0:
2589  switch (op2) {
2590  case 1:
2591  return MISCREG_IFSR32_EL2;
2592  }
2593  break;
2594  case 1:
2595  switch (op2) {
2596  case 0:
2597  return MISCREG_AFSR0_EL2;
2598  case 1:
2599  return MISCREG_AFSR1_EL2;
2600  }
2601  break;
2602  case 2:
2603  switch (op2) {
2604  case 0:
2605  return MISCREG_ESR_EL2;
2606  case 3:
2607  return MISCREG_VSESR_EL2;
2608  }
2609  break;
2610  case 3:
2611  switch (op2) {
2612  case 0:
2613  return MISCREG_FPEXC32_EL2;
2614  }
2615  break;
2616  }
2617  break;
2618  case 5:
2619  switch (crm) {
2620  case 1:
2621  switch (op2) {
2622  case 0:
2623  return MISCREG_AFSR0_EL12;
2624  case 1:
2625  return MISCREG_AFSR1_EL12;
2626  }
2627  break;
2628  case 2:
2629  switch (op2) {
2630  case 0:
2631  return MISCREG_ESR_EL12;
2632  }
2633  break;
2634  }
2635  break;
2636  case 6:
2637  switch (crm) {
2638  case 1:
2639  switch (op2) {
2640  case 0:
2641  return MISCREG_AFSR0_EL3;
2642  case 1:
2643  return MISCREG_AFSR1_EL3;
2644  }
2645  break;
2646  case 2:
2647  switch (op2) {
2648  case 0:
2649  return MISCREG_ESR_EL3;
2650  }
2651  break;
2652  }
2653  break;
2654  }
2655  break;
2656  case 6:
2657  switch (op1) {
2658  case 0:
2659  switch (crm) {
2660  case 0:
2661  switch (op2) {
2662  case 0:
2663  return MISCREG_FAR_EL1;
2664  }
2665  break;
2666  }
2667  break;
2668  case 4:
2669  switch (crm) {
2670  case 0:
2671  switch (op2) {
2672  case 0:
2673  return MISCREG_FAR_EL2;
2674  case 4:
2675  return MISCREG_HPFAR_EL2;
2676  }
2677  break;
2678  }
2679  break;
2680  case 5:
2681  switch (crm) {
2682  case 0:
2683  switch (op2) {
2684  case 0:
2685  return MISCREG_FAR_EL12;
2686  }
2687  break;
2688  }
2689  break;
2690  case 6:
2691  switch (crm) {
2692  case 0:
2693  switch (op2) {
2694  case 0:
2695  return MISCREG_FAR_EL3;
2696  }
2697  break;
2698  }
2699  break;
2700  }
2701  break;
2702  case 7:
2703  switch (op1) {
2704  case 0:
2705  switch (crm) {
2706  case 4:
2707  switch (op2) {
2708  case 0:
2709  return MISCREG_PAR_EL1;
2710  }
2711  break;
2712  }
2713  break;
2714  }
2715  break;
2716  case 9:
2717  switch (op1) {
2718  case 0:
2719  switch (crm) {
2720  case 14:
2721  switch (op2) {
2722  case 1:
2723  return MISCREG_PMINTENSET_EL1;
2724  case 2:
2725  return MISCREG_PMINTENCLR_EL1;
2726  }
2727  break;
2728  }
2729  break;
2730  case 3:
2731  switch (crm) {
2732  case 12:
2733  switch (op2) {
2734  case 0:
2735  return MISCREG_PMCR_EL0;
2736  case 1:
2737  return MISCREG_PMCNTENSET_EL0;
2738  case 2:
2739  return MISCREG_PMCNTENCLR_EL0;
2740  case 3:
2741  return MISCREG_PMOVSCLR_EL0;
2742  case 4:
2743  return MISCREG_PMSWINC_EL0;
2744  case 5:
2745  return MISCREG_PMSELR_EL0;
2746  case 6:
2747  return MISCREG_PMCEID0_EL0;
2748  case 7:
2749  return MISCREG_PMCEID1_EL0;
2750  }
2751  break;
2752  case 13:
2753  switch (op2) {
2754  case 0:
2755  return MISCREG_PMCCNTR_EL0;
2756  case 1:
2757  return MISCREG_PMXEVTYPER_EL0;
2758  case 2:
2759  return MISCREG_PMXEVCNTR_EL0;
2760  }
2761  break;
2762  case 14:
2763  switch (op2) {
2764  case 0:
2765  return MISCREG_PMUSERENR_EL0;
2766  case 3:
2767  return MISCREG_PMOVSSET_EL0;
2768  }
2769  break;
2770  }
2771  break;
2772  }
2773  break;
2774  case 10:
2775  switch (op1) {
2776  case 0:
2777  switch (crm) {
2778  case 2:
2779  switch (op2) {
2780  case 0:
2781  return MISCREG_MAIR_EL1;
2782  }
2783  break;
2784  case 3:
2785  switch (op2) {
2786  case 0:
2787  return MISCREG_AMAIR_EL1;
2788  }
2789  break;
2790  }
2791  break;
2792  case 4:
2793  switch (crm) {
2794  case 2:
2795  switch (op2) {
2796  case 0:
2797  return MISCREG_MAIR_EL2;
2798  }
2799  break;
2800  case 3:
2801  switch (op2) {
2802  case 0:
2803  return MISCREG_AMAIR_EL2;
2804  }
2805  break;
2806  }
2807  break;
2808  case 5:
2809  switch (crm) {
2810  case 2:
2811  switch (op2) {
2812  case 0:
2813  return MISCREG_MAIR_EL12;
2814  }
2815  break;
2816  case 3:
2817  switch (op2) {
2818  case 0:
2819  return MISCREG_AMAIR_EL12;
2820  }
2821  break;
2822  }
2823  break;
2824  case 6:
2825  switch (crm) {
2826  case 2:
2827  switch (op2) {
2828  case 0:
2829  return MISCREG_MAIR_EL3;
2830  }
2831  break;
2832  case 3:
2833  switch (op2) {
2834  case 0:
2835  return MISCREG_AMAIR_EL3;
2836  }
2837  break;
2838  }
2839  break;
2840  }
2841  break;
2842  case 11:
2843  switch (op1) {
2844  case 1:
2845  switch (crm) {
2846  case 0:
2847  switch (op2) {
2848  case 2:
2849  return MISCREG_L2CTLR_EL1;
2850  case 3:
2851  return MISCREG_L2ECTLR_EL1;
2852  }
2853  break;
2854  }
2855  M5_FALLTHROUGH;
2856  default:
2857  // S3_<op1>_11_<Cm>_<op2>
2858  return MISCREG_IMPDEF_UNIMPL;
2859  }
2860  M5_UNREACHABLE;
2861  case 12:
2862  switch (op1) {
2863  case 0:
2864  switch (crm) {
2865  case 0:
2866  switch (op2) {
2867  case 0:
2868  return MISCREG_VBAR_EL1;
2869  case 1:
2870  return MISCREG_RVBAR_EL1;
2871  }
2872  break;
2873  case 1:
2874  switch (op2) {
2875  case 0:
2876  return MISCREG_ISR_EL1;
2877  case 1:
2878  return MISCREG_DISR_EL1;
2879  }
2880  break;
2881  case 8:
2882  switch (op2) {
2883  case 0:
2884  return MISCREG_ICC_IAR0_EL1;
2885  case 1:
2886  return MISCREG_ICC_EOIR0_EL1;
2887  case 2:
2888  return MISCREG_ICC_HPPIR0_EL1;
2889  case 3:
2890  return MISCREG_ICC_BPR0_EL1;
2891  case 4:
2892  return MISCREG_ICC_AP0R0_EL1;
2893  case 5:
2894  return MISCREG_ICC_AP0R1_EL1;
2895  case 6:
2896  return MISCREG_ICC_AP0R2_EL1;
2897  case 7:
2898  return MISCREG_ICC_AP0R3_EL1;
2899  }
2900  break;
2901  case 9:
2902  switch (op2) {
2903  case 0:
2904  return MISCREG_ICC_AP1R0_EL1;
2905  case 1:
2906  return MISCREG_ICC_AP1R1_EL1;
2907  case 2:
2908  return MISCREG_ICC_AP1R2_EL1;
2909  case 3:
2910  return MISCREG_ICC_AP1R3_EL1;
2911  }
2912  break;
2913  case 11:
2914  switch (op2) {
2915  case 1:
2916  return MISCREG_ICC_DIR_EL1;
2917  case 3:
2918  return MISCREG_ICC_RPR_EL1;
2919  case 5:
2920  return MISCREG_ICC_SGI1R_EL1;
2921  case 6:
2922  return MISCREG_ICC_ASGI1R_EL1;
2923  case 7:
2924  return MISCREG_ICC_SGI0R_EL1;
2925  }
2926  break;
2927  case 12:
2928  switch (op2) {
2929  case 0:
2930  return MISCREG_ICC_IAR1_EL1;
2931  case 1:
2932  return MISCREG_ICC_EOIR1_EL1;
2933  case 2:
2934  return MISCREG_ICC_HPPIR1_EL1;
2935  case 3:
2936  return MISCREG_ICC_BPR1_EL1;
2937  case 4:
2938  return MISCREG_ICC_CTLR_EL1;
2939  case 5:
2940  return MISCREG_ICC_SRE_EL1;
2941  case 6:
2942  return MISCREG_ICC_IGRPEN0_EL1;
2943  case 7:
2944  return MISCREG_ICC_IGRPEN1_EL1;
2945  }
2946  break;
2947  }
2948  break;
2949  case 4:
2950  switch (crm) {
2951  case 0:
2952  switch (op2) {
2953  case 0:
2954  return MISCREG_VBAR_EL2;
2955  case 1:
2956  return MISCREG_RVBAR_EL2;
2957  }
2958  break;
2959  case 1:
2960  switch (op2) {
2961  case 1:
2962  return MISCREG_VDISR_EL2;
2963  }
2964  break;
2965  case 8:
2966  switch (op2) {
2967  case 0:
2968  return MISCREG_ICH_AP0R0_EL2;
2969  case 1:
2970  return MISCREG_ICH_AP0R1_EL2;
2971  case 2:
2972  return MISCREG_ICH_AP0R2_EL2;
2973  case 3:
2974  return MISCREG_ICH_AP0R3_EL2;
2975  }
2976  break;
2977  case 9:
2978  switch (op2) {
2979  case 0:
2980  return MISCREG_ICH_AP1R0_EL2;
2981  case 1:
2982  return MISCREG_ICH_AP1R1_EL2;
2983  case 2:
2984  return MISCREG_ICH_AP1R2_EL2;
2985  case 3:
2986  return MISCREG_ICH_AP1R3_EL2;
2987  case 5:
2988  return MISCREG_ICC_SRE_EL2;
2989  }
2990  break;
2991  case 11:
2992  switch (op2) {
2993  case 0:
2994  return MISCREG_ICH_HCR_EL2;
2995  case 1:
2996  return MISCREG_ICH_VTR_EL2;
2997  case 2:
2998  return MISCREG_ICH_MISR_EL2;
2999  case 3:
3000  return MISCREG_ICH_EISR_EL2;
3001  case 5:
3002  return MISCREG_ICH_ELRSR_EL2;
3003  case 7:
3004  return MISCREG_ICH_VMCR_EL2;
3005  }
3006  break;
3007  case 12:
3008  switch (op2) {
3009  case 0:
3010  return MISCREG_ICH_LR0_EL2;
3011  case 1:
3012  return MISCREG_ICH_LR1_EL2;
3013  case 2:
3014  return MISCREG_ICH_LR2_EL2;
3015  case 3:
3016  return MISCREG_ICH_LR3_EL2;
3017  case 4:
3018  return MISCREG_ICH_LR4_EL2;
3019  case 5:
3020  return MISCREG_ICH_LR5_EL2;
3021  case 6:
3022  return MISCREG_ICH_LR6_EL2;
3023  case 7:
3024  return MISCREG_ICH_LR7_EL2;
3025  }
3026  break;
3027  case 13:
3028  switch (op2) {
3029  case 0:
3030  return MISCREG_ICH_LR8_EL2;
3031  case 1:
3032  return MISCREG_ICH_LR9_EL2;
3033  case 2:
3034  return MISCREG_ICH_LR10_EL2;
3035  case 3:
3036  return MISCREG_ICH_LR11_EL2;
3037  case 4:
3038  return MISCREG_ICH_LR12_EL2;
3039  case 5:
3040  return MISCREG_ICH_LR13_EL2;
3041  case 6:
3042  return MISCREG_ICH_LR14_EL2;
3043  case 7:
3044  return MISCREG_ICH_LR15_EL2;
3045  }
3046  break;
3047  }
3048  break;
3049  case 5:
3050  switch (crm) {
3051  case 0:
3052  switch (op2) {
3053  case 0:
3054  return MISCREG_VBAR_EL12;
3055  }
3056  break;
3057  }
3058  break;
3059  case 6:
3060  switch (crm) {
3061  case 0:
3062  switch (op2) {
3063  case 0:
3064  return MISCREG_VBAR_EL3;
3065  case 1:
3066  return MISCREG_RVBAR_EL3;
3067  case 2:
3068  return MISCREG_RMR_EL3;
3069  }
3070  break;
3071  case 12:
3072  switch (op2) {
3073  case 4:
3074  return MISCREG_ICC_CTLR_EL3;
3075  case 5:
3076  return MISCREG_ICC_SRE_EL3;
3077  case 7:
3078  return MISCREG_ICC_IGRPEN1_EL3;
3079  }
3080  break;
3081  }
3082  break;
3083  }
3084  break;
3085  case 13:
3086  switch (op1) {
3087  case 0:
3088  switch (crm) {
3089  case 0:
3090  switch (op2) {
3091  case 1:
3092  return MISCREG_CONTEXTIDR_EL1;
3093  case 4:
3094  return MISCREG_TPIDR_EL1;
3095  }
3096  break;
3097  }
3098  break;
3099  case 3:
3100  switch (crm) {
3101  case 0:
3102  switch (op2) {
3103  case 2:
3104  return MISCREG_TPIDR_EL0;
3105  case 3:
3106  return MISCREG_TPIDRRO_EL0;
3107  }
3108  break;
3109  }
3110  break;
3111  case 4:
3112  switch (crm) {
3113  case 0:
3114  switch (op2) {
3115  case 1:
3116  return MISCREG_CONTEXTIDR_EL2;
3117  case 2:
3118  return MISCREG_TPIDR_EL2;
3119  }
3120  break;
3121  }
3122  break;
3123  case 5:
3124  switch (crm) {
3125  case 0:
3126  switch (op2) {
3127  case 1:
3128  return MISCREG_CONTEXTIDR_EL12;
3129  }
3130  break;
3131  }
3132  break;
3133  case 6:
3134  switch (crm) {
3135  case 0:
3136  switch (op2) {
3137  case 2:
3138  return MISCREG_TPIDR_EL3;
3139  }
3140  break;
3141  }
3142  break;
3143  }
3144  break;
3145  case 14:
3146  switch (op1) {
3147  case 0:
3148  switch (crm) {
3149  case 1:
3150  switch (op2) {
3151  case 0:
3152  return MISCREG_CNTKCTL_EL1;
3153  }
3154  break;
3155  }
3156  break;
3157  case 3:
3158  switch (crm) {
3159  case 0:
3160  switch (op2) {
3161  case 0:
3162  return MISCREG_CNTFRQ_EL0;
3163  case 1:
3164  return MISCREG_CNTPCT_EL0;
3165  case 2:
3166  return MISCREG_CNTVCT_EL0;
3167  }
3168  break;
3169  case 2:
3170  switch (op2) {
3171  case 0:
3172  return MISCREG_CNTP_TVAL_EL0;
3173  case 1:
3174  return MISCREG_CNTP_CTL_EL0;
3175  case 2:
3176  return MISCREG_CNTP_CVAL_EL0;
3177  }
3178  break;
3179  case 3:
3180  switch (op2) {
3181  case 0:
3182  return MISCREG_CNTV_TVAL_EL0;
3183  case 1:
3184  return MISCREG_CNTV_CTL_EL0;
3185  case 2:
3186  return MISCREG_CNTV_CVAL_EL0;
3187  }
3188  break;
3189  case 8:
3190  switch (op2) {
3191  case 0:
3192  return MISCREG_PMEVCNTR0_EL0;
3193  case 1:
3194  return MISCREG_PMEVCNTR1_EL0;
3195  case 2:
3196  return MISCREG_PMEVCNTR2_EL0;
3197  case 3:
3198  return MISCREG_PMEVCNTR3_EL0;
3199  case 4:
3200  return MISCREG_PMEVCNTR4_EL0;
3201  case 5:
3202  return MISCREG_PMEVCNTR5_EL0;
3203  }
3204  break;
3205  case 12:
3206  switch (op2) {
3207  case 0:
3208  return MISCREG_PMEVTYPER0_EL0;
3209  case 1:
3210  return MISCREG_PMEVTYPER1_EL0;
3211  case 2:
3212  return MISCREG_PMEVTYPER2_EL0;
3213  case 3:
3214  return MISCREG_PMEVTYPER3_EL0;
3215  case 4:
3216  return MISCREG_PMEVTYPER4_EL0;
3217  case 5:
3218  return MISCREG_PMEVTYPER5_EL0;
3219  }
3220  break;
3221  case 15:
3222  switch (op2) {
3223  case 7:
3224  return MISCREG_PMCCFILTR_EL0;
3225  }
3226  }
3227  break;
3228  case 4:
3229  switch (crm) {
3230  case 0:
3231  switch (op2) {
3232  case 3:
3233  return MISCREG_CNTVOFF_EL2;
3234  }
3235  break;
3236  case 1:
3237  switch (op2) {
3238  case 0:
3239  return MISCREG_CNTHCTL_EL2;
3240  }
3241  break;
3242  case 2:
3243  switch (op2) {
3244  case 0:
3245  return MISCREG_CNTHP_TVAL_EL2;
3246  case 1:
3247  return MISCREG_CNTHP_CTL_EL2;
3248  case 2:
3249  return MISCREG_CNTHP_CVAL_EL2;
3250  }
3251  break;
3252  case 3:
3253  switch (op2) {
3254  case 0:
3255  return MISCREG_CNTHV_TVAL_EL2;
3256  case 1:
3257  return MISCREG_CNTHV_CTL_EL2;
3258  case 2:
3259  return MISCREG_CNTHV_CVAL_EL2;
3260  }
3261  break;
3262  }
3263  break;
3264  case 5:
3265  switch (crm) {
3266  case 1:
3267  switch (op2) {
3268  case 0:
3269  return MISCREG_CNTKCTL_EL12;
3270  }
3271  break;
3272  case 2:
3273  switch (op2) {
3274  case 0:
3275  return MISCREG_CNTP_TVAL_EL02;
3276  case 1:
3277  return MISCREG_CNTP_CTL_EL02;
3278  case 2:
3279  return MISCREG_CNTP_CVAL_EL02;
3280  }
3281  break;
3282  case 3:
3283  switch (op2) {
3284  case 0:
3285  return MISCREG_CNTV_TVAL_EL02;
3286  case 1:
3287  return MISCREG_CNTV_CTL_EL02;
3288  case 2:
3289  return MISCREG_CNTV_CVAL_EL02;
3290  }
3291  break;
3292  }
3293  break;
3294  case 7:
3295  switch (crm) {
3296  case 2:
3297  switch (op2) {
3298  case 0:
3299  return MISCREG_CNTPS_TVAL_EL1;
3300  case 1:
3301  return MISCREG_CNTPS_CTL_EL1;
3302  case 2:
3303  return MISCREG_CNTPS_CVAL_EL1;
3304  }
3305  break;
3306  }
3307  break;
3308  }
3309  break;
3310  case 15:
3311  switch (op1) {
3312  case 0:
3313  switch (crm) {
3314  case 0:
3315  switch (op2) {
3316  case 0:
3317  return MISCREG_IL1DATA0_EL1;
3318  case 1:
3319  return MISCREG_IL1DATA1_EL1;
3320  case 2:
3321  return MISCREG_IL1DATA2_EL1;
3322  case 3:
3323  return MISCREG_IL1DATA3_EL1;
3324  }
3325  break;
3326  case 1:
3327  switch (op2) {
3328  case 0:
3329  return MISCREG_DL1DATA0_EL1;
3330  case 1:
3331  return MISCREG_DL1DATA1_EL1;
3332  case 2:
3333  return MISCREG_DL1DATA2_EL1;
3334  case 3:
3335  return MISCREG_DL1DATA3_EL1;
3336  case 4:
3337  return MISCREG_DL1DATA4_EL1;
3338  }
3339  break;
3340  }
3341  break;
3342  case 1:
3343  switch (crm) {
3344  case 0:
3345  switch (op2) {
3346  case 0:
3347  return MISCREG_L2ACTLR_EL1;
3348  }
3349  break;
3350  case 2:
3351  switch (op2) {
3352  case 0:
3353  return MISCREG_CPUACTLR_EL1;
3354  case 1:
3355  return MISCREG_CPUECTLR_EL1;
3356  case 2:
3357  return MISCREG_CPUMERRSR_EL1;
3358  case 3:
3359  return MISCREG_L2MERRSR_EL1;
3360  }
3361  break;
3362  case 3:
3363  switch (op2) {
3364  case 0:
3365  return MISCREG_CBAR_EL1;
3366 
3367  }
3368  break;
3369  }
3370  break;
3371  }
3372  // S3_<op1>_15_<Cm>_<op2>
3373  return MISCREG_IMPDEF_UNIMPL;
3374  }
3375  break;
3376  }
3377 
3378  return MISCREG_UNKNOWN;
3379 }
3380 
3381 bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
3382 
3383 void
3384 ISA::initializeMiscRegMetadata()
3385 {
3386  // the MiscReg metadata tables are shared across all instances of the
3387  // ISA object, so there's no need to initialize them multiple times.
3388  static bool completed = false;
3389  if (completed)
3390  return;
3391 
3392  // This boolean variable specifies if the system is running in aarch32 at
3393  // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
3394  // is running in aarch64 (aarch32EL3 = false)
3395  bool aarch32EL3 = haveSecurity && !highestELIs64;
3396 
3397  // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
3398  // unsupported
3399  bool SPAN = false;
3400 
3401  // Implicit error synchronization event enable (Arm 8.2+), unsupported
3402  bool IESB = false;
3403 
3404  // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
3405  // unsupported
3406  bool LSMAOE = false;
3407 
3408  // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
3409  bool nTLSMD = false;
3410 
3411  // Pointer authentication (Arm 8.3+), unsupported
3412  bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
3413  bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
3414  bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
3415  bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
3416 
3430  InitReg(MISCREG_CPSR)
3431  .allPrivileges();
3432  InitReg(MISCREG_SPSR)
3433  .allPrivileges();
3434  InitReg(MISCREG_SPSR_FIQ)
3435  .allPrivileges();
3436  InitReg(MISCREG_SPSR_IRQ)
3437  .allPrivileges();
3438  InitReg(MISCREG_SPSR_SVC)
3439  .allPrivileges();
3440  InitReg(MISCREG_SPSR_MON)
3441  .allPrivileges();
3442  InitReg(MISCREG_SPSR_ABT)
3443  .allPrivileges();
3444  InitReg(MISCREG_SPSR_HYP)
3445  .allPrivileges();
3446  InitReg(MISCREG_SPSR_UND)
3447  .allPrivileges();
3448  InitReg(MISCREG_ELR_HYP)
3449  .allPrivileges();
3450  InitReg(MISCREG_FPSID)
3451  .allPrivileges();
3452  InitReg(MISCREG_FPSCR)
3453  .allPrivileges();
3454  InitReg(MISCREG_MVFR1)
3455  .allPrivileges();
3456  InitReg(MISCREG_MVFR0)
3457  .allPrivileges();
3458  InitReg(MISCREG_FPEXC)
3459  .allPrivileges();
3460 
3461  // Helper registers
3462  InitReg(MISCREG_CPSR_MODE)
3463  .allPrivileges();
3464  InitReg(MISCREG_CPSR_Q)
3465  .allPrivileges();
3466  InitReg(MISCREG_FPSCR_EXC)
3467  .allPrivileges();
3468  InitReg(MISCREG_FPSCR_QC)
3469  .allPrivileges();
3470  InitReg(MISCREG_LOCKADDR)
3471  .allPrivileges();
3472  InitReg(MISCREG_LOCKFLAG)
3473  .allPrivileges();
3474  InitReg(MISCREG_PRRR_MAIR0)
3475  .mutex()
3476  .banked();
3477  InitReg(MISCREG_PRRR_MAIR0_NS)
3478  .mutex()
3479  .privSecure(!aarch32EL3)
3480  .bankedChild();
3481  InitReg(MISCREG_PRRR_MAIR0_S)
3482  .mutex()
3483  .bankedChild();
3484  InitReg(MISCREG_NMRR_MAIR1)
3485  .mutex()
3486  .banked();
3487  InitReg(MISCREG_NMRR_MAIR1_NS)
3488  .mutex()
3489  .privSecure(!aarch32EL3)
3490  .bankedChild();
3491  InitReg(MISCREG_NMRR_MAIR1_S)
3492  .mutex()
3493  .bankedChild();
3494  InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
3495  .mutex();
3496  InitReg(MISCREG_SCTLR_RST)
3497  .allPrivileges();
3498  InitReg(MISCREG_SEV_MAILBOX)
3499  .allPrivileges();
3500 
3501  // AArch32 CP14 registers
3502  InitReg(MISCREG_DBGDIDR)
3503  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3504  InitReg(MISCREG_DBGDSCRint)
3505  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3506  InitReg(MISCREG_DBGDCCINT)
3507  .unimplemented()
3508  .allPrivileges();
3509  InitReg(MISCREG_DBGDTRTXint)
3510  .unimplemented()
3511  .allPrivileges();
3512  InitReg(MISCREG_DBGDTRRXint)
3513  .unimplemented()
3514  .allPrivileges();
3515  InitReg(MISCREG_DBGWFAR)
3516  .unimplemented()
3517  .allPrivileges();
3518  InitReg(MISCREG_DBGVCR)
3519  .allPrivileges().exceptUserMode();
3520  InitReg(MISCREG_DBGDTRRXext)
3521  .unimplemented()
3522  .allPrivileges();
3523  InitReg(MISCREG_DBGDSCRext)
3524  .allPrivileges();
3525  InitReg(MISCREG_DBGDTRTXext)
3526  .unimplemented()
3527  .allPrivileges();
3528  InitReg(MISCREG_DBGOSECCR)
3529  .unimplemented()
3530  .allPrivileges();
3531  InitReg(MISCREG_DBGBVR0)
3532  .allPrivileges().exceptUserMode();
3533  InitReg(MISCREG_DBGBVR1)
3534  .allPrivileges().exceptUserMode();
3535  InitReg(MISCREG_DBGBVR2)
3536  .allPrivileges().exceptUserMode();
3537  InitReg(MISCREG_DBGBVR3)
3538  .allPrivileges().exceptUserMode();
3539  InitReg(MISCREG_DBGBVR4)
3540  .allPrivileges().exceptUserMode();
3541  InitReg(MISCREG_DBGBVR5)
3542  .allPrivileges().exceptUserMode();
3543  InitReg(MISCREG_DBGBVR6)
3544  .allPrivileges().exceptUserMode();
3545  InitReg(MISCREG_DBGBVR7)
3546  .allPrivileges().exceptUserMode();
3547  InitReg(MISCREG_DBGBVR8)
3548  .allPrivileges().exceptUserMode();
3549  InitReg(MISCREG_DBGBVR9)
3550  .allPrivileges().exceptUserMode();
3551  InitReg(MISCREG_DBGBVR10)
3552  .allPrivileges().exceptUserMode();
3553  InitReg(MISCREG_DBGBVR11)
3554  .allPrivileges().exceptUserMode();
3555  InitReg(MISCREG_DBGBVR12)
3556  .allPrivileges().exceptUserMode();
3557  InitReg(MISCREG_DBGBVR13)
3558  .allPrivileges().exceptUserMode();
3559  InitReg(MISCREG_DBGBVR14)
3560  .allPrivileges().exceptUserMode();
3561  InitReg(MISCREG_DBGBVR15)
3562  .allPrivileges().exceptUserMode();
3563  InitReg(MISCREG_DBGBCR0)
3564  .allPrivileges().exceptUserMode();
3565  InitReg(MISCREG_DBGBCR1)
3566  .allPrivileges().exceptUserMode();
3567  InitReg(MISCREG_DBGBCR2)
3568  .allPrivileges().exceptUserMode();
3569  InitReg(MISCREG_DBGBCR3)
3570  .allPrivileges().exceptUserMode();
3571  InitReg(MISCREG_DBGBCR4)
3572  .allPrivileges().exceptUserMode();
3573  InitReg(MISCREG_DBGBCR5)
3574  .allPrivileges().exceptUserMode();
3575  InitReg(MISCREG_DBGBCR6)
3576  .allPrivileges().exceptUserMode();
3577  InitReg(MISCREG_DBGBCR7)
3578  .allPrivileges().exceptUserMode();
3579  InitReg(MISCREG_DBGBCR8)
3580  .allPrivileges().exceptUserMode();
3581  InitReg(MISCREG_DBGBCR9)
3582  .allPrivileges().exceptUserMode();
3583  InitReg(MISCREG_DBGBCR10)
3584  .allPrivileges().exceptUserMode();
3585  InitReg(MISCREG_DBGBCR11)
3586  .allPrivileges().exceptUserMode();
3587  InitReg(MISCREG_DBGBCR12)
3588  .allPrivileges().exceptUserMode();
3589  InitReg(MISCREG_DBGBCR13)
3590  .allPrivileges().exceptUserMode();
3591  InitReg(MISCREG_DBGBCR14)
3592  .allPrivileges().exceptUserMode();
3593  InitReg(MISCREG_DBGBCR15)
3594  .allPrivileges().exceptUserMode();
3595  InitReg(MISCREG_DBGWVR0)
3596  .allPrivileges().exceptUserMode();
3597  InitReg(MISCREG_DBGWVR1)
3598  .allPrivileges().exceptUserMode();
3599  InitReg(MISCREG_DBGWVR2)
3600  .allPrivileges().exceptUserMode();
3601  InitReg(MISCREG_DBGWVR3)
3602  .allPrivileges().exceptUserMode();
3603  InitReg(MISCREG_DBGWVR4)
3604  .allPrivileges().exceptUserMode();
3605  InitReg(MISCREG_DBGWVR5)
3606  .allPrivileges().exceptUserMode();
3607  InitReg(MISCREG_DBGWVR6)
3608  .allPrivileges().exceptUserMode();
3609  InitReg(MISCREG_DBGWVR7)
3610  .allPrivileges().exceptUserMode();
3611  InitReg(MISCREG_DBGWVR8)
3612  .allPrivileges().exceptUserMode();
3613  InitReg(MISCREG_DBGWVR9)
3614  .allPrivileges().exceptUserMode();
3615  InitReg(MISCREG_DBGWVR10)
3616  .allPrivileges().exceptUserMode();
3617  InitReg(MISCREG_DBGWVR11)
3618  .allPrivileges().exceptUserMode();
3619  InitReg(MISCREG_DBGWVR12)
3620  .allPrivileges().exceptUserMode();
3621  InitReg(MISCREG_DBGWVR13)
3622  .allPrivileges().exceptUserMode();
3623  InitReg(MISCREG_DBGWVR14)
3624  .allPrivileges().exceptUserMode();
3625  InitReg(MISCREG_DBGWVR15)
3626  .allPrivileges().exceptUserMode();
3627  InitReg(MISCREG_DBGWCR0)
3628  .allPrivileges().exceptUserMode();
3629  InitReg(MISCREG_DBGWCR1)
3630  .allPrivileges().exceptUserMode();
3631  InitReg(MISCREG_DBGWCR2)
3632  .allPrivileges().exceptUserMode();
3633  InitReg(MISCREG_DBGWCR3)
3634  .allPrivileges().exceptUserMode();
3635  InitReg(MISCREG_DBGWCR4)
3636  .allPrivileges().exceptUserMode();
3637  InitReg(MISCREG_DBGWCR5)
3638  .allPrivileges().exceptUserMode();
3639  InitReg(MISCREG_DBGWCR6)
3640  .allPrivileges().exceptUserMode();
3641  InitReg(MISCREG_DBGWCR7)
3642  .allPrivileges().exceptUserMode();
3643  InitReg(MISCREG_DBGWCR8)
3644  .allPrivileges().exceptUserMode();
3645  InitReg(MISCREG_DBGWCR9)
3646  .allPrivileges().exceptUserMode();
3647  InitReg(MISCREG_DBGWCR10)
3648  .allPrivileges().exceptUserMode();
3649  InitReg(MISCREG_DBGWCR11)
3650  .allPrivileges().exceptUserMode();
3651  InitReg(MISCREG_DBGWCR12)
3652  .allPrivileges().exceptUserMode();
3653  InitReg(MISCREG_DBGWCR13)
3654  .allPrivileges().exceptUserMode();
3655  InitReg(MISCREG_DBGWCR14)
3656  .allPrivileges().exceptUserMode();
3657  InitReg(MISCREG_DBGWCR15)
3658  .allPrivileges().exceptUserMode();
3659  InitReg(MISCREG_DBGDRAR)
3660  .unimplemented()
3661  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3662  InitReg(MISCREG_DBGBXVR0)
3663  .allPrivileges().exceptUserMode();
3664  InitReg(MISCREG_DBGBXVR1)
3665  .allPrivileges().exceptUserMode();
3666  InitReg(MISCREG_DBGBXVR2)
3667  .allPrivileges().exceptUserMode();
3668  InitReg(MISCREG_DBGBXVR3)
3669  .allPrivileges().exceptUserMode();
3670  InitReg(MISCREG_DBGBXVR4)
3671  .allPrivileges().exceptUserMode();
3672  InitReg(MISCREG_DBGBXVR5)
3673  .allPrivileges().exceptUserMode();
3674  InitReg(MISCREG_DBGBXVR0)
3675  .allPrivileges().exceptUserMode();
3676  InitReg(MISCREG_DBGBXVR6)
3677  .allPrivileges().exceptUserMode();
3678  InitReg(MISCREG_DBGBXVR7)
3679  .allPrivileges().exceptUserMode();
3680  InitReg(MISCREG_DBGBXVR8)
3681  .allPrivileges().exceptUserMode();
3682  InitReg(MISCREG_DBGBXVR9)
3683  .allPrivileges().exceptUserMode();
3684  InitReg(MISCREG_DBGBXVR10)
3685  .allPrivileges().exceptUserMode();
3686  InitReg(MISCREG_DBGBXVR11)
3687  .allPrivileges().exceptUserMode();
3688  InitReg(MISCREG_DBGBXVR12)
3689  .allPrivileges().exceptUserMode();
3690  InitReg(MISCREG_DBGBXVR13)
3691  .allPrivileges().exceptUserMode();
3692  InitReg(MISCREG_DBGBXVR14)
3693  .allPrivileges().exceptUserMode();
3694  InitReg(MISCREG_DBGBXVR15)
3695  .allPrivileges().exceptUserMode();
3696  InitReg(MISCREG_DBGOSLAR)
3697  .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3698  InitReg(MISCREG_DBGOSLSR)
3699  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3700  InitReg(MISCREG_DBGOSDLR)
3701  .unimplemented()
3702  .warnNotFail()
3703  .allPrivileges();
3704  InitReg(MISCREG_DBGPRCR)
3705  .unimplemented()
3706  .allPrivileges();
3707  InitReg(MISCREG_DBGDSAR)
3708  .unimplemented()
3709  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3710  InitReg(MISCREG_DBGCLAIMSET)
3711  .unimplemented()
3712  .allPrivileges();
3713  InitReg(MISCREG_DBGCLAIMCLR)
3714  .unimplemented()
3715  .allPrivileges();
3716  InitReg(MISCREG_DBGAUTHSTATUS)
3717  .unimplemented()
3718  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3719  InitReg(MISCREG_DBGDEVID2)
3720  .unimplemented()
3721  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3722  InitReg(MISCREG_DBGDEVID1)
3723  .unimplemented()
3724  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3725  InitReg(MISCREG_DBGDEVID0)
3726  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3727  InitReg(MISCREG_TEECR)
3728  .unimplemented()
3729  .allPrivileges();
3730  InitReg(MISCREG_JIDR)
3731  .allPrivileges();
3732  InitReg(MISCREG_TEEHBR)
3733  .allPrivileges();
3734  InitReg(MISCREG_JOSCR)
3735  .allPrivileges();
3736  InitReg(MISCREG_JMCR)
3737  .allPrivileges();
3738 
3739  // AArch32 CP15 registers
3740  InitReg(MISCREG_MIDR)
3741  .allPrivileges().exceptUserMode().writes(0);
3742  InitReg(MISCREG_CTR)
3743  .allPrivileges().exceptUserMode().writes(0);
3744  InitReg(MISCREG_TCMTR)
3745  .allPrivileges().exceptUserMode().writes(0);
3746  InitReg(MISCREG_TLBTR)
3747  .allPrivileges().exceptUserMode().writes(0);
3748  InitReg(MISCREG_MPIDR)
3749  .allPrivileges().exceptUserMode().writes(0);
3750  InitReg(MISCREG_REVIDR)
3751  .unimplemented()
3752  .warnNotFail()
3753  .allPrivileges().exceptUserMode().writes(0);
3754  InitReg(MISCREG_ID_PFR0)
3755  .allPrivileges().exceptUserMode().writes(0);
3756  InitReg(MISCREG_ID_PFR1)
3757  .allPrivileges().exceptUserMode().writes(0);
3758  InitReg(MISCREG_ID_DFR0)
3759  .allPrivileges().exceptUserMode().writes(0);
3760  InitReg(MISCREG_ID_AFR0)
3761  .allPrivileges().exceptUserMode().writes(0);
3762  InitReg(MISCREG_ID_MMFR0)
3763  .allPrivileges().exceptUserMode().writes(0);
3764  InitReg(MISCREG_ID_MMFR1)
3765  .allPrivileges().exceptUserMode().writes(0);
3766  InitReg(MISCREG_ID_MMFR2)
3767  .allPrivileges().exceptUserMode().writes(0);
3768  InitReg(MISCREG_ID_MMFR3)
3769  .allPrivileges().exceptUserMode().writes(0);
3770  InitReg(MISCREG_ID_ISAR0)
3771  .allPrivileges().exceptUserMode().writes(0);
3772  InitReg(MISCREG_ID_ISAR1)
3773  .allPrivileges().exceptUserMode().writes(0);
3774  InitReg(MISCREG_ID_ISAR2)
3775  .allPrivileges().exceptUserMode().writes(0);
3776  InitReg(MISCREG_ID_ISAR3)
3777  .allPrivileges().exceptUserMode().writes(0);
3778  InitReg(MISCREG_ID_ISAR4)
3779  .allPrivileges().exceptUserMode().writes(0);
3780  InitReg(MISCREG_ID_ISAR5)
3781  .allPrivileges().exceptUserMode().writes(0);
3782  InitReg(MISCREG_CCSIDR)
3783  .allPrivileges().exceptUserMode().writes(0);
3784  InitReg(MISCREG_CLIDR)
3785  .allPrivileges().exceptUserMode().writes(0);
3786  InitReg(MISCREG_AIDR)
3787  .allPrivileges().exceptUserMode().writes(0);
3788  InitReg(MISCREG_CSSELR)
3789  .banked();
3790  InitReg(MISCREG_CSSELR_NS)
3791  .bankedChild()
3792  .privSecure(!aarch32EL3)
3793  .nonSecure().exceptUserMode();
3794  InitReg(MISCREG_CSSELR_S)
3795  .bankedChild()
3796  .secure().exceptUserMode();
3797  InitReg(MISCREG_VPIDR)
3798  .hyp().monNonSecure();
3799  InitReg(MISCREG_VMPIDR)
3800  .hyp().monNonSecure();
3801  InitReg(MISCREG_SCTLR)
3802  .banked()
3803  // readMiscRegNoEffect() uses this metadata
3804  // despite using children (below) as backing store
3805  .res0(0x8d22c600)
3806  .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3807  | (LSMAOE ? 0 : 0x10)
3808  | (nTLSMD ? 0 : 0x8));
3809  InitReg(MISCREG_SCTLR_NS)
3810  .bankedChild()
3811  .privSecure(!aarch32EL3)
3812  .nonSecure().exceptUserMode();
3813  InitReg(MISCREG_SCTLR_S)
3814  .bankedChild()
3815  .secure().exceptUserMode();
3816  InitReg(MISCREG_ACTLR)
3817  .banked();
3818  InitReg(MISCREG_ACTLR_NS)
3819  .bankedChild()
3820  .privSecure(!aarch32EL3)
3821  .nonSecure().exceptUserMode();
3822  InitReg(MISCREG_ACTLR_S)
3823  .bankedChild()
3824  .secure().exceptUserMode();
3825  InitReg(MISCREG_CPACR)
3826  .allPrivileges().exceptUserMode();
3827  InitReg(MISCREG_SDCR)
3828  .mon();
3829  InitReg(MISCREG_SCR)
3830  .mon().secure().exceptUserMode()
3831  .res0(0xff40) // [31:16], [6]
3832  .res1(0x0030); // [5:4]
3833  InitReg(MISCREG_SDER)
3834  .mon();
3835  InitReg(MISCREG_NSACR)
3836  .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3837  InitReg(MISCREG_HSCTLR)
3838  .hyp().monNonSecure()
3839  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3840  | (IESB ? 0 : 0x200000)
3841  | (EnDA ? 0 : 0x8000000)
3842  | (EnIB ? 0 : 0x40000000)
3843  | (EnIA ? 0 : 0x80000000))
3844  .res1(0x30c50830);
3845  InitReg(MISCREG_HACTLR)
3846  .hyp().monNonSecure();
3847  InitReg(MISCREG_HCR)
3848  .hyp().monNonSecure()
3849  .res0(0x90000000);
3850  InitReg(MISCREG_HCR2)
3851  .hyp().monNonSecure()
3852  .res0(0xffa9ff8c);
3853  InitReg(MISCREG_HDCR)
3854  .hyp().monNonSecure();
3855  InitReg(MISCREG_HCPTR)
3856  .hyp().monNonSecure();
3857  InitReg(MISCREG_HSTR)
3858  .hyp().monNonSecure();
3859  InitReg(MISCREG_HACR)
3860  .unimplemented()
3861  .warnNotFail()
3862  .hyp().monNonSecure();
3863  InitReg(MISCREG_TTBR0)
3864  .banked();
3865  InitReg(MISCREG_TTBR0_NS)
3866  .bankedChild()
3867  .privSecure(!aarch32EL3)
3868  .nonSecure().exceptUserMode();
3869  InitReg(MISCREG_TTBR0_S)
3870  .bankedChild()
3871  .secure().exceptUserMode();
3872  InitReg(MISCREG_TTBR1)
3873  .banked();
3874  InitReg(MISCREG_TTBR1_NS)
3875  .bankedChild()
3876  .privSecure(!aarch32EL3)
3877  .nonSecure().exceptUserMode();
3878  InitReg(MISCREG_TTBR1_S)
3879  .bankedChild()
3880  .secure().exceptUserMode();
3881  InitReg(MISCREG_TTBCR)
3882  .banked();
3883  InitReg(MISCREG_TTBCR_NS)
3884  .bankedChild()
3885  .privSecure(!aarch32EL3)
3886  .nonSecure().exceptUserMode();
3887  InitReg(MISCREG_TTBCR_S)
3888  .bankedChild()
3889  .secure().exceptUserMode();
3890  InitReg(MISCREG_HTCR)
3891  .hyp().monNonSecure();
3892  InitReg(MISCREG_VTCR)
3893  .hyp().monNonSecure();
3894  InitReg(MISCREG_DACR)
3895  .banked();
3896  InitReg(MISCREG_DACR_NS)
3897  .bankedChild()
3898  .privSecure(!aarch32EL3)
3899  .nonSecure().exceptUserMode();
3900  InitReg(MISCREG_DACR_S)
3901  .bankedChild()
3902  .secure().exceptUserMode();
3903  InitReg(MISCREG_DFSR)
3904  .banked();
3905  InitReg(MISCREG_DFSR_NS)
3906  .bankedChild()
3907  .privSecure(!aarch32EL3)
3908  .nonSecure().exceptUserMode();
3909  InitReg(MISCREG_DFSR_S)
3910  .bankedChild()
3911  .secure().exceptUserMode();
3912  InitReg(MISCREG_IFSR)
3913  .banked();
3914  InitReg(MISCREG_IFSR_NS)
3915  .bankedChild()
3916  .privSecure(!aarch32EL3)
3917  .nonSecure().exceptUserMode();
3918  InitReg(MISCREG_IFSR_S)
3919  .bankedChild()
3920  .secure().exceptUserMode();
3921  InitReg(MISCREG_ADFSR)
3922  .unimplemented()
3923  .warnNotFail()
3924  .banked();
3925  InitReg(MISCREG_ADFSR_NS)
3926  .unimplemented()
3927  .warnNotFail()
3928  .bankedChild()
3929  .privSecure(!aarch32EL3)
3930  .nonSecure().exceptUserMode();
3931  InitReg(MISCREG_ADFSR_S)
3932  .unimplemented()
3933  .warnNotFail()
3934  .bankedChild()
3935  .secure().exceptUserMode();
3936  InitReg(MISCREG_AIFSR)
3937  .unimplemented()
3938  .warnNotFail()
3939  .banked();
3940  InitReg(MISCREG_AIFSR_NS)
3941  .unimplemented()
3942  .warnNotFail()
3943  .bankedChild()
3944  .privSecure(!aarch32EL3)
3945  .nonSecure().exceptUserMode();
3946  InitReg(MISCREG_AIFSR_S)
3947  .unimplemented()
3948  .warnNotFail()
3949  .bankedChild()
3950  .secure().exceptUserMode();
3951  InitReg(MISCREG_HADFSR)
3952  .hyp().monNonSecure();
3953  InitReg(MISCREG_HAIFSR)
3954  .hyp().monNonSecure();
3955  InitReg(MISCREG_HSR)
3956  .hyp().monNonSecure();
3957  InitReg(MISCREG_DFAR)
3958  .banked();
3959  InitReg(MISCREG_DFAR_NS)
3960  .bankedChild()
3961  .privSecure(!aarch32EL3)
3962  .nonSecure().exceptUserMode();
3963  InitReg(MISCREG_DFAR_S)
3964  .bankedChild()
3965  .secure().exceptUserMode();
3966  InitReg(MISCREG_IFAR)
3967  .banked();
3968  InitReg(MISCREG_IFAR_NS)
3969  .bankedChild()
3970  .privSecure(!aarch32EL3)
3971  .nonSecure().exceptUserMode();
3972  InitReg(MISCREG_IFAR_S)
3973  .bankedChild()
3974  .secure().exceptUserMode();
3975  InitReg(MISCREG_HDFAR)
3976  .hyp().monNonSecure();
3977  InitReg(MISCREG_HIFAR)
3978  .hyp().monNonSecure();
3979  InitReg(MISCREG_HPFAR)
3980  .hyp().monNonSecure();
3981  InitReg(MISCREG_ICIALLUIS)
3982  .unimplemented()
3983  .warnNotFail()
3984  .writes(1).exceptUserMode();
3985  InitReg(MISCREG_BPIALLIS)
3986  .unimplemented()
3987  .warnNotFail()
3988  .writes(1).exceptUserMode();
3989  InitReg(MISCREG_PAR)
3990  .banked();
3991  InitReg(MISCREG_PAR_NS)
3992  .bankedChild()
3993  .privSecure(!aarch32EL3)
3994  .nonSecure().exceptUserMode();
3995  InitReg(MISCREG_PAR_S)
3996  .bankedChild()
3997  .secure().exceptUserMode();
3998  InitReg(MISCREG_ICIALLU)
3999  .writes(1).exceptUserMode();
4000  InitReg(MISCREG_ICIMVAU)
4001  .unimplemented()
4002  .warnNotFail()
4003  .writes(1).exceptUserMode();
4004  InitReg(MISCREG_CP15ISB)
4005  .writes(1);
4006  InitReg(MISCREG_BPIALL)
4007  .unimplemented()
4008  .warnNotFail()
4009  .writes(1).exceptUserMode();
4010  InitReg(MISCREG_BPIMVA)
4011  .unimplemented()
4012  .warnNotFail()
4013  .writes(1).exceptUserMode();
4014  InitReg(MISCREG_DCIMVAC)
4015  .unimplemented()
4016  .warnNotFail()
4017  .writes(1).exceptUserMode();
4018  InitReg(MISCREG_DCISW)
4019  .unimplemented()
4020  .warnNotFail()
4021  .writes(1).exceptUserMode();
4022  InitReg(MISCREG_ATS1CPR)
4023  .writes(1).exceptUserMode();
4024  InitReg(MISCREG_ATS1CPW)
4025  .writes(1).exceptUserMode();
4026  InitReg(MISCREG_ATS1CUR)
4027  .writes(1).exceptUserMode();
4028  InitReg(MISCREG_ATS1CUW)
4029  .writes(1).exceptUserMode();
4030  InitReg(MISCREG_ATS12NSOPR)
4031  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4032  InitReg(MISCREG_ATS12NSOPW)
4033  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4034  InitReg(MISCREG_ATS12NSOUR)
4035  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4036  InitReg(MISCREG_ATS12NSOUW)
4037  .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
4038  InitReg(MISCREG_DCCMVAC)
4039  .writes(1).exceptUserMode();
4040  InitReg(MISCREG_DCCSW)
4041  .unimplemented()
4042  .warnNotFail()
4043  .writes(1).exceptUserMode();
4044  InitReg(MISCREG_CP15DSB)
4045  .writes(1);
4046  InitReg(MISCREG_CP15DMB)
4047  .writes(1);
4048  InitReg(MISCREG_DCCMVAU)
4049  .unimplemented()
4050  .warnNotFail()
4051  .writes(1).exceptUserMode();
4052  InitReg(MISCREG_DCCIMVAC)
4053  .unimplemented()
4054  .warnNotFail()
4055  .writes(1).exceptUserMode();
4056  InitReg(MISCREG_DCCISW)
4057  .unimplemented()
4058  .warnNotFail()
4059  .writes(1).exceptUserMode();
4060  InitReg(MISCREG_ATS1HR)
4061  .monNonSecureWrite().hypWrite();
4062  InitReg(MISCREG_ATS1HW)
4063  .monNonSecureWrite().hypWrite();
4064  InitReg(MISCREG_TLBIALLIS)
4065  .writes(1).exceptUserMode();
4066  InitReg(MISCREG_TLBIMVAIS)
4067  .writes(1).exceptUserMode();
4068  InitReg(MISCREG_TLBIASIDIS)
4069  .writes(1).exceptUserMode();
4070  InitReg(MISCREG_TLBIMVAAIS)
4071  .writes(1).exceptUserMode();
4072  InitReg(MISCREG_TLBIMVALIS)
4073  .writes(1).exceptUserMode();
4074  InitReg(MISCREG_TLBIMVAALIS)
4075  .writes(1).exceptUserMode();
4076  InitReg(MISCREG_ITLBIALL)
4077  .writes(1).exceptUserMode();
4078  InitReg(MISCREG_ITLBIMVA)
4079  .writes(1).exceptUserMode();
4080  InitReg(MISCREG_ITLBIASID)
4081  .writes(1).exceptUserMode();
4082  InitReg(MISCREG_DTLBIALL)
4083  .writes(1).exceptUserMode();
4084  InitReg(MISCREG_DTLBIMVA)
4085  .writes(1).exceptUserMode();
4086  InitReg(MISCREG_DTLBIASID)
4087  .writes(1).exceptUserMode();
4088  InitReg(MISCREG_TLBIALL)
4089  .writes(1).exceptUserMode();
4090  InitReg(MISCREG_TLBIMVA)
4091  .writes(1).exceptUserMode();
4092  InitReg(MISCREG_TLBIASID)
4093  .writes(1).exceptUserMode();
4094  InitReg(MISCREG_TLBIMVAA)
4095  .writes(1).exceptUserMode();
4096  InitReg(MISCREG_TLBIMVAL)
4097  .writes(1).exceptUserMode();
4098  InitReg(MISCREG_TLBIMVAAL)
4099  .writes(1).exceptUserMode();
4100  InitReg(MISCREG_TLBIIPAS2IS)
4101  .monNonSecureWrite().hypWrite();
4102  InitReg(MISCREG_TLBIIPAS2LIS)
4103  .monNonSecureWrite().hypWrite();
4104  InitReg(MISCREG_TLBIALLHIS)
4105  .monNonSecureWrite().hypWrite();
4106  InitReg(MISCREG_TLBIMVAHIS)
4107  .monNonSecureWrite().hypWrite();
4108  InitReg(MISCREG_TLBIALLNSNHIS)
4109  .monNonSecureWrite().hypWrite();
4110  InitReg(MISCREG_TLBIMVALHIS)
4111  .monNonSecureWrite().hypWrite();
4112  InitReg(MISCREG_TLBIIPAS2)
4113  .monNonSecureWrite().hypWrite();
4114  InitReg(MISCREG_TLBIIPAS2L)
4115  .monNonSecureWrite().hypWrite();
4116  InitReg(MISCREG_TLBIALLH)
4117  .monNonSecureWrite().hypWrite();
4118  InitReg(MISCREG_TLBIMVAH)
4119  .monNonSecureWrite().hypWrite();
4120  InitReg(MISCREG_TLBIALLNSNH)
4121  .monNonSecureWrite().hypWrite();
4122  InitReg(MISCREG_TLBIMVALH)
4123  .monNonSecureWrite().hypWrite();
4124  InitReg(MISCREG_PMCR)
4125  .allPrivileges();
4126  InitReg(MISCREG_PMCNTENSET)
4127  .allPrivileges();
4128  InitReg(MISCREG_PMCNTENCLR)
4129  .allPrivileges();
4130  InitReg(MISCREG_PMOVSR)
4131  .allPrivileges();
4132  InitReg(MISCREG_PMSWINC)
4133  .allPrivileges();
4134  InitReg(MISCREG_PMSELR)
4135  .allPrivileges();
4136  InitReg(MISCREG_PMCEID0)
4137  .allPrivileges();
4138  InitReg(MISCREG_PMCEID1)
4139  .allPrivileges();
4140  InitReg(MISCREG_PMCCNTR)
4141  .allPrivileges();
4142  InitReg(MISCREG_PMXEVTYPER)
4143  .allPrivileges();
4144  InitReg(MISCREG_PMCCFILTR)
4145  .allPrivileges();
4146  InitReg(MISCREG_PMXEVCNTR)
4147  .allPrivileges();
4148  InitReg(MISCREG_PMUSERENR)
4149  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
4150  InitReg(MISCREG_PMINTENSET)
4151  .allPrivileges().exceptUserMode();
4152  InitReg(MISCREG_PMINTENCLR)
4153  .allPrivileges().exceptUserMode();
4154  InitReg(MISCREG_PMOVSSET)
4155  .unimplemented()
4156  .allPrivileges();
4157  InitReg(MISCREG_L2CTLR)
4158  .allPrivileges().exceptUserMode();
4159  InitReg(MISCREG_L2ECTLR)
4160  .unimplemented()
4161  .allPrivileges().exceptUserMode();
4162  InitReg(MISCREG_PRRR)
4163  .banked();
4164  InitReg(MISCREG_PRRR_NS)
4165  .bankedChild()
4166  .privSecure(!aarch32EL3)
4167  .nonSecure().exceptUserMode();
4168  InitReg(MISCREG_PRRR_S)
4169  .bankedChild()
4170  .secure().exceptUserMode();
4171  InitReg(MISCREG_MAIR0)
4172  .banked();
4173  InitReg(MISCREG_MAIR0_NS)
4174  .bankedChild()
4175  .privSecure(!aarch32EL3)
4176  .nonSecure().exceptUserMode();
4177  InitReg(MISCREG_MAIR0_S)
4178  .bankedChild()
4179  .secure().exceptUserMode();
4180  InitReg(MISCREG_NMRR)
4181  .banked();
4182  InitReg(MISCREG_NMRR_NS)
4183  .bankedChild()
4184  .privSecure(!aarch32EL3)
4185  .nonSecure().exceptUserMode();
4186  InitReg(MISCREG_NMRR_S)
4187  .bankedChild()
4188  .secure().exceptUserMode();
4189  InitReg(MISCREG_MAIR1)
4190  .banked();
4191  InitReg(MISCREG_MAIR1_NS)
4192  .bankedChild()
4193  .privSecure(!aarch32EL3)
4194  .nonSecure().exceptUserMode();
4195  InitReg(MISCREG_MAIR1_S)
4196  .bankedChild()
4197  .secure().exceptUserMode();
4198  InitReg(MISCREG_AMAIR0)
4199  .banked();
4200  InitReg(MISCREG_AMAIR0_NS)
4201  .bankedChild()
4202  .privSecure(!aarch32EL3)
4203  .nonSecure().exceptUserMode();
4204  InitReg(MISCREG_AMAIR0_S)
4205  .bankedChild()
4206  .secure().exceptUserMode();
4207  InitReg(MISCREG_AMAIR1)
4208  .banked();
4209  InitReg(MISCREG_AMAIR1_NS)
4210  .bankedChild()
4211  .privSecure(!aarch32EL3)
4212  .nonSecure().exceptUserMode();
4213  InitReg(MISCREG_AMAIR1_S)
4214  .bankedChild()
4215  .secure().exceptUserMode();
4216  InitReg(MISCREG_HMAIR0)
4217  .hyp().monNonSecure();
4218  InitReg(MISCREG_HMAIR1)
4219  .hyp().monNonSecure();
4220  InitReg(MISCREG_HAMAIR0)
4221  .unimplemented()
4222  .warnNotFail()
4223  .hyp().monNonSecure();
4224  InitReg(MISCREG_HAMAIR1)
4225  .unimplemented()
4226  .warnNotFail()
4227  .hyp().monNonSecure();
4228  InitReg(MISCREG_VBAR)
4229  .banked();
4230  InitReg(MISCREG_VBAR_NS)
4231  .bankedChild()
4232  .privSecure(!aarch32EL3)
4233  .nonSecure().exceptUserMode();
4234  InitReg(MISCREG_VBAR_S)
4235  .bankedChild()
4236  .secure().exceptUserMode();
4237  InitReg(MISCREG_MVBAR)
4238  .mon().secure()
4239  .hypRead(FullSystem && system->highestEL() == EL2)
4240  .privRead(FullSystem && system->highestEL() == EL1)
4241  .exceptUserMode();
4242  InitReg(MISCREG_RMR)
4243  .unimplemented()
4244  .mon().secure().exceptUserMode();
4245  InitReg(MISCREG_ISR)
4246  .allPrivileges().exceptUserMode().writes(0);
4247  InitReg(MISCREG_HVBAR)
4248  .hyp().monNonSecure()
4249  .res0(0x1f);
4250  InitReg(MISCREG_FCSEIDR)
4251  .unimplemented()
4252  .warnNotFail()
4253  .allPrivileges().exceptUserMode();
4254  InitReg(MISCREG_CONTEXTIDR)
4255  .banked();
4256  InitReg(MISCREG_CONTEXTIDR_NS)
4257  .bankedChild()
4258  .privSecure(!aarch32EL3)
4259  .nonSecure().exceptUserMode();
4260  InitReg(MISCREG_CONTEXTIDR_S)
4261  .bankedChild()
4262  .secure().exceptUserMode();
4263  InitReg(MISCREG_TPIDRURW)
4264  .banked();
4265  InitReg(MISCREG_TPIDRURW_NS)
4266  .bankedChild()
4267  .allPrivileges()
4268  .privSecure(!aarch32EL3)
4269  .monSecure(0);
4270  InitReg(MISCREG_TPIDRURW_S)
4271  .bankedChild()
4272  .secure();
4273  InitReg(MISCREG_TPIDRURO)
4274  .banked();
4275  InitReg(MISCREG_TPIDRURO_NS)
4276  .bankedChild()
4277  .allPrivileges()
4278  .userNonSecureWrite(0).userSecureRead(1)
4279  .privSecure(!aarch32EL3)
4280  .monSecure(0);
4281  InitReg(MISCREG_TPIDRURO_S)
4282  .bankedChild()
4283  .secure().userSecureWrite(0);
4284  InitReg(MISCREG_TPIDRPRW)
4285  .banked();
4286  InitReg(MISCREG_TPIDRPRW_NS)
4287  .bankedChild()
4288  .nonSecure().exceptUserMode()
4289  .privSecure(!aarch32EL3);
4290  InitReg(MISCREG_TPIDRPRW_S)
4291  .bankedChild()
4292  .secure().exceptUserMode();
4293  InitReg(MISCREG_HTPIDR)
4294  .hyp().monNonSecure();
4295  // BEGIN Generic Timer (AArch32)
4296  InitReg(MISCREG_CNTFRQ)
4297  .reads(1)
4298  .highest(system)
4299  .privSecureWrite(aarch32EL3);
4300  InitReg(MISCREG_CNTPCT)
4301  .unverifiable()
4302  .reads(1);
4303  InitReg(MISCREG_CNTVCT)
4304  .unverifiable()
4305  .reads(1);
4306  InitReg(MISCREG_CNTP_CTL)
4307  .banked();
4308  InitReg(MISCREG_CNTP_CTL_NS)
4309  .bankedChild()
4310  .nonSecure()
4311  .privSecure(!aarch32EL3)
4312  .res0(0xfffffff8);
4313  InitReg(MISCREG_CNTP_CTL_S)
4314  .bankedChild()
4315  .secure()
4316  .privSecure(aarch32EL3)
4317  .res0(0xfffffff8);
4318  InitReg(MISCREG_CNTP_CVAL)
4319  .banked();
4320  InitReg(MISCREG_CNTP_CVAL_NS)
4321  .bankedChild()
4322  .nonSecure()
4323  .privSecure(!aarch32EL3);
4324  InitReg(MISCREG_CNTP_CVAL_S)
4325  .bankedChild()
4326  .secure()
4327  .privSecure(aarch32EL3);
4328  InitReg(MISCREG_CNTP_TVAL)
4329  .banked();
4330  InitReg(MISCREG_CNTP_TVAL_NS)
4331  .bankedChild()
4332  .nonSecure()
4333  .privSecure(!aarch32EL3);
4334  InitReg(MISCREG_CNTP_TVAL_S)
4335  .bankedChild()
4336  .secure()
4337  .privSecure(aarch32EL3);
4338  InitReg(MISCREG_CNTV_CTL)
4339  .allPrivileges()
4340  .res0(0xfffffff8);
4341  InitReg(MISCREG_CNTV_CVAL)
4342  .allPrivileges();
4343  InitReg(MISCREG_CNTV_TVAL)
4344  .allPrivileges();
4345  InitReg(MISCREG_CNTKCTL)
4346  .allPrivileges()
4347  .exceptUserMode()
4348  .res0(0xfffdfc00);
4349  InitReg(MISCREG_CNTHCTL)
4350  .monNonSecure()
4351  .hyp()
4352  .res0(0xfffdff00);
4353  InitReg(MISCREG_CNTHP_CTL)
4354  .monNonSecure()
4355  .hyp()
4356  .res0(0xfffffff8);
4357  InitReg(MISCREG_CNTHP_CVAL)
4358  .monNonSecure()
4359  .hyp();
4360  InitReg(MISCREG_CNTHP_TVAL)
4361  .monNonSecure()
4362  .hyp();
4363  InitReg(MISCREG_CNTVOFF)
4364  .monNonSecure()
4365  .hyp();
4366  // END Generic Timer (AArch32)
4367  InitReg(MISCREG_IL1DATA0)
4368  .unimplemented()
4369  .allPrivileges().exceptUserMode();
4370  InitReg(MISCREG_IL1DATA1)
4371  .unimplemented()
4372  .allPrivileges().exceptUserMode();
4373  InitReg(MISCREG_IL1DATA2)
4374  .unimplemented()
4375  .allPrivileges().exceptUserMode();
4376  InitReg(MISCREG_IL1DATA3)
4377  .unimplemented()
4378  .allPrivileges().exceptUserMode();
4379  InitReg(MISCREG_DL1DATA0)
4380  .unimplemented()
4381  .allPrivileges().exceptUserMode();
4382  InitReg(MISCREG_DL1DATA1)
4383  .unimplemented()
4384  .allPrivileges().exceptUserMode();
4385  InitReg(MISCREG_DL1DATA2)
4386  .unimplemented()
4387  .allPrivileges().exceptUserMode();
4388  InitReg(MISCREG_DL1DATA3)
4389  .unimplemented()
4390  .allPrivileges().exceptUserMode();
4391  InitReg(MISCREG_DL1DATA4)
4392  .unimplemented()
4393  .allPrivileges().exceptUserMode();
4394  InitReg(MISCREG_RAMINDEX)
4395  .unimplemented()
4396  .writes(1).exceptUserMode();
4397  InitReg(MISCREG_L2ACTLR)
4398  .unimplemented()
4399  .allPrivileges().exceptUserMode();
4400  InitReg(MISCREG_CBAR)
4401  .unimplemented()
4402  .allPrivileges().exceptUserMode().writes(0);
4403  InitReg(MISCREG_HTTBR)
4404  .hyp().monNonSecure();
4405  InitReg(MISCREG_VTTBR)
4406  .hyp().monNonSecure();
4407  InitReg(MISCREG_CPUMERRSR)
4408  .unimplemented()
4409  .allPrivileges().exceptUserMode();
4410  InitReg(MISCREG_L2MERRSR)
4411  .unimplemented()
4412  .warnNotFail()
4413  .allPrivileges().exceptUserMode();
4414 
4415  // AArch64 registers (Op0=2);
4416  InitReg(MISCREG_MDCCINT_EL1)
4417  .allPrivileges();
4418  InitReg(MISCREG_OSDTRRX_EL1)
4419  .allPrivileges()
4420  .mapsTo(MISCREG_DBGDTRRXext);
4421  InitReg(MISCREG_MDSCR_EL1)
4422  .allPrivileges()
4423  .mapsTo(MISCREG_DBGDSCRext);
4424  InitReg(MISCREG_OSDTRTX_EL1)
4425  .allPrivileges()
4426  .mapsTo(MISCREG_DBGDTRTXext);
4427  InitReg(MISCREG_OSECCR_EL1)
4428  .allPrivileges()
4429  .mapsTo(MISCREG_DBGOSECCR);
4430  InitReg(MISCREG_DBGBVR0_EL1)
4431  .allPrivileges().exceptUserMode()
4432  .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
4433  InitReg(MISCREG_DBGBVR1_EL1)
4434  .allPrivileges().exceptUserMode()
4435  .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
4436  InitReg(MISCREG_DBGBVR2_EL1)
4437  .allPrivileges().exceptUserMode()
4438  .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
4439  InitReg(MISCREG_DBGBVR3_EL1)
4440  .allPrivileges().exceptUserMode()
4441  .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
4442  InitReg(MISCREG_DBGBVR4_EL1)
4443  .allPrivileges().exceptUserMode()
4444  .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
4445  InitReg(MISCREG_DBGBVR5_EL1)
4446  .allPrivileges().exceptUserMode()
4447  .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
4448  InitReg(MISCREG_DBGBVR6_EL1)
4449  .allPrivileges().exceptUserMode()
4450  .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
4451  InitReg(MISCREG_DBGBVR7_EL1)
4452  .allPrivileges().exceptUserMode()
4453  .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
4454  InitReg(MISCREG_DBGBVR8_EL1)
4455  .allPrivileges().exceptUserMode()
4456  .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
4457  InitReg(MISCREG_DBGBVR9_EL1)
4458  .allPrivileges().exceptUserMode()
4459  .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
4460  InitReg(MISCREG_DBGBVR10_EL1)
4461  .allPrivileges().exceptUserMode()
4462  .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
4463  InitReg(MISCREG_DBGBVR11_EL1)
4464  .allPrivileges().exceptUserMode()
4465  .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
4466  InitReg(MISCREG_DBGBVR12_EL1)
4467  .allPrivileges().exceptUserMode()
4468  .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
4469  InitReg(MISCREG_DBGBVR13_EL1)
4470  .allPrivileges().exceptUserMode()
4471  .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
4472  InitReg(MISCREG_DBGBVR14_EL1)
4473  .allPrivileges().exceptUserMode()
4474  .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
4475  InitReg(MISCREG_DBGBVR15_EL1)
4476  .allPrivileges().exceptUserMode()
4477  .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
4478  InitReg(MISCREG_DBGBCR0_EL1)
4479  .allPrivileges().exceptUserMode()
4480  .mapsTo(MISCREG_DBGBCR0);
4481  InitReg(MISCREG_DBGBCR1_EL1)
4482  .allPrivileges().exceptUserMode()
4483  .mapsTo(MISCREG_DBGBCR1);
4484  InitReg(MISCREG_DBGBCR2_EL1)
4485  .allPrivileges().exceptUserMode()
4486  .mapsTo(MISCREG_DBGBCR2);
4487  InitReg(MISCREG_DBGBCR3_EL1)
4488  .allPrivileges().exceptUserMode()
4489  .mapsTo(MISCREG_DBGBCR3);
4490  InitReg(MISCREG_DBGBCR4_EL1)
4491  .allPrivileges().exceptUserMode()
4492  .mapsTo(MISCREG_DBGBCR4);
4493  InitReg(MISCREG_DBGBCR5_EL1)
4494  .allPrivileges().exceptUserMode()
4495  .mapsTo(MISCREG_DBGBCR5);
4496  InitReg(MISCREG_DBGBCR6_EL1)
4497  .allPrivileges().exceptUserMode()
4498  .mapsTo(MISCREG_DBGBCR6);
4499  InitReg(MISCREG_DBGBCR7_EL1)
4500  .allPrivileges().exceptUserMode()
4501  .mapsTo(MISCREG_DBGBCR7);
4502  InitReg(MISCREG_DBGBCR8_EL1)
4503  .allPrivileges().exceptUserMode()
4504  .mapsTo(MISCREG_DBGBCR8);
4505  InitReg(MISCREG_DBGBCR9_EL1)
4506  .allPrivileges().exceptUserMode()
4507  .mapsTo(MISCREG_DBGBCR9);
4508  InitReg(MISCREG_DBGBCR10_EL1)
4509  .allPrivileges().exceptUserMode()
4510  .mapsTo(MISCREG_DBGBCR10);
4511  InitReg(MISCREG_DBGBCR11_EL1)
4512  .allPrivileges().exceptUserMode()
4513  .mapsTo(MISCREG_DBGBCR11);
4514  InitReg(MISCREG_DBGBCR12_EL1)
4515  .allPrivileges().exceptUserMode()
4516  .mapsTo(MISCREG_DBGBCR12);
4517  InitReg(MISCREG_DBGBCR13_EL1)
4518  .allPrivileges().exceptUserMode()
4519  .mapsTo(MISCREG_DBGBCR13);
4520  InitReg(MISCREG_DBGBCR14_EL1)
4521  .allPrivileges().exceptUserMode()
4522  .mapsTo(MISCREG_DBGBCR14);
4523  InitReg(MISCREG_DBGBCR15_EL1)
4524  .allPrivileges().exceptUserMode()
4525  .mapsTo(MISCREG_DBGBCR15);
4526  InitReg(MISCREG_DBGWVR0_EL1)
4527  .allPrivileges().exceptUserMode()
4528  .mapsTo(MISCREG_DBGWVR0);
4529  InitReg(MISCREG_DBGWVR1_EL1)
4530  .allPrivileges().exceptUserMode()
4531  .mapsTo(MISCREG_DBGWVR1);
4532  InitReg(MISCREG_DBGWVR2_EL1)
4533  .allPrivileges().exceptUserMode()
4534  .mapsTo(MISCREG_DBGWVR2);
4535  InitReg(MISCREG_DBGWVR3_EL1)
4536  .allPrivileges().exceptUserMode()
4537  .mapsTo(MISCREG_DBGWVR3);
4538  InitReg(MISCREG_DBGWVR4_EL1)
4539  .allPrivileges().exceptUserMode()
4540  .mapsTo(MISCREG_DBGWVR4);
4541  InitReg(MISCREG_DBGWVR5_EL1)
4542  .allPrivileges().exceptUserMode()
4543  .mapsTo(MISCREG_DBGWVR5);
4544  InitReg(MISCREG_DBGWVR6_EL1)
4545  .allPrivileges().exceptUserMode()
4546  .mapsTo(MISCREG_DBGWVR6);
4547  InitReg(MISCREG_DBGWVR7_EL1)
4548  .allPrivileges().exceptUserMode()
4549  .mapsTo(MISCREG_DBGWVR7);
4550  InitReg(MISCREG_DBGWVR8_EL1)
4551  .allPrivileges().exceptUserMode()
4552  .mapsTo(MISCREG_DBGWVR8);
4553  InitReg(MISCREG_DBGWVR9_EL1)
4554  .allPrivileges().exceptUserMode()
4555  .mapsTo(MISCREG_DBGWVR9);
4556  InitReg(MISCREG_DBGWVR10_EL1)
4557  .allPrivileges().exceptUserMode()
4558  .mapsTo(MISCREG_DBGWVR10);
4559  InitReg(MISCREG_DBGWVR11_EL1)
4560  .allPrivileges().exceptUserMode()
4561  .mapsTo(MISCREG_DBGWVR11);
4562  InitReg(MISCREG_DBGWVR12_EL1)
4563  .allPrivileges().exceptUserMode()
4564  .mapsTo(MISCREG_DBGWVR12);
4565  InitReg(MISCREG_DBGWVR13_EL1)
4566  .allPrivileges().exceptUserMode()
4567  .mapsTo(MISCREG_DBGWVR13);
4568  InitReg(MISCREG_DBGWVR14_EL1)
4569  .allPrivileges().exceptUserMode()
4570  .mapsTo(MISCREG_DBGWVR14);
4571  InitReg(MISCREG_DBGWVR15_EL1)
4572  .allPrivileges().exceptUserMode()
4573  .mapsTo(MISCREG_DBGWVR15);
4574  InitReg(MISCREG_DBGWCR0_EL1)
4575  .allPrivileges().exceptUserMode()
4576  .mapsTo(MISCREG_DBGWCR0);
4577  InitReg(MISCREG_DBGWCR1_EL1)
4578  .allPrivileges().exceptUserMode()
4579  .mapsTo(MISCREG_DBGWCR1);
4580  InitReg(MISCREG_DBGWCR2_EL1)
4581  .allPrivileges().exceptUserMode()
4582  .mapsTo(MISCREG_DBGWCR2);
4583  InitReg(MISCREG_DBGWCR3_EL1)
4584  .allPrivileges().exceptUserMode()
4585  .mapsTo(MISCREG_DBGWCR3);
4586  InitReg(MISCREG_DBGWCR4_EL1)
4587  .allPrivileges().exceptUserMode()
4588  .mapsTo(MISCREG_DBGWCR4);
4589  InitReg(MISCREG_DBGWCR5_EL1)
4590  .allPrivileges().exceptUserMode()
4591  .mapsTo(MISCREG_DBGWCR5);
4592  InitReg(MISCREG_DBGWCR6_EL1)
4593  .allPrivileges().exceptUserMode()
4594  .mapsTo(MISCREG_DBGWCR6);
4595  InitReg(MISCREG_DBGWCR7_EL1)
4596  .allPrivileges().exceptUserMode()
4597  .mapsTo(MISCREG_DBGWCR7);
4598  InitReg(MISCREG_DBGWCR8_EL1)
4599  .allPrivileges().exceptUserMode()
4600  .mapsTo(MISCREG_DBGWCR8);
4601  InitReg(MISCREG_DBGWCR9_EL1)
4602  .allPrivileges().exceptUserMode()
4603  .mapsTo(MISCREG_DBGWCR9);
4604  InitReg(MISCREG_DBGWCR10_EL1)
4605  .allPrivileges().exceptUserMode()
4606  .mapsTo(MISCREG_DBGWCR10);
4607  InitReg(MISCREG_DBGWCR11_EL1)
4608  .allPrivileges().exceptUserMode()
4609  .mapsTo(MISCREG_DBGWCR11);
4610  InitReg(MISCREG_DBGWCR12_EL1)
4611  .allPrivileges().exceptUserMode()
4612  .mapsTo(MISCREG_DBGWCR12);
4613  InitReg(MISCREG_DBGWCR13_EL1)
4614  .allPrivileges().exceptUserMode()
4615  .mapsTo(MISCREG_DBGWCR13);
4616  InitReg(MISCREG_DBGWCR14_EL1)
4617  .allPrivileges().exceptUserMode()
4618  .mapsTo(MISCREG_DBGWCR14);
4619  InitReg(MISCREG_DBGWCR15_EL1)
4620  .allPrivileges().exceptUserMode()
4621  .mapsTo(MISCREG_DBGWCR15);
4622  InitReg(MISCREG_MDCCSR_EL0)
4623  .allPrivileges().writes(0)
4624  //monSecureWrite(0).monNonSecureWrite(0)
4625  .mapsTo(MISCREG_DBGDSCRint);
4626  InitReg(MISCREG_MDDTR_EL0)
4627  .allPrivileges();
4628  InitReg(MISCREG_MDDTRTX_EL0)
4629  .allPrivileges();
4630  InitReg(MISCREG_MDDTRRX_EL0)
4631  .allPrivileges();
4632  InitReg(MISCREG_DBGVCR32_EL2)
4633  .hyp().mon()
4634  .mapsTo(MISCREG_DBGVCR);
4635  InitReg(MISCREG_MDRAR_EL1)
4636  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4637  .mapsTo(MISCREG_DBGDRAR);
4638  InitReg(MISCREG_OSLAR_EL1)
4639  .allPrivileges().monSecureRead(0).monNonSecureRead(0)
4640  .mapsTo(MISCREG_DBGOSLAR);
4641  InitReg(MISCREG_OSLSR_EL1)
4642  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4643  .mapsTo(MISCREG_DBGOSLSR);
4644  InitReg(MISCREG_OSDLR_EL1)
4645  .allPrivileges()
4646  .mapsTo(MISCREG_DBGOSDLR);
4647  InitReg(MISCREG_DBGPRCR_EL1)
4648  .allPrivileges()
4649  .mapsTo(MISCREG_DBGPRCR);
4650  InitReg(MISCREG_DBGCLAIMSET_EL1)
4651  .allPrivileges()
4652  .mapsTo(MISCREG_DBGCLAIMSET);
4653  InitReg(MISCREG_DBGCLAIMCLR_EL1)
4654  .allPrivileges()
4655  .mapsTo(MISCREG_DBGCLAIMCLR);
4656  InitReg(MISCREG_DBGAUTHSTATUS_EL1)
4657  .allPrivileges().monSecureWrite(0).monNonSecureWrite(0)
4658  .mapsTo(MISCREG_DBGAUTHSTATUS);
4659  InitReg(MISCREG_TEECR32_EL1);
4660  InitReg(MISCREG_TEEHBR32_EL1);
4661 
4662  // AArch64 registers (Op0=1,3);
4663  InitReg(MISCREG_MIDR_EL1)
4664  .allPrivileges().exceptUserMode().writes(0);
4665  InitReg(MISCREG_MPIDR_EL1)
4666  .allPrivileges().exceptUserMode().writes(0);
4667  InitReg(MISCREG_REVIDR_EL1)
4668  .allPrivileges().exceptUserMode().writes(0);
4669  InitReg(MISCREG_ID_PFR0_EL1)
4670  .allPrivileges().exceptUserMode().writes(0)
4671  .mapsTo(MISCREG_ID_PFR0);
4672  InitReg(MISCREG_ID_PFR1_EL1)
4673  .allPrivileges().exceptUserMode().writes(0)
4674  .mapsTo(MISCREG_ID_PFR1);
4675  InitReg(MISCREG_ID_DFR0_EL1)
4676  .allPrivileges().exceptUserMode().writes(0)
4677  .mapsTo(MISCREG_ID_DFR0);
4678  InitReg(MISCREG_ID_AFR0_EL1)
4679  .allPrivileges().exceptUserMode().writes(0)
4680  .mapsTo(MISCREG_ID_AFR0);
4681  InitReg(MISCREG_ID_MMFR0_EL1)
4682  .allPrivileges().exceptUserMode().writes(0)
4683  .mapsTo(MISCREG_ID_MMFR0);
4684  InitReg(MISCREG_ID_MMFR1_EL1)
4685  .allPrivileges().exceptUserMode().writes(0)
4686  .mapsTo(MISCREG_ID_MMFR1);
4687  InitReg(MISCREG_ID_MMFR2_EL1)
4688  .allPrivileges().exceptUserMode().writes(0)
4689  .mapsTo(MISCREG_ID_MMFR2);
4690  InitReg(MISCREG_ID_MMFR3_EL1)
4691  .allPrivileges().exceptUserMode().writes(0)
4692  .mapsTo(MISCREG_ID_MMFR3);
4693  InitReg(MISCREG_ID_ISAR0_EL1)
4694  .allPrivileges().exceptUserMode().writes(0)
4695  .mapsTo(MISCREG_ID_ISAR0);
4696  InitReg(MISCREG_ID_ISAR1_EL1)
4697  .allPrivileges().exceptUserMode().writes(0)
4698  .mapsTo(MISCREG_ID_ISAR1);
4699  InitReg(MISCREG_ID_ISAR2_EL1)
4700  .allPrivileges().exceptUserMode().writes(0)
4701  .mapsTo(MISCREG_ID_ISAR2);
4702  InitReg(MISCREG_ID_ISAR3_EL1)
4703  .allPrivileges().exceptUserMode().writes(0)
4704  .mapsTo(MISCREG_ID_ISAR3);
4705  InitReg(MISCREG_ID_ISAR4_EL1)
4706  .allPrivileges().exceptUserMode().writes(0)
4707  .mapsTo(MISCREG_ID_ISAR4);
4708  InitReg(MISCREG_ID_ISAR5_EL1)
4709  .allPrivileges().exceptUserMode().writes(0)
4710  .mapsTo(MISCREG_ID_ISAR5);
4711  InitReg(MISCREG_MVFR0_EL1)
4712  .allPrivileges().exceptUserMode().writes(0);
4713  InitReg(MISCREG_MVFR1_EL1)
4714  .allPrivileges().exceptUserMode().writes(0);
4715  InitReg(MISCREG_MVFR2_EL1)
4716  .allPrivileges().exceptUserMode().writes(0);
4717  InitReg(MISCREG_ID_AA64PFR0_EL1)
4718  .allPrivileges().exceptUserMode().writes(0);
4719  InitReg(MISCREG_ID_AA64PFR1_EL1)
4720  .allPrivileges().exceptUserMode().writes(0);
4721  InitReg(MISCREG_ID_AA64DFR0_EL1)
4722  .allPrivileges().exceptUserMode().writes(0);
4723  InitReg(MISCREG_ID_AA64DFR1_EL1)
4724  .allPrivileges().exceptUserMode().writes(0);
4725  InitReg(MISCREG_ID_AA64AFR0_EL1)
4726  .allPrivileges().exceptUserMode().writes(0);
4727  InitReg(MISCREG_ID_AA64AFR1_EL1)
4728  .allPrivileges().exceptUserMode().writes(0);
4729  InitReg(MISCREG_ID_AA64ISAR0_EL1)
4730  .allPrivileges().exceptUserMode().writes(0);
4731  InitReg(MISCREG_ID_AA64ISAR1_EL1)
4732  .allPrivileges().exceptUserMode().writes(0);
4733  InitReg(MISCREG_ID_AA64MMFR0_EL1)
4734  .allPrivileges().exceptUserMode().writes(0);
4735  InitReg(MISCREG_ID_AA64MMFR1_EL1)
4736  .allPrivileges().exceptUserMode().writes(0);
4737  InitReg(MISCREG_ID_AA64MMFR2_EL1)
4738  .allPrivileges().exceptUserMode().writes(0);
4739 
4740  InitReg(MISCREG_APDAKeyHi_EL1)
4741  .allPrivileges().exceptUserMode();
4742  InitReg(MISCREG_APDAKeyLo_EL1)
4743  .allPrivileges().exceptUserMode();
4744  InitReg(MISCREG_APDBKeyHi_EL1)
4745  .allPrivileges().exceptUserMode();
4746  InitReg(MISCREG_APDBKeyLo_EL1)
4747  .allPrivileges().exceptUserMode();
4748  InitReg(MISCREG_APGAKeyHi_EL1)
4749  .allPrivileges().exceptUserMode();
4750  InitReg(MISCREG_APGAKeyLo_EL1)
4751  .allPrivileges().exceptUserMode();
4752  InitReg(MISCREG_APIAKeyHi_EL1)
4753  .allPrivileges().exceptUserMode();
4754  InitReg(MISCREG_APIAKeyLo_EL1)
4755  .allPrivileges().exceptUserMode();
4756  InitReg(MISCREG_APIBKeyHi_EL1)
4757  .allPrivileges().exceptUserMode();
4758  InitReg(MISCREG_APIBKeyLo_EL1)
4759  .allPrivileges().exceptUserMode();
4760 
4761  InitReg(MISCREG_CCSIDR_EL1)
4762  .allPrivileges().exceptUserMode().writes(0);
4763  InitReg(MISCREG_CLIDR_EL1)
4764  .allPrivileges().exceptUserMode().writes(0);
4765  InitReg(MISCREG_AIDR_EL1)
4766  .allPrivileges().exceptUserMode().writes(0);
4767  InitReg(MISCREG_CSSELR_EL1)
4768  .allPrivileges().exceptUserMode()
4769  .mapsTo(MISCREG_CSSELR_NS);
4770  InitReg(MISCREG_CTR_EL0)
4771  .reads(1);
4772  InitReg(MISCREG_DCZID_EL0)
4773  .reads(1);
4774  InitReg(MISCREG_VPIDR_EL2)
4775  .hyp().mon()
4776  .mapsTo(MISCREG_VPIDR);
4777  InitReg(MISCREG_VMPIDR_EL2)
4778  .hyp().mon()
4779  .mapsTo(MISCREG_VMPIDR);
4780  InitReg(MISCREG_SCTLR_EL1)
4781  .allPrivileges().exceptUserMode()
4782  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4783  | (IESB ? 0 : 0x200000)
4784  | (EnDA ? 0 : 0x8000000)
4785  | (EnIB ? 0 : 0x40000000)
4786  | (EnIA ? 0 : 0x80000000))
4787  .res1(0x500800 | (SPAN ? 0 : 0x800000)
4788  | (nTLSMD ? 0 : 0x8000000)
4789  | (LSMAOE ? 0 : 0x10000000))
4790  .mapsTo(MISCREG_SCTLR_NS);
4791  InitReg(MISCREG_SCTLR_EL12)
4792  .allPrivileges().exceptUserMode()
4793  .res0( 0x20440 | (EnDB ? 0 : 0x2000)
4794  | (IESB ? 0 : 0x200000)
4795  | (EnDA ? 0 : 0x8000000)
4796  | (EnIB ? 0 : 0x40000000)
4797  | (EnIA ? 0 : 0x80000000))
4798  .res1(0x500800 | (SPAN ? 0 : 0x800000)
4799  | (nTLSMD ? 0 : 0x8000000)
4800  | (LSMAOE ? 0 : 0x10000000))
4801  .mapsTo(MISCREG_SCTLR_EL1);
4802  InitReg(MISCREG_ACTLR_EL1)
4803  .allPrivileges().exceptUserMode()
4804  .mapsTo(MISCREG_ACTLR_NS);
4805  InitReg(MISCREG_CPACR_EL1)
4806  .allPrivileges().exceptUserMode()
4807  .mapsTo(MISCREG_CPACR);
4808  InitReg(MISCREG_CPACR_EL12)
4809  .allPrivileges().exceptUserMode()
4810  .mapsTo(MISCREG_CPACR_EL1);
4811  InitReg(MISCREG_SCTLR_EL2)
4812  .hyp().mon()
4813  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4814  | (IESB ? 0 : 0x200000)
4815  | (EnDA ? 0 : 0x8000000)
4816  | (EnIB ? 0 : 0x40000000)
4817  | (EnIA ? 0 : 0x80000000))
4818  .res1(0x30c50830)
4819  .mapsTo(MISCREG_HSCTLR);
4820  InitReg(MISCREG_ACTLR_EL2)
4821  .hyp().mon()
4822  .mapsTo(MISCREG_HACTLR);
4823  InitReg(MISCREG_HCR_EL2)
4824  .hyp().mon()
4825  .mapsTo(MISCREG_HCR, MISCREG_HCR2);
4826  InitReg(MISCREG_MDCR_EL2)
4827  .hyp().mon()
4828  .mapsTo(MISCREG_HDCR);
4829  InitReg(MISCREG_CPTR_EL2)
4830  .hyp().mon()
4831  .mapsTo(MISCREG_HCPTR);
4832  InitReg(MISCREG_HSTR_EL2)
4833  .hyp().mon()
4834  .mapsTo(MISCREG_HSTR);
4835  InitReg(MISCREG_HACR_EL2)
4836  .hyp().mon()
4837  .mapsTo(MISCREG_HACR);
4838  InitReg(MISCREG_SCTLR_EL3)
4839  .mon()
4840  .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
4841  | (IESB ? 0 : 0x200000)
4842  | (EnDA ? 0 : 0x8000000)
4843  | (EnIB ? 0 : 0x40000000)
4844  | (EnIA ? 0 : 0x80000000))
4845  .res1(0x30c50830);
4846  InitReg(MISCREG_ACTLR_EL3)
4847  .mon();
4848  InitReg(MISCREG_SCR_EL3)
4849  .mon()
4850  .mapsTo(MISCREG_SCR); // NAM D7-2005
4851  InitReg(MISCREG_SDER32_EL3)
4852  .mon()
4853  .mapsTo(MISCREG_SDER);
4854  InitReg(MISCREG_CPTR_EL3)
4855  .mon();
4856  InitReg(MISCREG_MDCR_EL3)
4857  .mon()
4858  .mapsTo(MISCREG_SDCR);
4859  InitReg(MISCREG_TTBR0_EL1)
4860  .allPrivileges().exceptUserMode()
4861  .mapsTo(MISCREG_TTBR0_NS);
4862  InitReg(MISCREG_TTBR0_EL12)
4863  .allPrivileges().exceptUserMode()
4864  .mapsTo(MISCREG_TTBR0_EL1);
4865  InitReg(MISCREG_TTBR1_EL1)
4866  .allPrivileges().exceptUserMode()
4867  .mapsTo(MISCREG_TTBR1_NS);
4868  InitReg(MISCREG_TTBR1_EL12)
4869  .allPrivileges().exceptUserMode()
4870  .mapsTo(MISCREG_TTBR1_EL1);
4871  InitReg(MISCREG_TCR_EL1)
4872  .allPrivileges().exceptUserMode()
4873  .mapsTo(MISCREG_TTBCR_NS);
4874  InitReg(MISCREG_TCR_EL12)
4875  .allPrivileges().exceptUserMode()
4876  .mapsTo(MISCREG_TTBCR_NS);
4877  InitReg(MISCREG_TTBR0_EL2)
4878  .hyp().mon()
4879  .mapsTo(MISCREG_HTTBR);
4880  InitReg(MISCREG_TTBR1_EL2)
4881  .hyp().mon();
4882  InitReg(MISCREG_TCR_EL2)
4883  .hyp().mon()
4884  .mapsTo(MISCREG_HTCR);
4885  InitReg(MISCREG_VTTBR_EL2)
4886  .hyp().mon()
4887  .mapsTo(MISCREG_VTTBR);
4888  InitReg(MISCREG_VTCR_EL2)
4889  .hyp().mon()
4890  .mapsTo(MISCREG_VTCR);
4891  InitReg(MISCREG_VSTTBR_EL2)
4892  .hyp().mon();
4893  InitReg(MISCREG_VSTCR_EL2)
4894  .hyp().mon();
4895  InitReg(MISCREG_TTBR0_EL3)
4896  .mon();
4897  InitReg(MISCREG_TCR_EL3)
4898  .mon();
4899  InitReg(MISCREG_DACR32_EL2)
4900  .hyp().mon()
4901  .mapsTo(MISCREG_DACR_NS);
4902  InitReg(MISCREG_SPSR_EL1)
4903  .allPrivileges().exceptUserMode()
4904  .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
4905  InitReg(MISCREG_SPSR_EL12)
4906  .allPrivileges().exceptUserMode()
4907  .mapsTo(MISCREG_SPSR_SVC);
4908  InitReg(MISCREG_ELR_EL1)
4909  .allPrivileges().exceptUserMode();
4910  InitReg(MISCREG_ELR_EL12)
4911  .allPrivileges().exceptUserMode()
4912  .mapsTo(MISCREG_ELR_EL1);
4913  InitReg(MISCREG_SP_EL0)
4914  .allPrivileges().exceptUserMode();
4915  InitReg(MISCREG_SPSEL)
4916  .allPrivileges().exceptUserMode();
4917  InitReg(MISCREG_CURRENTEL)
4918  .allPrivileges().exceptUserMode().writes(0);
4919  InitReg(MISCREG_PAN)
4920  .allPrivileges().exceptUserMode()
4921  .implemented(havePAN);
4922  InitReg(MISCREG_NZCV)
4923  .allPrivileges();
4924  InitReg(MISCREG_DAIF)
4925  .allPrivileges();
4926  InitReg(MISCREG_FPCR)
4927  .allPrivileges();
4928  InitReg(MISCREG_FPSR)
4929  .allPrivileges();
4930  InitReg(MISCREG_DSPSR_EL0)
4931  .allPrivileges();
4932  InitReg(MISCREG_DLR_EL0)
4933  .allPrivileges();
4934  InitReg(MISCREG_SPSR_EL2)
4935  .hyp().mon()
4936  .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
4937  InitReg(MISCREG_ELR_EL2)
4938  .hyp().mon();
4939  InitReg(MISCREG_SP_EL1)
4940  .hyp().mon();
4941  InitReg(MISCREG_SPSR_IRQ_AA64)
4942  .hyp().mon();
4943  InitReg(MISCREG_SPSR_ABT_AA64)
4944  .hyp().mon();
4945  InitReg(MISCREG_SPSR_UND_AA64)
4946  .hyp().mon();
4947  InitReg(MISCREG_SPSR_FIQ_AA64)
4948  .hyp().mon();
4949  InitReg(MISCREG_SPSR_EL3)
4950  .mon()
4951  .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
4952  InitReg(MISCREG_ELR_EL3)
4953  .mon();
4954  InitReg(MISCREG_SP_EL2)
4955  .mon();
4956  InitReg(MISCREG_AFSR0_EL1)
4957  .allPrivileges().exceptUserMode()
4958  .mapsTo(MISCREG_ADFSR_NS);
4959  InitReg(MISCREG_AFSR0_EL12)
4960  .allPrivileges().exceptUserMode()
4961  .mapsTo(MISCREG_ADFSR_NS);
4962  InitReg(MISCREG_AFSR1_EL1)
4963  .allPrivileges().exceptUserMode()
4964  .mapsTo(MISCREG_AIFSR_NS);
4965  InitReg(MISCREG_AFSR1_EL12)
4966  .allPrivileges().exceptUserMode()
4967  .mapsTo(MISCREG_AIFSR_NS);
4968  InitReg(MISCREG_ESR_EL1)
4969  .allPrivileges().exceptUserMode();
4970  InitReg(MISCREG_ESR_EL12)
4971  .allPrivileges().exceptUserMode()
4972  .mapsTo(MISCREG_ESR_EL1);
4973  InitReg(MISCREG_IFSR32_EL2)
4974  .hyp().mon()
4975  .mapsTo(MISCREG_IFSR_NS);
4976  InitReg(MISCREG_AFSR0_EL2)
4977  .hyp().mon()
4978  .mapsTo(MISCREG_HADFSR);
4979  InitReg(MISCREG_AFSR1_EL2)
4980  .hyp().mon()
4981  .mapsTo(MISCREG_HAIFSR);
4982  InitReg(MISCREG_ESR_EL2)
4983  .hyp().mon()
4984  .mapsTo(MISCREG_HSR);
4985  InitReg(MISCREG_FPEXC32_EL2)
4986  .hyp().mon().mapsTo(MISCREG_FPEXC);
4987  InitReg(MISCREG_AFSR0_EL3)
4988  .mon();
4989  InitReg(MISCREG_AFSR1_EL3)
4990  .mon();
4991  InitReg(MISCREG_ESR_EL3)
4992  .mon();
4993  InitReg(MISCREG_FAR_EL1)
4994  .allPrivileges().exceptUserMode()
4995  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4996  InitReg(MISCREG_FAR_EL12)
4997  .allPrivileges().exceptUserMode()
4998  .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
4999  InitReg(MISCREG_FAR_EL2)
5000  .hyp().mon()
5001  .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
5002  InitReg(MISCREG_HPFAR_EL2)
5003  .hyp().mon()
5004  .mapsTo(MISCREG_HPFAR);
5005  InitReg(MISCREG_FAR_EL3)
5006  .mon();
5007  InitReg(MISCREG_IC_IALLUIS)
5008  .warnNotFail()
5009  .writes(1).exceptUserMode();
5010  InitReg(MISCREG_PAR_EL1)
5011  .allPrivileges().exceptUserMode()
5012  .mapsTo(MISCREG_PAR_NS);
5013  InitReg(MISCREG_IC_IALLU)
5014  .warnNotFail()
5015  .writes(1).exceptUserMode();
5016  InitReg(MISCREG_DC_IVAC_Xt)
5017  .warnNotFail()
5018  .writes(1).exceptUserMode();
5019  InitReg(MISCREG_DC_ISW_Xt)
5020  .warnNotFail()
5021  .writes(1).exceptUserMode();
5022  InitReg(MISCREG_AT_S1E1R_Xt)
5023  .writes(1).exceptUserMode();
5024  InitReg(MISCREG_AT_S1E1W_Xt)
5025  .writes(1).exceptUserMode();
5026  InitReg(MISCREG_AT_S1E0R_Xt)
5027  .writes(1).exceptUserMode();
5028  InitReg(MISCREG_AT_S1E0W_Xt)
5029  .writes(1).exceptUserMode();
5030  InitReg(MISCREG_DC_CSW_Xt)
5031  .warnNotFail()
5032  .writes(1).exceptUserMode();
5033  InitReg(MISCREG_DC_CISW_Xt)
5034  .warnNotFail()
5035  .writes(1).exceptUserMode();
5036  InitReg(MISCREG_DC_ZVA_Xt)
5037  .warnNotFail()
5038  .writes(1).userSecureWrite(0);
5039  InitReg(MISCREG_IC_IVAU_Xt)
5040  .writes(1);
5041  InitReg(MISCREG_DC_CVAC_Xt)
5042  .warnNotFail()
5043  .writes(1);
5044  InitReg(MISCREG_DC_CVAU_Xt)
5045  .warnNotFail()
5046  .writes(1);
5047  InitReg(MISCREG_DC_CIVAC_Xt)
5048  .warnNotFail()
5049  .writes(1);
5050  InitReg(MISCREG_AT_S1E2R_Xt)
5051  .monNonSecureWrite().hypWrite();
5052  InitReg(MISCREG_AT_S1E2W_Xt)
5053  .monNonSecureWrite().hypWrite();
5054  InitReg(MISCREG_AT_S12E1R_Xt)
5055  .hypWrite().monSecureWrite().monNonSecureWrite();
5056  InitReg(MISCREG_AT_S12E1W_Xt)
5057  .hypWrite().monSecureWrite().monNonSecureWrite();
5058  InitReg(MISCREG_AT_S12E0R_Xt)
5059  .hypWrite().monSecureWrite().monNonSecureWrite();
5060  InitReg(MISCREG_AT_S12E0W_Xt)
5061  .hypWrite().monSecureWrite().monNonSecureWrite();
5062  InitReg(MISCREG_AT_S1E3R_Xt)
5063  .monSecureWrite().monNonSecureWrite();
5064  InitReg(MISCREG_AT_S1E3W_Xt)
5065  .monSecureWrite().monNonSecureWrite();
5066  InitReg(MISCREG_TLBI_VMALLE1IS)
5067  .writes(1).exceptUserMode();
5068  InitReg(MISCREG_TLBI_VAE1IS_Xt)
5069  .writes(1).exceptUserMode();
5070  InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
5071  .writes(1).exceptUserMode();
5072  InitReg(MISCREG_TLBI_VAAE1IS_Xt)
5073  .writes(1).exceptUserMode();
5074  InitReg(MISCREG_TLBI_VALE1IS_Xt)
5075  .writes(1).exceptUserMode();
5076  InitReg(MISCREG_TLBI_VAALE1IS_Xt)
5077  .writes(1).exceptUserMode();
5078  InitReg(MISCREG_TLBI_VMALLE1)
5079  .writes(1).exceptUserMode();
5080  InitReg(MISCREG_TLBI_VAE1_Xt)
5081  .writes(1).exceptUserMode();
5082  InitReg(MISCREG_TLBI_ASIDE1_Xt)
5083  .writes(1).exceptUserMode();
5084  InitReg(MISCREG_TLBI_VAAE1_Xt)
5085  .writes(1).exceptUserMode();
5086  InitReg(MISCREG_TLBI_VALE1_Xt)
5087  .writes(1).exceptUserMode();
5088  InitReg(MISCREG_TLBI_VAALE1_Xt)
5089  .writes(1).exceptUserMode();
5090  InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
5091  .hypWrite().monSecureWrite().monNonSecureWrite();
5092  InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
5093  .hypWrite().monSecureWrite().monNonSecureWrite();
5094  InitReg(MISCREG_TLBI_ALLE2IS)
5095  .monNonSecureWrite().hypWrite();
5096  InitReg(MISCREG_TLBI_VAE2IS_Xt)
5097  .monNonSecureWrite().hypWrite();
5098  InitReg(MISCREG_TLBI_ALLE1IS)
5099  .hypWrite().monSecureWrite().monNonSecureWrite();
5100  InitReg(MISCREG_TLBI_VALE2IS_Xt)
5101  .monNonSecureWrite().hypWrite();
5102  InitReg(MISCREG_TLBI_VMALLS12E1IS)
5103  .hypWrite().monSecureWrite().monNonSecureWrite();
5104  InitReg(MISCREG_TLBI_IPAS2E1_Xt)
5105  .hypWrite().monSecureWrite().monNonSecureWrite();
5106  InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
5107  .hypWrite().monSecureWrite().monNonSecureWrite();
5108  InitReg(MISCREG_TLBI_ALLE2)
5109  .monNonSecureWrite().hypWrite();
5110  InitReg(MISCREG_TLBI_VAE2_Xt)
5111  .monNonSecureWrite().hypWrite();
5112  InitReg(MISCREG_TLBI_ALLE1)
5113  .hypWrite().monSecureWrite().monNonSecureWrite();
5114  InitReg(MISCREG_TLBI_VALE2_Xt)
5115  .monNonSecureWrite().hypWrite();
5116  InitReg(MISCREG_TLBI_VMALLS12E1)
5117  .hypWrite().monSecureWrite().monNonSecureWrite();
5118  InitReg(MISCREG_TLBI_ALLE3IS)
5119  .monSecureWrite().monNonSecureWrite();
5120  InitReg(MISCREG_TLBI_VAE3IS_Xt)
5121  .monSecureWrite().monNonSecureWrite();
5122  InitReg(MISCREG_TLBI_VALE3IS_Xt)
5123  .monSecureWrite().monNonSecureWrite();
5124  InitReg(MISCREG_TLBI_ALLE3)
5125  .monSecureWrite().monNonSecureWrite();
5126  InitReg(MISCREG_TLBI_VAE3_Xt)
5127  .monSecureWrite().monNonSecureWrite();
5128  InitReg(MISCREG_TLBI_VALE3_Xt)
5129  .monSecureWrite().monNonSecureWrite();
5130  InitReg(MISCREG_PMINTENSET_EL1)
5131  .allPrivileges().exceptUserMode()
5132  .mapsTo(MISCREG_PMINTENSET);
5133  InitReg(MISCREG_PMINTENCLR_EL1)
5134  .allPrivileges().exceptUserMode()
5135  .mapsTo(MISCREG_PMINTENCLR);
5136  InitReg(MISCREG_PMCR_EL0)
5137  .allPrivileges()
5138  .mapsTo(MISCREG_PMCR);
5139  InitReg(MISCREG_PMCNTENSET_EL0)
5140  .allPrivileges()
5141  .mapsTo(MISCREG_PMCNTENSET);
5142  InitReg(MISCREG_PMCNTENCLR_EL0)
5143  .allPrivileges()
5144  .mapsTo(MISCREG_PMCNTENCLR);
5145  InitReg(MISCREG_PMOVSCLR_EL0)
5146  .allPrivileges();
5147 // .mapsTo(MISCREG_PMOVSCLR);
5148  InitReg(MISCREG_PMSWINC_EL0)
5149  .writes(1).user()
5150  .mapsTo(MISCREG_PMSWINC);
5151  InitReg(MISCREG_PMSELR_EL0)
5152  .allPrivileges()
5153  .mapsTo(MISCREG_PMSELR);
5154  InitReg(MISCREG_PMCEID0_EL0)
5155  .reads(1).user()
5156  .mapsTo(MISCREG_PMCEID0);
5157  InitReg(MISCREG_PMCEID1_EL0)
5158  .reads(1).user()
5159  .mapsTo(MISCREG_PMCEID1);
5160  InitReg(MISCREG_PMCCNTR_EL0)
5161  .allPrivileges()
5162  .mapsTo(MISCREG_PMCCNTR);
5163  InitReg(MISCREG_PMXEVTYPER_EL0)
5164  .allPrivileges()
5165  .mapsTo(MISCREG_PMXEVTYPER);
5166  InitReg(MISCREG_PMCCFILTR_EL0)
5167  .allPrivileges();
5168  InitReg(MISCREG_PMXEVCNTR_EL0)
5169  .allPrivileges()
5170  .mapsTo(MISCREG_PMXEVCNTR);
5171  InitReg(MISCREG_PMUSERENR_EL0)
5172  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5173  .mapsTo(MISCREG_PMUSERENR);
5174  InitReg(MISCREG_PMOVSSET_EL0)
5175  .allPrivileges()
5176  .mapsTo(MISCREG_PMOVSSET);
5177  InitReg(MISCREG_MAIR_EL1)
5178  .allPrivileges().exceptUserMode()
5179  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5180  InitReg(MISCREG_MAIR_EL12)
5181  .allPrivileges().exceptUserMode()
5182  .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5183  InitReg(MISCREG_AMAIR_EL1)
5184  .allPrivileges().exceptUserMode()
5185  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5186  InitReg(MISCREG_AMAIR_EL12)
5187  .allPrivileges().exceptUserMode()
5188  .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5189  InitReg(MISCREG_MAIR_EL2)
5190  .hyp().mon()
5191  .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
5192  InitReg(MISCREG_AMAIR_EL2)
5193  .hyp().mon()
5194  .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
5195  InitReg(MISCREG_MAIR_EL3)
5196  .mon();
5197  InitReg(MISCREG_AMAIR_EL3)
5198  .mon();
5199  InitReg(MISCREG_L2CTLR_EL1)
5200  .allPrivileges().exceptUserMode();
5201  InitReg(MISCREG_L2ECTLR_EL1)
5202  .allPrivileges().exceptUserMode();
5203  InitReg(MISCREG_VBAR_EL1)
5204  .allPrivileges().exceptUserMode()
5205  .mapsTo(MISCREG_VBAR_NS);
5206  InitReg(MISCREG_VBAR_EL12)
5207  .allPrivileges().exceptUserMode()
5208  .mapsTo(MISCREG_VBAR_NS);
5209  InitReg(MISCREG_RVBAR_EL1)
5210  .allPrivileges().exceptUserMode().writes(0);
5211  InitReg(MISCREG_ISR_EL1)
5212  .allPrivileges().exceptUserMode().writes(0);
5213  InitReg(MISCREG_VBAR_EL2)
5214  .hyp().mon()
5215  .res0(0x7ff)
5216  .mapsTo(MISCREG_HVBAR);
5217  InitReg(MISCREG_RVBAR_EL2)
5218  .mon().hyp().writes(0);
5219  InitReg(MISCREG_VBAR_EL3)
5220  .mon();
5221  InitReg(MISCREG_RVBAR_EL3)
5222  .mon().writes(0);
5223  InitReg(MISCREG_RMR_EL3)
5224  .mon();
5225  InitReg(MISCREG_CONTEXTIDR_EL1)
5226  .allPrivileges().exceptUserMode()
5227  .mapsTo(MISCREG_CONTEXTIDR_NS);
5228  InitReg(MISCREG_CONTEXTIDR_EL12)
5229  .allPrivileges().exceptUserMode()
5230  .mapsTo(MISCREG_CONTEXTIDR_NS);
5231  InitReg(MISCREG_TPIDR_EL1)
5232  .allPrivileges().exceptUserMode()
5233  .mapsTo(MISCREG_TPIDRPRW_NS);
5234  InitReg(MISCREG_TPIDR_EL0)
5235  .allPrivileges()
5236  .mapsTo(MISCREG_TPIDRURW_NS);
5237  InitReg(MISCREG_TPIDRRO_EL0)
5238  .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5239  .mapsTo(MISCREG_TPIDRURO_NS);
5240  InitReg(MISCREG_TPIDR_EL2)
5241  .hyp().mon()
5242  .mapsTo(MISCREG_HTPIDR);
5243  InitReg(MISCREG_TPIDR_EL3)
5244  .mon();
5245  // BEGIN Generic Timer (AArch64)
5246  InitReg(MISCREG_CNTFRQ_EL0)
5247  .reads(1)
5248  .highest(system)
5249  .privSecureWrite(aarch32EL3)
5250  .mapsTo(MISCREG_CNTFRQ);
5251  InitReg(MISCREG_CNTPCT_EL0)
5252  .unverifiable()
5253  .reads(1)
5254  .mapsTo(MISCREG_CNTPCT);
5255  InitReg(MISCREG_CNTVCT_EL0)
5256  .unverifiable()
5257  .reads(1)
5258  .mapsTo(MISCREG_CNTVCT);
5259  InitReg(MISCREG_CNTP_CTL_EL0)
5260  .allPrivileges()
5261  .res0(0xfffffffffffffff8)
5262  .mapsTo(MISCREG_CNTP_CTL_NS);
5263  InitReg(MISCREG_CNTP_CVAL_EL0)
5264  .allPrivileges()
5265  .mapsTo(MISCREG_CNTP_CVAL_NS);
5266  InitReg(MISCREG_CNTP_TVAL_EL0)
5267  .allPrivileges()
5268  .res0(0xffffffff00000000)
5269  .mapsTo(MISCREG_CNTP_TVAL_NS);
5270  InitReg(MISCREG_CNTV_CTL_EL0)
5271  .allPrivileges()
5272  .res0(0xfffffffffffffff8)
5273  .mapsTo(MISCREG_CNTV_CTL);
5274  InitReg(MISCREG_CNTV_CVAL_EL0)
5275  .allPrivileges()
5276  .mapsTo(MISCREG_CNTV_CVAL);
5277  InitReg(MISCREG_CNTV_TVAL_EL0)
5278  .allPrivileges()
5279  .res0(0xffffffff00000000)
5280  .mapsTo(MISCREG_CNTV_TVAL);
5281  InitReg(MISCREG_CNTP_CTL_EL02)
5282  .monE2H()
5283  .hypE2H()
5284  .res0(0xfffffffffffffff8)
5285  .mapsTo(MISCREG_CNTP_CTL_NS);
5286  InitReg(MISCREG_CNTP_CVAL_EL02)
5287  .monE2H()
5288  .hypE2H()
5289  .mapsTo(MISCREG_CNTP_CVAL_NS);
5290  InitReg(MISCREG_CNTP_TVAL_EL02)
5291  .monE2H()
5292  .hypE2H()
5293  .res0(0xffffffff00000000)
5294  .mapsTo(MISCREG_CNTP_TVAL_NS);
5295  InitReg(MISCREG_CNTV_CTL_EL02)
5296  .monE2H()
5297  .hypE2H()
5298  .res0(0xfffffffffffffff8)
5299  .mapsTo(MISCREG_CNTV_CTL);
5300  InitReg(MISCREG_CNTV_CVAL_EL02)
5301  .monE2H()
5302  .hypE2H()
5303  .mapsTo(MISCREG_CNTV_CVAL);
5304  InitReg(MISCREG_CNTV_TVAL_EL02)
5305  .monE2H()
5306  .hypE2H()
5307  .res0(0xffffffff00000000)
5308  .mapsTo(MISCREG_CNTV_TVAL);
5309  InitReg(MISCREG_CNTKCTL_EL1)
5310  .allPrivileges()
5311  .exceptUserMode()
5312  .res0(0xfffffffffffdfc00)
5313  .mapsTo(MISCREG_CNTKCTL);
5314  InitReg(MISCREG_CNTKCTL_EL12)
5315  .monE2H()
5316  .hypE2H()
5317  .res0(0xfffffffffffdfc00)
5318  .mapsTo(MISCREG_CNTKCTL);
5319  InitReg(MISCREG_CNTPS_CTL_EL1)
5320  .mon()
5321  .privSecure()
5322  .res0(0xfffffffffffffff8);
5323  InitReg(MISCREG_CNTPS_CVAL_EL1)
5324  .mon()
5325  .privSecure();
5326  InitReg(MISCREG_CNTPS_TVAL_EL1)
5327  .mon()
5328  .privSecure()
5329  .res0(0xffffffff00000000);
5330  InitReg(MISCREG_CNTHCTL_EL2)
5331  .mon()
5332  .hyp()
5333  .res0(0xfffffffffffc0000)
5334  .mapsTo(MISCREG_CNTHCTL);
5335  InitReg(MISCREG_CNTHP_CTL_EL2)
5336  .mon()
5337  .hyp()
5338  .res0(0xfffffffffffffff8)
5339  .mapsTo(MISCREG_CNTHP_CTL);
5340  InitReg(MISCREG_CNTHP_CVAL_EL2)
5341  .mon()
5342  .hyp()
5343  .mapsTo(MISCREG_CNTHP_CVAL);
5344  InitReg(MISCREG_CNTHP_TVAL_EL2)
5345  .mon()
5346  .hyp()
5347  .res0(0xffffffff00000000)
5348  .mapsTo(MISCREG_CNTHP_TVAL);
5349  InitReg(MISCREG_CNTHPS_CTL_EL2)
5350  .mon()
5351  .hyp()
5352  .res0(0xfffffffffffffff8)
5353  .unimplemented();
5354  InitReg(MISCREG_CNTHPS_CVAL_EL2)
5355  .mon()
5356  .hyp()
5357  .res0(0xfffffffffffffff8)
5358  .unimplemented();
5359  InitReg(MISCREG_CNTHPS_TVAL_EL2)
5360  .mon()
5361  .hyp()
5362  .res0(0xfffffffffffffff8)
5363  .unimplemented();
5364  InitReg(MISCREG_CNTHV_CTL_EL2)
5365  .mon()
5366  .hyp()
5367  .res0(0xfffffffffffffff8);
5368  InitReg(MISCREG_CNTHV_CVAL_EL2)
5369  .mon()
5370  .hyp();
5371  InitReg(MISCREG_CNTHV_TVAL_EL2)
5372  .mon()
5373  .hyp()
5374  .res0(0xffffffff00000000);
5375  InitReg(MISCREG_CNTHVS_CTL_EL2)
5376  .mon()
5377  .hyp()
5378  .res0(0xfffffffffffffff8)
5379  .unimplemented();
5380  InitReg(MISCREG_CNTHVS_CVAL_EL2)
5381  .mon()
5382  .hyp()
5383  .res0(0xfffffffffffffff8)
5384  .unimplemented();
5385  InitReg(MISCREG_CNTHVS_TVAL_EL2)
5386  .mon()
5387  .hyp()
5388  .res0(0xfffffffffffffff8)
5389  .unimplemented();
5390  // ENDIF Armv8.1-VHE
5391  InitReg(MISCREG_CNTVOFF_EL2)
5392  .mon()
5393  .hyp()
5394  .mapsTo(MISCREG_CNTVOFF);
5395  // END Generic Timer (AArch64)
5396  InitReg(MISCREG_PMEVCNTR0_EL0)
5397  .allPrivileges();
5398 // .mapsTo(MISCREG_PMEVCNTR0);
5399  InitReg(MISCREG_PMEVCNTR1_EL0)
5400  .allPrivileges();
5401 // .mapsTo(MISCREG_PMEVCNTR1);
5402  InitReg(MISCREG_PMEVCNTR2_EL0)
5403  .allPrivileges();
5404 // .mapsTo(MISCREG_PMEVCNTR2);
5405  InitReg(MISCREG_PMEVCNTR3_EL0)
5406  .allPrivileges();
5407 // .mapsTo(MISCREG_PMEVCNTR3);
5408  InitReg(MISCREG_PMEVCNTR4_EL0)
5409  .allPrivileges();
5410 // .mapsTo(MISCREG_PMEVCNTR4);
5411  InitReg(MISCREG_PMEVCNTR5_EL0)
5412  .allPrivileges();
5413 // .mapsTo(MISCREG_PMEVCNTR5);
5414  InitReg(MISCREG_PMEVTYPER0_EL0)
5415  .allPrivileges();
5416 // .mapsTo(MISCREG_PMEVTYPER0);
5417  InitReg(MISCREG_PMEVTYPER1_EL0)
5418  .allPrivileges();
5419 // .mapsTo(MISCREG_PMEVTYPER1);
5420  InitReg(MISCREG_PMEVTYPER2_EL0)
5421  .allPrivileges();
5422 // .mapsTo(MISCREG_PMEVTYPER2);
5423  InitReg(MISCREG_PMEVTYPER3_EL0)
5424  .allPrivileges();
5425 // .mapsTo(MISCREG_PMEVTYPER3);
5426  InitReg(MISCREG_PMEVTYPER4_EL0)
5427  .allPrivileges();
5428 // .mapsTo(MISCREG_PMEVTYPER4);
5429  InitReg(MISCREG_PMEVTYPER5_EL0)
5430  .allPrivileges();
5431 // .mapsTo(MISCREG_PMEVTYPER5);
5432  InitReg(MISCREG_IL1DATA0_EL1)
5433  .allPrivileges().exceptUserMode();
5434  InitReg(MISCREG_IL1DATA1_EL1)
5435  .allPrivileges().exceptUserMode();
5436  InitReg(MISCREG_IL1DATA2_EL1)
5437  .allPrivileges().exceptUserMode();
5438  InitReg(MISCREG_IL1DATA3_EL1)
5439  .allPrivileges().exceptUserMode();
5440  InitReg(MISCREG_DL1DATA0_EL1)
5441  .allPrivileges().exceptUserMode();
5442  InitReg(MISCREG_DL1DATA1_EL1)
5443  .allPrivileges().exceptUserMode();
5444  InitReg(MISCREG_DL1DATA2_EL1)
5445  .allPrivileges().exceptUserMode();
5446  InitReg(MISCREG_DL1DATA3_EL1)
5447  .allPrivileges().exceptUserMode();
5448  InitReg(MISCREG_DL1DATA4_EL1)
5449  .allPrivileges().exceptUserMode();
5450  InitReg(MISCREG_L2ACTLR_EL1)
5451  .allPrivileges().exceptUserMode();
5452  InitReg(MISCREG_CPUACTLR_EL1)
5453  .allPrivileges().exceptUserMode();
5454  InitReg(MISCREG_CPUECTLR_EL1)
5455  .allPrivileges().exceptUserMode();
5456  InitReg(MISCREG_CPUMERRSR_EL1)
5457  .allPrivileges().exceptUserMode();
5458  InitReg(MISCREG_L2MERRSR_EL1)
5459  .unimplemented()
5460  .warnNotFail()
5461  .allPrivileges().exceptUserMode();
5462  InitReg(MISCREG_CBAR_EL1)
5463  .allPrivileges().exceptUserMode().writes(0);
5464  InitReg(MISCREG_CONTEXTIDR_EL2)
5465  .mon().hyp();
5466 
5467  // GICv3 AArch64
5468  InitReg(MISCREG_ICC_PMR_EL1)
5469  .res0(0xffffff00) // [31:8]
5470  .allPrivileges().exceptUserMode()
5471  .mapsTo(MISCREG_ICC_PMR);
5472  InitReg(MISCREG_ICC_IAR0_EL1)
5473  .allPrivileges().exceptUserMode().writes(0)
5474  .mapsTo(MISCREG_ICC_IAR0);
5475  InitReg(MISCREG_ICC_EOIR0_EL1)
5476  .allPrivileges().exceptUserMode().reads(0)
5477  .mapsTo(MISCREG_ICC_EOIR0);
5478  InitReg(MISCREG_ICC_HPPIR0_EL1)
5479  .allPrivileges().exceptUserMode().writes(0)
5480  .mapsTo(MISCREG_ICC_HPPIR0);
5481  InitReg(MISCREG_ICC_BPR0_EL1)
5482  .res0(0xfffffff8) // [31:3]
5483  .allPrivileges().exceptUserMode()
5484  .mapsTo(MISCREG_ICC_BPR0);
5485  InitReg(MISCREG_ICC_AP0R0_EL1)
5486  .allPrivileges().exceptUserMode()
5487  .mapsTo(MISCREG_ICC_AP0R0);
5488  InitReg(MISCREG_ICC_AP0R1_EL1)
5489  .allPrivileges().exceptUserMode()
5490  .mapsTo(MISCREG_ICC_AP0R1);
5491  InitReg(MISCREG_ICC_AP0R2_EL1)
5492  .allPrivileges().exceptUserMode()
5493  .mapsTo(MISCREG_ICC_AP0R2);
5494  InitReg(MISCREG_ICC_AP0R3_EL1)
5495  .allPrivileges().exceptUserMode()
5496  .mapsTo(MISCREG_ICC_AP0R3);
5497  InitReg(MISCREG_ICC_AP1R0_EL1)
5498  .banked64()
5499  .mapsTo(MISCREG_ICC_AP1R0);
5500  InitReg(MISCREG_ICC_AP1R0_EL1_NS)
5501  .bankedChild()
5502  .allPrivileges().exceptUserMode()
5503  .mapsTo(MISCREG_ICC_AP1R0_NS);
5504  InitReg(MISCREG_ICC_AP1R0_EL1_S)
5505  .bankedChild()
5506  .allPrivileges().exceptUserMode()
5507  .mapsTo(MISCREG_ICC_AP1R0_S);
5508  InitReg(MISCREG_ICC_AP1R1_EL1)
5509  .banked64()
5510  .mapsTo(MISCREG_ICC_AP1R1);
5511  InitReg(MISCREG_ICC_AP1R1_EL1_NS)
5512  .bankedChild()
5513  .allPrivileges().exceptUserMode()
5514  .mapsTo(MISCREG_ICC_AP1R1_NS);
5515  InitReg(MISCREG_ICC_AP1R1_EL1_S)
5516  .bankedChild()
5517  .allPrivileges().exceptUserMode()
5518  .mapsTo(MISCREG_ICC_AP1R1_S);
5519  InitReg(MISCREG_ICC_AP1R2_EL1)
5520  .banked64()
5521  .mapsTo(MISCREG_ICC_AP1R2);
5522  InitReg(MISCREG_ICC_AP1R2_EL1_NS)
5523  .bankedChild()
5524  .allPrivileges().exceptUserMode()
5525  .mapsTo(MISCREG_ICC_AP1R2_NS);
5526  InitReg(MISCREG_ICC_AP1R2_EL1_S)
5527  .bankedChild()
5528  .allPrivileges().exceptUserMode()
5529  .mapsTo(MISCREG_ICC_AP1R2_S);
5530  InitReg(MISCREG_ICC_AP1R3_EL1)
5531  .banked64()
5532  .mapsTo(MISCREG_ICC_AP1R3);
5533  InitReg(MISCREG_ICC_AP1R3_EL1_NS)
5534  .bankedChild()
5535  .allPrivileges().exceptUserMode()
5536  .mapsTo(MISCREG_ICC_AP1R3_NS);
5537  InitReg(MISCREG_ICC_AP1R3_EL1_S)
5538  .bankedChild()
5539  .allPrivileges().exceptUserMode()
5540  .mapsTo(MISCREG_ICC_AP1R3_S);
5541  InitReg(MISCREG_ICC_DIR_EL1)
5542  .res0(0xFF000000) // [31:24]
5543  .allPrivileges().exceptUserMode().reads(0)
5544  .mapsTo(MISCREG_ICC_DIR);
5545  InitReg(MISCREG_ICC_RPR_EL1)
5546  .allPrivileges().exceptUserMode().writes(0)
5547  .mapsTo(MISCREG_ICC_RPR);
5548  InitReg(MISCREG_ICC_SGI1R_EL1)
5549  .allPrivileges().exceptUserMode().reads(0)
5550  .mapsTo(MISCREG_ICC_SGI1R);
5551  InitReg(MISCREG_ICC_ASGI1R_EL1)
5552  .allPrivileges().exceptUserMode().reads(0)
5553  .mapsTo(MISCREG_ICC_ASGI1R);
5554  InitReg(MISCREG_ICC_SGI0R_EL1)
5555  .allPrivileges().exceptUserMode().reads(0)
5556  .mapsTo(MISCREG_ICC_SGI0R);
5557  InitReg(MISCREG_ICC_IAR1_EL1)
5558  .allPrivileges().exceptUserMode().writes(0)
5559  .mapsTo(MISCREG_ICC_IAR1);
5560  InitReg(MISCREG_ICC_EOIR1_EL1)
5561  .res0(0xFF000000) // [31:24]
5562  .allPrivileges().exceptUserMode().reads(0)
5563  .mapsTo(MISCREG_ICC_EOIR1);
5564  InitReg(MISCREG_ICC_HPPIR1_EL1)
5565  .allPrivileges().exceptUserMode().writes(0)
5566  .mapsTo(MISCREG_ICC_HPPIR1);
5567  InitReg(MISCREG_ICC_BPR1_EL1)
5568  .banked64()
5569  .mapsTo(MISCREG_ICC_BPR1);
5570  InitReg(MISCREG_ICC_BPR1_EL1_NS)
5571  .bankedChild()
5572  .res0(0xfffffff8) // [31:3]
5573  .allPrivileges().exceptUserMode()
5574  .mapsTo(MISCREG_ICC_BPR1_NS);
5575  InitReg(MISCREG_ICC_BPR1_EL1_S)
5576  .bankedChild()
5577  .res0(0xfffffff8) // [31:3]
5578  .secure().exceptUserMode()
5579  .mapsTo(MISCREG_ICC_BPR1_S);
5580  InitReg(MISCREG_ICC_CTLR_EL1)
5581  .banked64()
5582  .mapsTo(MISCREG_ICC_CTLR);
5583  InitReg(MISCREG_ICC_CTLR_EL1_NS)
5584  .bankedChild()
5585  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5586  .allPrivileges().exceptUserMode()
5587  .mapsTo(MISCREG_ICC_CTLR_NS);
5588  InitReg(MISCREG_ICC_CTLR_EL1_S)
5589  .bankedChild()
5590  .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
5591  .secure().exceptUserMode()
5592  .mapsTo(MISCREG_ICC_CTLR_S);
5593  InitReg(MISCREG_ICC_SRE_EL1)
5594  .banked()
5595  .mapsTo(MISCREG_ICC_SRE);
5596  InitReg(MISCREG_ICC_SRE_EL1_NS)
5597  .bankedChild()
5598  .res0(0xFFFFFFF8) // [31:3]
5599  .allPrivileges().exceptUserMode()
5600  .mapsTo(MISCREG_ICC_SRE_NS);
5601  InitReg(MISCREG_ICC_SRE_EL1_S)
5602  .bankedChild()
5603  .res0(0xFFFFFFF8) // [31:3]
5604  .secure().exceptUserMode()
5605  .mapsTo(MISCREG_ICC_SRE_S);
5606  InitReg(MISCREG_ICC_IGRPEN0_EL1)
5607  .res0(0xFFFFFFFE) // [31:1]
5608  .allPrivileges().exceptUserMode()
5609  .mapsTo(MISCREG_ICC_IGRPEN0);
5610  InitReg(MISCREG_ICC_IGRPEN1_EL1)
5611  .banked64()
5612  .mapsTo(MISCREG_ICC_IGRPEN1);
5613  InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
5614  .bankedChild()
5615  .res0(0xFFFFFFFE) // [31:1]
5616  .allPrivileges().exceptUserMode()
5617  .mapsTo(MISCREG_ICC_IGRPEN1_NS);
5618  InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
5619  .bankedChild()
5620  .res0(0xFFFFFFFE) // [31:1]
5621  .secure().exceptUserMode()
5622  .mapsTo(MISCREG_ICC_IGRPEN1_S);
5623  InitReg(MISCREG_ICC_SRE_EL2)
5624  .hyp().mon()
5625  .mapsTo(MISCREG_ICC_HSRE);
5626  InitReg(MISCREG_ICC_CTLR_EL3)
5627  .allPrivileges().exceptUserMode()
5628  .mapsTo(MISCREG_ICC_MCTLR);
5629  InitReg(MISCREG_ICC_SRE_EL3)
5630  .allPrivileges().exceptUserMode()
5631  .mapsTo(MISCREG_ICC_MSRE);
5632  InitReg(MISCREG_ICC_IGRPEN1_EL3)
5633  .allPrivileges().exceptUserMode()
5634  .mapsTo(MISCREG_ICC_MGRPEN1);
5635 
5636  InitReg(MISCREG_ICH_AP0R0_EL2)
5637  .hyp().mon()
5638  .mapsTo(MISCREG_ICH_AP0R0);
5639  InitReg(MISCREG_ICH_AP0R1_EL2)
5640  .hyp().mon()
5641  .unimplemented()
5642  .mapsTo(MISCREG_ICH_AP0R1);
5643  InitReg(MISCREG_ICH_AP0R2_EL2)
5644  .hyp().mon()
5645  .unimplemented()
5646  .mapsTo(MISCREG_ICH_AP0R2);
5647  InitReg(MISCREG_ICH_AP0R3_EL2)
5648  .hyp().mon()
5649  .unimplemented()
5650  .mapsTo(MISCREG_ICH_AP0R3);
5651  InitReg(MISCREG_ICH_AP1R0_EL2)
5652  .hyp().mon()
5653  .mapsTo(MISCREG_ICH_AP1R0);
5654  InitReg(MISCREG_ICH_AP1R1_EL2)
5655  .hyp().mon()
5656  .unimplemented()
5657  .mapsTo(MISCREG_ICH_AP1R1);
5658  InitReg(MISCREG_ICH_AP1R2_EL2)
5659  .hyp().mon()
5660  .unimplemented()
5661  .mapsTo(MISCREG_ICH_AP1R2);
5662  InitReg(MISCREG_ICH_AP1R3_EL2)
5663  .hyp().mon()
5664  .unimplemented()
5665  .mapsTo(MISCREG_ICH_AP1R3);
5666  InitReg(MISCREG_ICH_HCR_EL2)
5667  .hyp().mon()
5668  .mapsTo(MISCREG_ICH_HCR);
5669  InitReg(MISCREG_ICH_VTR_EL2)
5670  .hyp().mon().writes(0)
5671  .mapsTo(MISCREG_ICH_VTR);
5672  InitReg(MISCREG_ICH_MISR_EL2)
5673  .hyp().mon().writes(0)
5674  .mapsTo(MISCREG_ICH_MISR);
5675  InitReg(MISCREG_ICH_EISR_EL2)
5676  .hyp().mon().writes(0)
5677  .mapsTo(MISCREG_ICH_EISR);
5678  InitReg(MISCREG_ICH_ELRSR_EL2)
5679  .hyp().mon().writes(0)
5680  .mapsTo(MISCREG_ICH_ELRSR);
5681  InitReg(MISCREG_ICH_VMCR_EL2)
5682  .hyp().mon()
5683  .mapsTo(MISCREG_ICH_VMCR);
5684  InitReg(MISCREG_ICH_LR0_EL2)
5685  .hyp().mon()
5686  .allPrivileges().exceptUserMode();
5687  InitReg(MISCREG_ICH_LR1_EL2)
5688  .hyp().mon()
5689  .allPrivileges().exceptUserMode();
5690  InitReg(MISCREG_ICH_LR2_EL2)
5691  .hyp().mon()
5692  .allPrivileges().exceptUserMode();
5693  InitReg(MISCREG_ICH_LR3_EL2)
5694  .hyp().mon()
5695  .allPrivileges().exceptUserMode();
5696  InitReg(MISCREG_ICH_LR4_EL2)
5697  .hyp().mon()
5698  .allPrivileges().exceptUserMode();
5699  InitReg(MISCREG_ICH_LR5_EL2)
5700  .hyp().mon()
5701  .allPrivileges().exceptUserMode();
5702  InitReg(MISCREG_ICH_LR6_EL2)
5703  .hyp().mon()
5704  .allPrivileges().exceptUserMode();
5705  InitReg(MISCREG_ICH_LR7_EL2)
5706  .hyp().mon()
5707  .allPrivileges().exceptUserMode();
5708  InitReg(MISCREG_ICH_LR8_EL2)
5709  .hyp().mon()
5710  .allPrivileges().exceptUserMode();
5711  InitReg(MISCREG_ICH_LR9_EL2)
5712  .hyp().mon()
5713  .allPrivileges().exceptUserMode();
5714  InitReg(MISCREG_ICH_LR10_EL2)
5715  .hyp().mon()
5716  .allPrivileges().exceptUserMode();
5717  InitReg(MISCREG_ICH_LR11_EL2)
5718  .hyp().mon()
5719  .allPrivileges().exceptUserMode();
5720  InitReg(MISCREG_ICH_LR12_EL2)
5721  .hyp().mon()
5722  .allPrivileges().exceptUserMode();
5723  InitReg(MISCREG_ICH_LR13_EL2)
5724  .hyp().mon()
5725  .allPrivileges().exceptUserMode();
5726  InitReg(MISCREG_ICH_LR14_EL2)
5727  .hyp().mon()
5728  .allPrivileges().exceptUserMode();
5729  InitReg(MISCREG_ICH_LR15_EL2)
5730  .hyp().mon()
5731  .allPrivileges().exceptUserMode();
5732 
5733  // GICv3 AArch32
5734  InitReg(MISCREG_ICC_AP0R0)
5735  .allPrivileges().exceptUserMode();
5736  InitReg(MISCREG_ICC_AP0R1)
5737  .allPrivileges().exceptUserMode();
5738  InitReg(MISCREG_ICC_AP0R2)
5739  .allPrivileges().exceptUserMode();
5740  InitReg(MISCREG_ICC_AP0R3)
5741  .allPrivileges().exceptUserMode();
5742  InitReg(MISCREG_ICC_AP1R0)
5743  .allPrivileges().exceptUserMode();
5744  InitReg(MISCREG_ICC_AP1R0_NS)
5745  .allPrivileges().exceptUserMode();
5746  InitReg(MISCREG_ICC_AP1R0_S)
5747  .allPrivileges().exceptUserMode();
5748  InitReg(MISCREG_ICC_AP1R1)
5749  .allPrivileges().exceptUserMode();
5750  InitReg(MISCREG_ICC_AP1R1_NS)
5751  .allPrivileges().exceptUserMode();
5752  InitReg(MISCREG_ICC_AP1R1_S)
5753  .allPrivileges().exceptUserMode();
5754  InitReg(MISCREG_ICC_AP1R2)
5755  .allPrivileges().exceptUserMode();
5756  InitReg(MISCREG_ICC_AP1R2_NS)
5757  .allPrivileges().exceptUserMode();
5758  InitReg(MISCREG_ICC_AP1R2_S)
5759  .allPrivileges().exceptUserMode();
5760  InitReg(MISCREG_ICC_AP1R3)
5761  .allPrivileges().exceptUserMode();
5762  InitReg(MISCREG_ICC_AP1R3_NS)
5763  .allPrivileges().exceptUserMode();
5764  InitReg(MISCREG_ICC_AP1R3_S)
5765  .allPrivileges().exceptUserMode();
5766  InitReg(MISCREG_ICC_ASGI1R)
5767  .allPrivileges().exceptUserMode().reads(0);
5768  InitReg(MISCREG_ICC_BPR0)
5769  .allPrivileges().exceptUserMode();
5770  InitReg(MISCREG_ICC_BPR1)
5771  .allPrivileges().exceptUserMode();
5772  InitReg(MISCREG_ICC_BPR1_NS)
5773  .allPrivileges().exceptUserMode();
5774  InitReg(MISCREG_ICC_BPR1_S)
5775  .allPrivileges().exceptUserMode();
5776  InitReg(MISCREG_ICC_CTLR)
5777  .allPrivileges().exceptUserMode();
5778  InitReg(MISCREG_ICC_CTLR_NS)
5779  .allPrivileges().exceptUserMode();
5780  InitReg(MISCREG_ICC_CTLR_S)
5781  .allPrivileges().exceptUserMode();
5782  InitReg(MISCREG_ICC_DIR)
5783  .allPrivileges().exceptUserMode().reads(0);
5784  InitReg(MISCREG_ICC_EOIR0)
5785  .allPrivileges().exceptUserMode().reads(0);
5786  InitReg(MISCREG_ICC_EOIR1)
5787  .allPrivileges().exceptUserMode().reads(0);
5788  InitReg(MISCREG_ICC_HPPIR0)
5789  .allPrivileges().exceptUserMode().writes(0);
5790  InitReg(MISCREG_ICC_HPPIR1)
5791  .allPrivileges().exceptUserMode().writes(0);
5792  InitReg(MISCREG_ICC_HSRE)
5793  .allPrivileges().exceptUserMode();
5794  InitReg(MISCREG_ICC_IAR0)
5795  .allPrivileges().exceptUserMode().writes(0);
5796  InitReg(MISCREG_ICC_IAR1)
5797  .allPrivileges().exceptUserMode().writes(0);
5798  InitReg(MISCREG_ICC_IGRPEN0)
5799  .allPrivileges().exceptUserMode();
5800  InitReg(MISCREG_ICC_IGRPEN1)
5801  .allPrivileges().exceptUserMode();
5802  InitReg(MISCREG_ICC_IGRPEN1_NS)
5803  .allPrivileges().exceptUserMode();
5804  InitReg(MISCREG_ICC_IGRPEN1_S)
5805  .allPrivileges().exceptUserMode();
5806  InitReg(MISCREG_ICC_MCTLR)
5807  .allPrivileges().exceptUserMode();
5808  InitReg(MISCREG_ICC_MGRPEN1)
5809  .allPrivileges().exceptUserMode();
5810  InitReg(MISCREG_ICC_MSRE)
5811  .allPrivileges().exceptUserMode();
5812  InitReg(MISCREG_ICC_PMR)
5813  .allPrivileges().exceptUserMode();
5814  InitReg(MISCREG_ICC_RPR)
5815  .allPrivileges().exceptUserMode().writes(0);
5816  InitReg(MISCREG_ICC_SGI0R)
5817  .allPrivileges().exceptUserMode().reads(0);
5818  InitReg(MISCREG_ICC_SGI1R)
5819  .allPrivileges().exceptUserMode().reads(0);
5820  InitReg(MISCREG_ICC_SRE)
5821  .allPrivileges().exceptUserMode();
5822  InitReg(MISCREG_ICC_SRE_NS)
5823  .allPrivileges().exceptUserMode();
5824  InitReg(MISCREG_ICC_SRE_S)
5825  .allPrivileges().exceptUserMode();
5826 
5827  InitReg(MISCREG_ICH_AP0R0)
5828  .hyp().mon();
5829  InitReg(MISCREG_ICH_AP0R1)
5830  .hyp().mon();
5831  InitReg(MISCREG_ICH_AP0R2)
5832  .hyp().mon();
5833  InitReg(MISCREG_ICH_AP0R3)
5834  .hyp().mon();
5835  InitReg(MISCREG_ICH_AP1R0)
5836  .hyp().mon();
5837  InitReg(MISCREG_ICH_AP1R1)
5838  .hyp().mon();
5839  InitReg(MISCREG_ICH_AP1R2)
5840  .hyp().mon();
5841  InitReg(MISCREG_ICH_AP1R3)
5842  .hyp().mon();
5843  InitReg(MISCREG_ICH_HCR)
5844  .hyp().mon();
5845  InitReg(MISCREG_ICH_VTR)
5846  .hyp().mon().writes(0);
5847  InitReg(MISCREG_ICH_MISR)
5848  .hyp().mon().writes(0);
5849  InitReg(MISCREG_ICH_EISR)
5850  .hyp().mon().writes(0);
5851  InitReg(MISCREG_ICH_ELRSR)
5852  .hyp().mon().writes(0);
5853  InitReg(MISCREG_ICH_VMCR)
5854  .hyp().mon();
5855  InitReg(MISCREG_ICH_LR0)
5856  .hyp().mon();
5857  InitReg(MISCREG_ICH_LR1)
5858  .hyp().mon();
5859  InitReg(MISCREG_ICH_LR2)
5860  .hyp().mon();
5861  InitReg(MISCREG_ICH_LR3)
5862  .hyp().mon();
5863  InitReg(MISCREG_ICH_LR4)
5864  .hyp().mon();
5865  InitReg(MISCREG_ICH_LR5)
5866  .hyp().mon();
5867  InitReg(MISCREG_ICH_LR6)
5868  .hyp().mon();
5869  InitReg(MISCREG_ICH_LR7)
5870  .hyp().mon();
5871  InitReg(MISCREG_ICH_LR8)
5872  .hyp().mon();
5873  InitReg(MISCREG_ICH_LR9)
5874  .hyp().mon();
5875  InitReg(MISCREG_ICH_LR10)
5876  .hyp().mon();
5877  InitReg(MISCREG_ICH_LR11)
5878  .hyp().mon();
5879  InitReg(MISCREG_ICH_LR12)
5880  .hyp().mon();
5881  InitReg(MISCREG_ICH_LR13)
5882  .hyp().mon();
5883  InitReg(MISCREG_ICH_LR14)
5884  .hyp().mon();
5885  InitReg(MISCREG_ICH_LR15)
5886  .hyp().mon();
5887  InitReg(MISCREG_ICH_LRC0)
5888  .mapsTo(MISCREG_ICH_LR0)
5889  .hyp().mon();
5890  InitReg(MISCREG_ICH_LRC1)
5891  .mapsTo(MISCREG_ICH_LR1)
5892  .hyp().mon();
5893  InitReg(MISCREG_ICH_LRC2)
5894  .mapsTo(MISCREG_ICH_LR2)
5895  .hyp().mon();
5896  InitReg(MISCREG_ICH_LRC3)
5897  .mapsTo(MISCREG_ICH_LR3)
5898  .hyp().mon();
5899  InitReg(MISCREG_ICH_LRC4)
5900  .mapsTo(MISCREG_ICH_LR4)
5901  .hyp().mon();
5902  InitReg(MISCREG_ICH_LRC5)
5903  .mapsTo(MISCREG_ICH_LR5)
5904  .hyp().mon();
5905  InitReg(MISCREG_ICH_LRC6)
5906  .mapsTo(MISCREG_ICH_LR6)
5907  .hyp().mon();
5908  InitReg(MISCREG_ICH_LRC7)
5909  .mapsTo(MISCREG_ICH_LR7)
5910  .hyp().mon();
5911  InitReg(MISCREG_ICH_LRC8)
5912  .mapsTo(MISCREG_ICH_LR8)
5913  .hyp().mon();
5914  InitReg(MISCREG_ICH_LRC9)
5915  .mapsTo(MISCREG_ICH_LR9)
5916  .hyp().mon();
5917  InitReg(MISCREG_ICH_LRC10)
5918  .mapsTo(MISCREG_ICH_LR10)
5919  .hyp().mon();
5920  InitReg(MISCREG_ICH_LRC11)
5921  .mapsTo(MISCREG_ICH_LR11)
5922  .hyp().mon();
5923  InitReg(MISCREG_ICH_LRC12)
5924  .mapsTo(MISCREG_ICH_LR12)
5925  .hyp().mon();
5926  InitReg(MISCREG_ICH_LRC13)
5927  .mapsTo(MISCREG_ICH_LR13)
5928  .hyp().mon();
5929  InitReg(MISCREG_ICH_LRC14)
5930  .mapsTo(MISCREG_ICH_LR14)
5931  .hyp().mon();
5932  InitReg(MISCREG_ICH_LRC15)
5933  .mapsTo(MISCREG_ICH_LR15)
5934  .hyp().mon();
5935 
5936  // SVE
5937  InitReg(MISCREG_ID_AA64ZFR0_EL1)
5938  .allPrivileges().exceptUserMode().writes(0);
5939  InitReg(MISCREG_ZCR_EL3)
5940  .mon();
5941  InitReg(MISCREG_ZCR_EL2)
5942  .hyp().mon();
5943  InitReg(MISCREG_ZCR_EL12)
5944  .allPrivileges().exceptUserMode()
5945  .mapsTo(MISCREG_ZCR_EL1);
5946  InitReg(MISCREG_ZCR_EL1)
5947  .allPrivileges().exceptUserMode();
5948 
5949  // Dummy registers
5950  InitReg(MISCREG_NOP)
5951  .allPrivileges();
5952  InitReg(MISCREG_RAZ)
5953  .allPrivileges().exceptUserMode().writes(0);
5954  InitReg(MISCREG_CP14_UNIMPL)
5955  .unimplemented()
5956  .warnNotFail();
5957  InitReg(MISCREG_CP15_UNIMPL)
5958  .unimplemented()
5959  .warnNotFail();
5960  InitReg(MISCREG_UNKNOWN);
5961  InitReg(MISCREG_IMPDEF_UNIMPL)
5962  .unimplemented()
5963  .warnNotFail(impdefAsNop);
5964 
5965  // RAS extension (unimplemented)
5966  InitReg(MISCREG_ERRIDR_EL1)
5967  .unimplemented()
5968  .warnNotFail();
5969  InitReg(MISCREG_ERRSELR_EL1)
5970  .unimplemented()
5971  .warnNotFail();
5972  InitReg(MISCREG_ERXFR_EL1)
5973  .unimplemented()
5974  .warnNotFail();
5975  InitReg(MISCREG_ERXCTLR_EL1)
5976  .unimplemented()
5977  .warnNotFail();
5978  InitReg(MISCREG_ERXSTATUS_EL1)
5979  .unimplemented()
5980  .warnNotFail();
5981  InitReg(MISCREG_ERXADDR_EL1)
5982  .unimplemented()
5983  .warnNotFail();
5984  InitReg(MISCREG_ERXMISC0_EL1)
5985  .unimplemented()
5986  .warnNotFail();
5987  InitReg(MISCREG_ERXMISC1_EL1)
5988  .unimplemented()
5989  .warnNotFail();
5990  InitReg(MISCREG_DISR_EL1)
5991  .unimplemented()
5992  .warnNotFail();
5993  InitReg(MISCREG_VSESR_EL2)
5994  .unimplemented()
5995  .warnNotFail();
5996  InitReg(MISCREG_VDISR_EL2)
5997  .unimplemented()
5998  .warnNotFail();
5999 
6000  // Register mappings for some unimplemented registers:
6001  // ESR_EL1 -> DFSR
6002  // RMR_EL1 -> RMR
6003  // RMR_EL2 -> HRMR
6004  // DBGDTR_EL0 -> DBGDTR{R or T}Xint
6005  // DBGDTRRX_EL0 -> DBGDTRRXint
6006  // DBGDTRTX_EL0 -> DBGDTRRXint
6007  // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
6008 
6009  completed = true;
6010 }
6011 
6012 } // namespace ArmISA
ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition: miscregs.hh:644
ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition: miscregs.hh:315
ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition: miscregs.hh:182
ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition: miscregs.hh:347
ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition: miscregs.hh:552
ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition: miscregs.hh:668
ArmISA::MISCREG_TPIDRURW
@ MISCREG_TPIDRURW
Definition: miscregs.hh:396
ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition: miscregs.hh:471
ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition: miscregs.hh:603
ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition: miscregs.hh:142
ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition: miscregs.hh:241
ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition: miscregs.hh:92
ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition: miscregs.hh:964
ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition: miscregs.hh:638
ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition: miscregs.hh:183
ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: miscregs.hh:814
ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition: miscregs.hh:807
ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition: miscregs.hh:134
ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition: miscregs.hh:143
ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition: miscregs.hh:630
ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition: miscregs.hh:826
ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition: miscregs.hh:716
ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition: miscregs.hh:973
ArmISA::MISCREG_ICH_LR2
@ MISCREG_ICH_LR2
Definition: miscregs.hh:1014
ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition: miscregs.hh:490
ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition: miscregs.hh:874
ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:369
ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: miscregs.hh:682
ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition: miscregs.hh:558
ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition: miscregs.hh:302
ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition: miscregs.hh:1081
ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition: miscregs.hh:353
ArmISA::MISCREG_ICC_AP1R3_S
@ MISCREG_ICC_AP1R3_S
Definition: miscregs.hh:966
ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition: miscregs.hh:661
ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition: miscregs.hh:792
ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition: miscregs.hh:669
ArmISA::MISCREG_ICC_AP1R3_NS
@ MISCREG_ICC_AP1R3_NS
Definition: miscregs.hh:965
ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition: miscregs.hh:127
ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition: miscregs.hh:387
ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition: miscregs.hh:308
ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition: miscregs.hh:620
ArmISA::ns
Bitfield< 0 > ns
Definition: miscregs_types.hh:328
ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition: miscregs.hh:313
ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition: miscregs.hh:178
ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition: miscregs.hh:461
ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:642
ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition: miscregs.hh:550
ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition: miscregs.hh:318
ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition: miscregs.hh:108
ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition: miscregs.hh:709
ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition: miscregs.hh:1022
ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition: miscregs.hh:470
ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition: miscregs.hh:771
ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition: miscregs.cc:3384
ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition: miscregs.hh:110
warn
#define warn(...)
Definition: logging.hh:239
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:560
ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition: miscregs.hh:758
ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition: miscregs.hh:775
ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition: miscregs.hh:766
ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition: miscregs.hh:504
ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition: miscregs.hh:865
ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition: miscregs.hh:454
ArmISA::EL2
@ EL2
Definition: types.hh:624
ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition: miscregs.hh:977
ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition: miscregs.hh:419
ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:643
ArmISA::MISCREG_MON_E2H_WR
@ MISCREG_MON_E2H_WR
Definition: miscregs.hh:1135
ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition: miscregs.hh:1048
ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition: miscregs.hh:628
ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition: miscregs.hh:507
ArmISA::MISCREG_ICH_LRC10
@ MISCREG_ICH_LRC10
Definition: miscregs.hh:1038
ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: miscregs.hh:245
ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition: miscregs.hh:180
ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition: miscregs.hh:518
ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition: miscregs.hh:248
ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition: miscregs.hh:132
ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition: miscregs.hh:567
ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition: miscregs.hh:646
ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition: miscregs.hh:660
ArmISA::unflattenResultMiscReg
int unflattenResultMiscReg[NUM_MISCREGS]
If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
Definition: miscregs.cc:1344
ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition: miscregs.hh:658
ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition: miscregs.hh:885
ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition: miscregs.hh:336
ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition: miscregs.hh:782
ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition: miscregs.hh:81
ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition: miscregs.hh:64
ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition: miscregs.hh:226
ArmISA::MISCREG_ICH_LR6
@ MISCREG_ICH_LR6
Definition: miscregs.hh:1018
ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition: miscregs.hh:150
ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition: miscregs.hh:987
ArmISA::MISCREG_ICH_LRC5
@ MISCREG_ICH_LRC5
Definition: miscregs.hh:1033
ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition: miscregs.hh:737
ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition: miscregs.hh:191
ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition: miscregs.hh:522
ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition: miscregs.hh:408
ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition: miscregs.hh:136
ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition: miscregs.hh:530
ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition: miscregs.hh:795
ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition: miscregs.hh:65
ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition: miscregs.hh:755
ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition: miscregs.hh:1028
ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition: miscregs.hh:509
ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition: miscregs.hh:309
ArmISA::canWriteCoprocReg
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to write coprocessor registers.
Definition: miscregs.cc:1253
ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition: miscregs.hh:500
ArmISA::MISCREG_TLBI_VAALE1IS_Xt
@ MISCREG_TLBI_VAALE1IS_Xt
Definition: miscregs.hh:675
ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition: miscregs.hh:223
ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition: miscregs.hh:170
ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition: miscregs.cc:1347
ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition: miscregs.hh:830
ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition: miscregs.hh:835
ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition: miscregs.hh:989
ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition: miscregs.hh:840
ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition: miscregs.hh:114
ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:204
ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition: miscregs.hh:851
ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition: miscregs.hh:647
ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition: miscregs.hh:115
ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition: miscregs.hh:1049
ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition: miscregs.hh:312
ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition: miscregs.hh:354
ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition: miscregs.hh:820
ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition: miscregs.hh:511
ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition: miscregs.hh:1046
ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition: miscregs.hh:648
ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition: miscregs.hh:444
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition: miscregs.hh:976
ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: miscregs.hh:559
ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition: miscregs.hh:384
ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition: miscregs.hh:711
ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition: miscregs.hh:394
ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition: miscregs.hh:383
ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition: miscregs.hh:570
ArmISA::MISCREG_HYP_E2H_WR
@ MISCREG_HYP_E2H_WR
Definition: miscregs.hh:1126
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:745
ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition: miscregs.hh:194
ArmISA::MISCREG_ICC_AP1R2_S
@ MISCREG_ICC_AP1R2_S
Definition: miscregs.hh:963
ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition: miscregs.hh:258
ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition: miscregs.hh:362
ArmISA::EL0
@ EL0
Definition: types.hh:622
ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition: miscregs.hh:331
ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition: miscregs.hh:514
ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition: miscregs.hh:527
ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition: miscregs.hh:255
ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition: miscregs.hh:990
ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition: miscregs.hh:783
ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition: miscregs.hh:528
ArmISA::MISCREG_TLBI_VAAE1IS_Xt
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: miscregs.hh:673
ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition: miscregs.hh:297
ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition: miscregs.hh:93
ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition: miscregs.hh:452
ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition: miscregs.hh:272
ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition: miscregs.hh:322
ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition: miscregs.cc:1311
ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition: miscregs.hh:888
ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition: miscregs.hh:483
ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition: miscregs.hh:968
ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition: miscregs.hh:74
ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition: miscregs.hh:502
ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition: miscregs.hh:211
ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition: miscregs.hh:198
ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition: miscregs.hh:138
ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition: miscregs.hh:515
ArmISA::MISCREG_ICC_SRE_S
@ MISCREG_ICC_SRE_S
Definition: miscregs.hh:996
ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition: miscregs.hh:610
ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition: miscregs.hh:352
ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition: miscregs.hh:750
ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition: miscregs.hh:869
ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition: miscregs.hh:107
ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition: miscregs.hh:847
ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition: miscregs.hh:286
ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition: miscregs.hh:298
ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition: miscregs.hh:836
ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: miscregs.hh:614
ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition: miscregs.hh:448
ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition: miscregs.hh:253
ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition: miscregs.hh:250
ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition: miscregs.hh:195
ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition: miscregs.hh:703
ArmISA::MISCREG_ICH_LR1_EL2
@ MISCREG_ICH_LR1_EL2
Definition: miscregs.hh:892
ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition: miscregs.hh:589
ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition: miscregs.hh:877
ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:143
ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition: miscregs.hh:616
ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition: miscregs.hh:270
ArmISA::decodeCP14Reg
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: miscregs.cc:51
ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition: miscregs.hh:1009
ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition: miscregs.hh:291
ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition: miscregs.hh:597
ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: miscregs.hh:612
ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition: miscregs.hh:1077
ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition: miscregs.hh:328
ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition: miscregs.hh:752
ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition: miscregs.hh:213
ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition: miscregs.hh:1002
ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition: miscregs.hh:568
ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition: miscregs.hh:794
ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition: miscregs.hh:952
ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition: miscregs.hh:764
ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition: miscregs.hh:740
ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition: miscregs.hh:316
ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition: miscregs.hh:489
ArmISA::MISCREG_TLBI_VMALLE1
@ MISCREG_TLBI_VMALLE1
Definition: miscregs.hh:676
ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition: miscregs.hh:222
ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition: miscregs.hh:206
ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition: miscregs.hh:473
ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition: miscregs.hh:784
ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition: miscregs.hh:551
ArmISA::MISCREG_TLBI_VMALLS12E1
@ MISCREG_TLBI_VMALLS12E1
Definition: miscregs.hh:695
ArmISA::MISCREG_TLBI_VALE3IS_Xt
@ MISCREG_TLBI_VALE3IS_Xt
Definition: miscregs.hh:698
ArmISA::MISCREG_MON_E2H_RD
@ MISCREG_MON_E2H_RD
Definition: miscregs.hh:1134
ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition: miscregs.hh:435
ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition: miscregs.hh:496
ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition: miscregs.hh:656
ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition: miscregs.hh:829
ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition: miscregs.hh:717
ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition: miscregs.hh:972
ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition: miscregs.hh:802
ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition: miscregs.hh:421
ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition: miscregs.hh:756
ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: miscregs.hh:235
ArmISA::MISCREG_HYP_RD
@ MISCREG_HYP_RD
Definition: miscregs.hh:1122
ArmISA::canReadCoprocReg
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to read coprocessor registers.
Definition: miscregs.cc:1207
ArmISA::MISCREG_ICH_LR13_EL2
@ MISCREG_ICH_LR13_EL2
Definition: miscregs.hh:904
ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:644
ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition: miscregs.hh:370
ArmISA::MISCREG_TLBI_ALLE3
@ MISCREG_TLBI_ALLE3
Definition: miscregs.hh:699
ArmISA::MISCREG_ICH_LRC4
@ MISCREG_ICH_LRC4
Definition: miscregs.hh:1032
ArmISA::MISCREG_ICH_LR3_EL2
@ MISCREG_ICH_LR3_EL2
Definition: miscregs.hh:894
ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition: miscregs.hh:993
ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition: miscregs.hh:819
ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition: miscregs.hh:417
ArmISA::MISCREG_ICH_LRC1
@ MISCREG_ICH_LRC1
Definition: miscregs.hh:1029
ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition: miscregs.hh:69
ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition: miscregs.hh:412
ArmISA::MISCREG_ICH_LRC2
@ MISCREG_ICH_LRC2
Definition: miscregs.hh:1030
ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition: miscregs.hh:386
ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition: miscregs.hh:753
ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition: miscregs.hh:645
ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition: miscregs.hh:391
ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition: miscregs.hh:978
ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition: miscregs.hh:969
ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition: miscregs.hh:172
ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition: miscregs.hh:1129
ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition: miscregs.hh:588
ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition: miscregs.hh:416
ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition: miscregs.hh:739
ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition: miscregs.hh:1113
ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition: miscregs.hh:520
ArmISA::MISCREG_TLBI_ASIDE1IS_Xt
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: miscregs.hh:672
ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition: miscregs.hh:77
ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition: miscregs.hh:99
ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition: miscregs.hh:491
ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition: miscregs.hh:190
ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition: miscregs.hh:526
ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: miscregs.hh:683
ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition: miscregs.hh:654
ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition: miscregs.hh:83
ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition: miscregs.hh:76
ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition: miscregs.hh:247
ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition: miscregs.hh:998
ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition: miscregs.hh:905
ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition: miscregs.hh:983
ArmISA::MISCREG_ICH_LR4
@ MISCREG_ICH_LR4
Definition: miscregs.hh:1016
ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition: miscregs.hh:564
ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition: miscregs.hh:431
ArmISA::MISCREG_ICH_LRC14
@ MISCREG_ICH_LRC14
Definition: miscregs.hh:1042
ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition: miscregs.hh:769
ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition: miscregs.hh:487
ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition: miscregs.hh:311
ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition: miscregs.hh:512
ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition: miscregs.hh:307
ArmISA::EL3
@ EL3
Definition: types.hh:625
ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition: miscregs.hh:886
ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition: miscregs.hh:175
ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: miscregs.cc:339
ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition: miscregs.hh:618
ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition: miscregs.hh:174
ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition: miscregs.hh:66
ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition: miscregs.hh:855
ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition: miscregs.hh:126
ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition: miscregs.hh:731
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition: miscregs.hh:821
ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition: miscregs.hh:451
ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition: miscregs.hh:330
ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition: miscregs.hh:1119
ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition: miscregs.hh:218
ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition: miscregs.hh:882
ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition: miscregs.hh:390
ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition: miscregs.hh:631
ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition: miscregs.hh:596
ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition: miscregs.hh:547
ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition: miscregs.hh:212
ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition: miscregs.hh:1003
ArmISA::ISA
Definition: isa.hh:65
ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition: miscregs.hh:447
ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition: miscregs.hh:450
ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition: miscregs.hh:898
ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition: miscregs.hh:992
ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition: miscregs.hh:381
ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition: miscregs.hh:221
ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition: miscregs.hh:838
ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition: miscregs.hh:144
ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition: miscregs.hh:770
ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition: miscregs.hh:859
ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition: miscregs.hh:606
ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition: miscregs.hh:104
ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition: miscregs.hh:575
ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition: miscregs.hh:751
ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition: miscregs.hh:1043
ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition: miscregs.hh:586
ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition: miscregs.hh:970
ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition: miscregs.hh:440
ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition: miscregs.hh:292
ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition: miscregs.cc:1363
ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition: miscregs.hh:1050
ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition: miscregs.hh:513
ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition: miscregs.hh:652
ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition: miscregs.hh:284
ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: miscregs.hh:88
ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition: miscregs.hh:441
ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition: miscregs.hh:833
ArmISA
Definition: ccregs.hh:41
ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition: miscregs.hh:129
ArmISA::MISCREG_TLBI_VALE2IS_Xt
@ MISCREG_TLBI_VALE2IS_Xt
Definition: miscregs.hh:687
ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition: miscregs.hh:602
ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition: miscregs.hh:667
ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition: miscregs.hh:1013
ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition: miscregs.hh:205
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition: miscregs.hh:742
ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition: miscregs.hh:566
ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition: miscregs.hh:320
ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition: miscregs.hh:130
ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition: miscregs.hh:548
ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition: miscregs.hh:300
ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition: miscregs.hh:164
ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition: miscregs.hh:334
ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition: miscregs.hh:967
ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition: miscregs.hh:1080
ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition: miscregs.hh:418
ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition: miscregs.hh:228
ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition: miscregs.hh:409
ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition: miscregs.hh:407
ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition: miscregs.hh:862
ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition: miscregs.hh:482
ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition: miscregs.hh:271
ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition: miscregs.hh:411
ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition: miscregs.hh:561
ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition: miscregs.hh:635
ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition: miscregs.hh:505
ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition: miscregs.hh:760
ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition: miscregs.hh:982
ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition: miscregs.hh:883
ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition: miscregs.hh:327
ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition: miscregs.hh:177
ArmISA::MISCREG_ICC_AP1R2_EL1_NS
@ MISCREG_ICC_AP1R2_EL1_NS
Definition: miscregs.hh:845
ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition: miscregs.hh:615
ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition: miscregs.hh:557
ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: miscregs.hh:79
ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition: miscregs.hh:485
ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition: miscregs.hh:498
ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition: miscregs.hh:659
ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition: miscregs.hh:367
ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition: miscregs.hh:131
ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition: miscregs.hh:239
ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition: miscregs.hh:499
ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition: miscregs.hh:145
ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition: miscregs.hh:540
ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition: miscregs.hh:1006
ArmISA::MISCREG_ICH_LR11
@ MISCREG_ICH_LR11
Definition: miscregs.hh:1023
ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition: miscregs.hh:337
ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition: miscregs.hh:872
ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition: miscregs.hh:147
ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition: miscregs.hh:420
ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition: miscregs.hh:556
ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition: miscregs.hh:225
ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition: miscregs.hh:749
ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition: miscregs.hh:649
ArmISA::MISCREG_ICH_LRC9
@ MISCREG_ICH_LRC9
Definition: miscregs.hh:1037
ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition: miscregs.hh:117
ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition: miscregs.hh:732
ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition: miscregs.hh:549
ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition: miscregs.hh:268
ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition: miscregs.hh:664
ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition: miscregs.hh:778
ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition: miscregs.hh:712
ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition: miscregs.hh:358
ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition: miscregs.hh:786
ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition: miscregs.hh:364
ArmISA::MISCREG_ICH_LR3
@ MISCREG_ICH_LR3
Definition: miscregs.hh:1015
ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition: miscregs.hh:984
ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition: miscregs.hh:634
ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition: miscregs.hh:850
ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition: miscregs.hh:517
ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition: miscregs.hh:469
ArmISA::MISCREG_RAZ
@ MISCREG_RAZ
Definition: miscregs.hh:1061
ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition: miscregs.hh:166
ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition: miscregs.hh:80
ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition: miscregs.hh:375
ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition: miscregs.hh:344
ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition: miscregs.hh:468
ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition: miscregs.hh:720
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition: miscregs.hh:133
ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition: miscregs.hh:279
ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition: miscregs.hh:350
ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition: miscregs.hh:85
ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition: miscregs.hh:438
ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition: miscregs.hh:488
ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition: miscregs.hh:759
ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition: miscregs.hh:155
ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition: miscregs.hh:523
ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition: miscregs.hh:214
ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition: miscregs.hh:854
ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition: miscregs.hh:657
ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition: miscregs.hh:168
ArmISA::MISCREG_TLBI_VAE3IS_Xt
@ MISCREG_TLBI_VAE3IS_Xt
Definition: miscregs.hh:697
ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition: miscregs.hh:458
ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition: miscregs.hh:106
ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:383
ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition: miscregs.hh:288
ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition: miscregs.hh:98
ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition: miscregs.hh:393
ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition: miscregs.hh:541
ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition: miscregs.hh:207
ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition: miscregs.hh:388
ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition: miscregs.hh:1115
ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition: miscregs.hh:796
ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition: miscregs.hh:546
ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition: miscregs.hh:951
ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition: miscregs.hh:202
ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition: miscregs.hh:167
ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition: miscregs.hh:841
ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition: miscregs.hh:422
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:553
ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition: miscregs.hh:282
ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition: miscregs.hh:95
ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition: miscregs.hh:325
ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition: miscregs.hh:642
ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition: miscregs.hh:1017
ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition: miscregs.hh:429
ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:161
ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition: miscregs.hh:650
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: miscregs.hh:78
ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition: miscregs.hh:804
ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition: miscregs.hh:1128
ArmISA::MISCREG_SCTLR_RST
@ MISCREG_SCTLR_RST
Definition: miscregs.hh:87
ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition: miscregs.hh:971
ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition: miscregs.hh:799
ArmISA::MISCREG_ICH_LR12
@ MISCREG_ICH_LR12
Definition: miscregs.hh:1024
ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition: miscregs.hh:281
ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition: miscregs.hh:640
ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition: miscregs.hh:636
ArmISA::MISCREG_ICC_AP1R1_NS
@ MISCREG_ICC_AP1R1_NS
Definition: miscregs.hh:959
ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition: miscregs.hh:378
ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition: miscregs.hh:503
ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition: miscregs.hh:173
ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition: miscregs.hh:101
ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition: miscregs.hh:339
ArmISA::MISCREG_HYP_E2H_RD
@ MISCREG_HYP_E2H_RD
Definition: miscregs.hh:1125
ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition: miscregs.hh:572
ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition: miscregs.hh:723
ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition: miscregs.hh:856
ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition: miscregs.hh:741
ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition: miscregs.hh:156
ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition: miscregs.hh:395
ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition: miscregs.hh:1076
ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition: miscregs.hh:449
ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition: miscregs.hh:242
ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition: miscregs.hh:544
ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition: miscregs.hh:539
ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition: miscregs.hh:809
ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition: miscregs.hh:902
ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition: miscregs.hh:627
ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition: miscregs.cc:1299
ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition: miscregs.hh:263
ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition: miscregs.hh:301
ArmISA::MISCREG_TLBI_VAE1IS_Xt
@ MISCREG_TLBI_VAE1IS_Xt
Definition: miscregs.hh:671
ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition: miscregs.hh:493
ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition: miscregs.hh:979
ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:621
ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition: miscregs.hh:261
ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition: miscregs.hh:368
ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition: miscregs.hh:360
ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition: miscregs.hh:785
ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition: miscregs.hh:803
ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition: miscregs.hh:82
ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition: miscregs.hh:204
ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition: miscregs.hh:884
ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition: miscregs.hh:162
ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition: miscregs.hh:1082
ArmISA::MISCREG_ICC_AP1R1_EL1_NS
@ MISCREG_ICC_AP1R1_EL1_NS
Definition: miscregs.hh:842
ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition: miscregs.hh:581
ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition: miscregs.hh:666
ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition: miscregs.hh:538
ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition: miscregs.hh:706
ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition: miscregs.hh:852
ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition: miscregs.hh:424
ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition: miscregs.hh:981
ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition: miscregs.hh:825
ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition: miscregs.hh:562
ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition: miscregs.hh:521
ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition: miscregs.hh:953
isa.hh
ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition: miscregs.hh:1036
ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition: miscregs.hh:639
ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition: miscregs.hh:728
ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition: miscregs.hh:365
ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition: miscregs.hh:863
ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition: miscregs.hh:663
ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition: miscregs.hh:466
ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition: miscregs.hh:653
ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition: miscregs.hh:704
ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition: miscregs.hh:486
ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition: miscregs.hh:1027
ArmISA::MISCREG_TPIDRURO
@ MISCREG_TPIDRURO
Definition: miscregs.hh:399
ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition: miscregs.hh:100
ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition: miscregs.hh:800
ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition: miscregs.hh:725
ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition: miscregs.hh:608
ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition: miscregs.hh:495
ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition: miscregs.hh:818
ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition: miscregs.hh:822
ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition: miscregs.hh:484
ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition: miscregs.hh:264
ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition: miscregs.hh:757
ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition: miscregs.hh:216
ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition: miscregs.hh:60
ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition: miscregs.hh:797
ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition: miscregs.hh:593
ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition: miscregs.hh:109
ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition: miscregs.hh:392
ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition: miscregs.hh:961
ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition: miscregs.hh:1075
ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition: miscregs.hh:529
ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition: miscregs.hh:895
ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition: miscregs.hh:887
ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition: miscregs.hh:889
ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition: miscregs.hh:140
ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition: miscregs.hh:189
ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition: miscregs.hh:219
ArmISA::el
Bitfield< 3, 2 > el
Definition: miscregs_types.hh:69
ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition: miscregs.hh:730
ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition: miscregs.hh:361
ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition: miscregs.hh:63
ArmISA::MISCREG_ICH_LRC3
@ MISCREG_ICH_LRC3
Definition: miscregs.hh:1031
ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition: miscregs.hh:335
ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition: miscregs.hh:267
ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition: miscregs.hh:524
ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition: miscregs.hh:254
ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition: miscregs.hh:346
ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition: miscregs.hh:991
ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition: miscregs.hh:262
ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition: miscregs.hh:348
ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition: miscregs.hh:555
ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition: miscregs.hh:234
ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition: miscregs.hh:843
ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition: miscregs.hh:152
ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition: miscregs.hh:492
ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition: miscregs.hh:577
ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition: miscregs.hh:477
ArmISA::MISCREG_HYP_WR
@ MISCREG_HYP_WR
Definition: miscregs.hh:1123
ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition: miscregs.hh:276
ArmISA::MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_TLBI_VMALLS12E1IS
Definition: miscregs.hh:688
ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition: miscregs.hh:376
ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition: miscregs.hh:273
ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition: miscregs.hh:379
ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition: miscregs.hh:231
ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition: miscregs.hh:455
M5_FALLTHROUGH
#define M5_FALLTHROUGH
Definition: compiler.hh:84
ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition: miscregs.hh:120
ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition: miscregs.hh:377
ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition: miscregs.hh:777
ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition: miscregs.hh:641
ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition: miscregs.hh:332
ArmISA::MISCREG_TLBI_VAAE1_Xt
@ MISCREG_TLBI_VAAE1_Xt
Definition: miscregs.hh:679
ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition: miscregs.hh:169
ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition: miscregs.hh:232
ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition: miscregs.hh:249
ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition: types.hh:115
ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:639
ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition: miscregs.hh:462
ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition: miscregs.hh:729
ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition: miscregs.hh:762
ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition: miscregs.hh:637
ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition: miscregs.hh:595
ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition: miscregs.hh:837
ArmISA::MISCREG_TLBI_VMALLE1IS
@ MISCREG_TLBI_VMALLE1IS
Definition: miscregs.hh:670
ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition: miscregs.hh:342
ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition: miscregs.hh:780
ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition: miscregs.hh:305
ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition: miscregs.hh:259
ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition: miscregs.hh:721
ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition: miscregs.hh:181
ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition: miscregs.hh:754
ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition: miscregs.hh:230
ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition: miscregs.hh:584
ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition: miscregs.hh:432
ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition: miscregs.hh:404
ArmISA::MISCREG_TLBI_VAE2_Xt
@ MISCREG_TLBI_VAE2_Xt
Definition: miscregs.hh:692
ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition: miscregs.hh:633
ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition: miscregs.hh:844
ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition: miscregs.hh:506
ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition: miscregs.hh:304
ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition: miscregs.hh:479
ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition: miscregs.hh:113
ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition: miscregs.hh:839
ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition: miscregs.hh:900
ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition: miscregs.hh:787
ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition: miscregs.hh:185
ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition: miscregs.hh:371
ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition: miscregs.hh:403
ArmISA::MISCREG_VSTTBR_EL2
@ MISCREG_VSTTBR_EL2
Definition: miscregs.hh:599
ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition: miscregs.hh:293
ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition: miscregs.hh:278
ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition: miscregs.hh:159
ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition: miscregs.hh:601
ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition: miscregs.hh:135
ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition: miscregs.hh:594
ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition: miscregs.hh:510
ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:637
ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition: miscregs.hh:321
ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition: miscregs.hh:860
ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition: miscregs.hh:317
ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition: miscregs.hh:243
ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition: miscregs.hh:160
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:578
ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition: miscregs.hh:714
ArmISA::decodeCP15Reg64
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition: miscregs.cc:1148
ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition: miscregs.hh:861
ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition: miscregs.hh:1120
ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition: miscregs.hh:788
ArmISA::MISCREG_TLBI_ALLE3IS
@ MISCREG_TLBI_ALLE3IS
Definition: miscregs.hh:696
ArmISA::MISCREG_ICH_LR14
@ MISCREG_ICH_LR14
Definition: miscregs.hh:1026
ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition: miscregs.hh:465
ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition: miscregs.hh:591
ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition: miscregs.hh:91
ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition: miscregs.hh:58
ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition: miscregs.hh:626
ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition: miscregs.hh:265
ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition: miscregs.hh:326
ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition: miscregs.hh:535
ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: miscregs.hh:71
ArmISA::EL1
@ EL1
Definition: types.hh:623
ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition: miscregs.hh:256
ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition: miscregs.hh:605
ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition: miscregs.hh:726
ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition: miscregs.hh:622
ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition: miscregs.hh:116
ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition: miscregs.hh:735
ArmISA::MISCREG_ICC_AP1R1_S
@ MISCREG_ICC_AP1R1_S
Definition: miscregs.hh:960
ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition: miscregs.hh:303
ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition: miscregs.hh:340
ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition: miscregs.hh:891
ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition: miscregs.hh:848
ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition: miscregs.hh:789
ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition: miscregs.hh:746
ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition: miscregs.hh:625
ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition: miscregs.hh:252
ArmISA::MISCREG_ICH_LR12_EL2
@ MISCREG_ICH_LR12_EL2
Definition: miscregs.hh:903
ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition: miscregs.hh:519
ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition: miscregs.hh:824
ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition: miscregs.hh:359
ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition: miscregs.hh:1069
ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition: miscregs.hh:280
ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition: miscregs.hh:727
ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition: miscregs.hh:398
ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition: miscregs.hh:768
ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: miscregs.hh:240
ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition: miscregs.hh:823
ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition: miscregs.hh:329
ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition: miscregs.hh:153
ArmISA::MISCREG_ICC_CTLR_S
@ MISCREG_ICC_CTLR_S
Definition: miscregs.hh:974
ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition: miscregs.hh:203
ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition: miscregs.hh:832
ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition: miscregs.hh:857
ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition: miscregs.hh:651
ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition: miscregs.hh:68
ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition: miscregs.hh:481
ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition: miscregs.hh:1047
full_system.hh
ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition: miscregs.hh:369
ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition: miscregs.hh:719
ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition: miscregs.hh:125
ArmISA::MISCREG_TLBI_VALE3_Xt
@ MISCREG_TLBI_VALE3_Xt
Definition: miscregs.hh:701
ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition: miscregs.hh:623
ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition: miscregs.hh:619
ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition: miscregs.hh:713
ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition: miscregs.hh:274
ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition: miscregs.hh:738
ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition: miscregs.hh:573
ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition: miscregs.hh:251
ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition: miscregs.hh:736
ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition: miscregs.hh:357
ArmISA::MISCREG_PAN
@ MISCREG_PAN
Definition: miscregs.hh:1085
ArmISA::MISCREG_ICC_SRE_EL1_S
@ MISCREG_ICC_SRE_EL1_S
Definition: miscregs.hh:866
ArmISA::MISCREG_TLBI_VALE2_Xt
@ MISCREG_TLBI_VALE2_Xt
Definition: miscregs.hh:694
ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition: miscregs.hh:765
ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition: miscregs.hh:1132
ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition: miscregs.hh:111
ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition: miscregs.hh:707
ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition: miscregs.hh:871
ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition: miscregs.hh:582
ArmISA::MISCREG_TPIDRPRW
@ MISCREG_TPIDRPRW
Definition: miscregs.hh:402
ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition: miscregs.hh:1117
ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition: miscregs.hh:890
ArmISA::MISCREG_ICC_SRE_NS
@ MISCREG_ICC_SRE_NS
Definition: miscregs.hh:995
ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition: miscregs.hh:363
miscregs.hh
ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition: miscregs.hh:475
ArmISA::MISCREG_ICH_LRC12
@ MISCREG_ICH_LRC12
Definition: miscregs.hh:1040
ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition: miscregs.hh:295
ArmISA::MISCREG_TLBI_VAE1_Xt
@ MISCREG_TLBI_VAE1_Xt
Definition: miscregs.hh:677
ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition: miscregs.hh:456
ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition: miscregs.hh:343
ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition: miscregs.hh:260
ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: miscregs.hh:585
ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition: miscregs.hh:790
ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition: miscregs.hh:285
ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition: miscregs.hh:776
ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition: miscregs.hh:1011
ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition: miscregs.hh:423
ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition: miscregs.hh:209
ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: miscregs.hh:580
ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition: miscregs.hh:1106
ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition: miscregs.hh:163
ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition: miscregs.hh:873
ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition: miscregs.hh:62
ArmISA::canWriteAArch64SysReg
bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: miscregs.cc:1411
ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition: miscregs.hh:385
ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition: miscregs.hh:831
ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:638
ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:641
ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition: miscregs.hh:817
ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition: miscregs.hh:609
ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition: miscregs.hh:743
ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition: miscregs.hh:355
ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition: miscregs.hh:372
ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition: miscregs.hh:958
ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition: miscregs.hh:236
ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition: miscregs.hh:349
ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition: miscregs.hh:467
ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition: miscregs.hh:269
ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition: miscregs.hh:184
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition: miscregs.hh:773
ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition: miscregs.hh:954
ArmISA::MISCREG_TLBI_VALE1IS_Xt
@ MISCREG_TLBI_VALE1IS_Xt
Definition: miscregs.hh:674
ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition: miscregs.hh:801
ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition: miscregs.hh:146
ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition: miscregs.hh:1112
ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition: miscregs.hh:472
ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition: miscregs.hh:767
ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition: miscregs.hh:607
ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition: miscregs.hh:897
ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: miscregs.hh:613
ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition: miscregs.hh:405
ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition: miscregs.hh:986
ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition: miscregs.hh:662
ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition: miscregs.hh:238
ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition: miscregs.hh:128
ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition: miscregs.hh:563
ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition: miscregs.hh:629
ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition: miscregs.hh:459
ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition: miscregs.hh:1020
ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition: miscregs.hh:808
ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition: miscregs.hh:374
ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition: miscregs.hh:165
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition: miscregs.hh:97
ArmISA::MISCREG_TLBI_ALLE2IS
@ MISCREG_TLBI_ALLE2IS
Definition: miscregs.hh:684
ArmISA::MISCREG_TLBI_ALLE1IS
@ MISCREG_TLBI_ALLE1IS
Definition: miscregs.hh:686
ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition: miscregs.hh:536
ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition: miscregs.hh:415
ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition: miscregs.hh:545
ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition: miscregs.hh:791
ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: miscregs.hh:579
ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition: miscregs.hh:210
ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition: miscregs.hh:1000
ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition: miscregs.hh:1114
ArmISA::MISCREG_TLBI_VAE3_Xt
@ MISCREG_TLBI_VAE3_Xt
Definition: miscregs.hh:700
ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition: miscregs.hh:430
ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition: miscregs.hh:341
ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition: miscregs.hh:319
ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:208
ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition: miscregs.hh:1039
ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition: miscregs.hh:401
ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition: miscregs.hh:853
ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition: miscregs.hh:1074
ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition: miscregs.hh:722
ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition: miscregs.hh:277
ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition: miscregs.hh:192
ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition: miscregs.hh:1118
ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition: miscregs.hh:798
ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition: miscregs.hh:123
ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition: miscregs.hh:999
ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: miscregs.hh:1088
ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition: miscregs.hh:186
ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition: miscregs.hh:1007
ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition: miscregs.hh:217
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition: miscregs.hh:600
ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition: miscregs.hh:84
ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition: miscregs.hh:86
ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition: miscregs.hh:906
ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition: miscregs.hh:464
ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition: miscregs.hh:61
ArmISA::MISCREG_TLBI_VAALE1_Xt
@ MISCREG_TLBI_VAALE1_Xt
Definition: miscregs.hh:681
ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition: miscregs.hh:880
ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition: miscregs.hh:1131
ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition: miscregs.hh:382
ArmISA::MiscRegIndex
MiscRegIndex
Definition: miscregs.hh:56
ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition: miscregs.hh:881
ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: miscregs.cc:1442
ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition: miscregs.hh:246
ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition: miscregs.hh:533
ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition: miscregs.hh:149
ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition: miscregs.hh:227
ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition: miscregs.hh:397
ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition: miscregs.hh:734
ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition: miscregs.hh:257
ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition: miscregs.hh:154
ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition: miscregs.hh:215
ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition: miscregs.hh:266
ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition: miscregs.hh:1004
ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition: miscregs.hh:805
ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition: miscregs.hh:179
ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition: miscregs.hh:955
ArmISA::MISCREG_NOP
@ MISCREG_NOP
Definition: miscregs.hh:1060
ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition: miscregs.hh:94
ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition: miscregs.hh:1078
ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition: miscregs.hh:988
ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition: miscregs.hh:534
logging.hh
ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition: miscregs.hh:324
ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition: miscregs.hh:323
ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition: miscregs.hh:1005
ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition: miscregs.hh:508
ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition: miscregs.hh:715
ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition: miscregs.hh:474
ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition: miscregs.hh:351
ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition: miscregs.hh:208
ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition: miscregs.hh:443
ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition: miscregs.hh:632
ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition: miscregs.hh:1019
ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition: miscregs.hh:494
ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition: miscregs.hh:296
ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition: miscregs.hh:901
ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition: miscregs.hh:1008
ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition: miscregs.hh:67
ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition: miscregs.hh:962
ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition: miscregs.hh:457
ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition: miscregs.hh:569
ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition: miscregs.hh:139
ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition: miscregs.hh:463
ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition: miscregs.hh:176
ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition: miscregs.hh:733
ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition: miscregs.hh:1079
ArmISA::MISCREG_TLBI_IPAS2E1_Xt
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: miscregs.hh:689
ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition: miscregs.hh:592
ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition: miscregs.hh:366
ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition: miscregs.hh:414
ArmISA::MISCREG_ICH_LR5_EL2
@ MISCREG_ICH_LR5_EL2
Definition: miscregs.hh:896
ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:640
ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition: miscregs.hh:747
ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition: miscregs.hh:724
ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition: miscregs.hh:137
ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition: miscregs.hh:705
ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition: miscregs.hh:718
ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition: miscregs.hh:710
ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition: miscregs.hh:565
ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition: miscregs.hh:161
ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition: miscregs.hh:102
ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition: miscregs.hh:400
ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition: miscregs.hh:380
ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition: miscregs.hh:283
ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition: miscregs.hh:310
ArmISA::MISCREG_ICH_LRC13
@ MISCREG_ICH_LRC13
Definition: miscregs.hh:1041
ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition: miscregs.hh:193
ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition: miscregs.hh:774
ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition: miscregs.hh:187
ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition: miscregs.hh:121
ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition: miscregs.hh:436
ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition: miscregs.hh:124
ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition: miscregs.hh:980
ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition: miscregs.hh:1010
ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition: miscregs.hh:598
ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition: miscregs.hh:812
ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition: miscregs.hh:537
ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: miscregs.hh:229
ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition: miscregs.hh:1073
ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition: miscregs.hh:275
ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition: miscregs.hh:867
ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition: miscregs.hh:413
ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition: miscregs.hh:543
ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition: miscregs.hh:879
ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition: miscregs.hh:665
ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition: miscregs.hh:708
ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition: miscregs.hh:306
ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition: miscregs.hh:516
ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition: miscregs.hh:763
ArmISA::MISCREG_ICC_AP1R0_NS
@ MISCREG_ICC_AP1R0_NS
Definition: miscregs.hh:956
ArmISA::MISCREG_TLBI_ALLE1
@ MISCREG_TLBI_ALLE1
Definition: miscregs.hh:693
ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition: miscregs.hh:1012
ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition: miscregs.hh:497
ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition: miscregs.hh:994
ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: miscregs.hh:611
ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: miscregs.hh:574
ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition: miscregs.hh:748
ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition: miscregs.hh:122
ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition: miscregs.hh:1072
ArmISA::MISCREG_ICH_LR8_EL2
@ MISCREG_ICH_LR8_EL2
Definition: miscregs.hh:899
ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition: miscregs.hh:480
ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:636
ArmISA::MISCREG_CP14_UNIMPL
@ MISCREG_CP14_UNIMPL
Definition: miscregs.hh:1062
ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition: miscregs.hh:437
ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition: miscregs.hh:141
ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition: miscregs.hh:793
ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition: miscregs.hh:439
ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition: miscregs.hh:643
ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition: miscregs.hh:201
ArmISA::MISCREG_ICH_LRC6
@ MISCREG_ICH_LRC6
Definition: miscregs.hh:1034
ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition: miscregs.hh:624
ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition: miscregs.hh:583
ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition: miscregs.hh:157
ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition: miscregs.hh:985
ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition: miscregs.hh:542
ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition: miscregs.hh:287
ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition: miscregs.hh:289
ArmISA::MISCREG_ICH_LR2_EL2
@ MISCREG_ICH_LR2_EL2
Definition: miscregs.hh:893
ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition: miscregs.hh:112
ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition: miscregs.hh:389
ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition: miscregs.hh:105
ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition: miscregs.hh:151
ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition: miscregs.hh:858
ArmISA::MISCREG_TLBI_ALLE2
@ MISCREG_TLBI_ALLE2
Definition: miscregs.hh:691
ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition: miscregs.hh:197
ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition: miscregs.hh:1064
ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition: miscregs.hh:103
ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition: miscregs.hh:294
ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition: miscregs.hh:426
ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition: miscregs.hh:333
ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition: miscregs.hh:870
ArmISA::MISCREG_TLBI_IPAS2LE1_Xt
@ MISCREG_TLBI_IPAS2LE1_Xt
Definition: miscregs.hh:690
ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg, ThreadContext *tc)
Definition: utility.cc:994
ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition: miscregs.hh:975
ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition: miscregs.hh:237
ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition: miscregs.hh:244
ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition: miscregs.hh:410
ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition: miscregs.hh:356
ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition: miscregs.hh:476
ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition: miscregs.hh:957
ArmISA::MISCREG_TLBI_VALE1_Xt
@ MISCREG_TLBI_VALE1_Xt
Definition: miscregs.hh:680
ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition: miscregs.hh:478
ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition: miscregs.hh:427
ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition: miscregs.hh:655
ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition: miscregs.hh:1100
ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: miscregs.hh:587
ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition: miscregs.hh:617
ArmISA::MISCREG_ICH_LR9
@ MISCREG_ICH_LR9
Definition: miscregs.hh:1021
ArmISA::MISCREG_ICC_AP1R2_EL1_S
@ MISCREG_ICC_AP1R2_EL1_S
Definition: miscregs.hh:846
ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition: miscregs.hh:425
ArmISA::miscRegInfo
bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:3381
ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition: miscregs.hh:196
ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition: miscregs.hh:864
ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition: miscregs.hh:621
ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition: miscregs.hh:576
ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition: miscregs.hh:554
ArmISA::canReadAArch64SysReg
bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: miscregs.cc:1369
ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition: miscregs.hh:338
ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition: miscregs.hh:525
ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition: miscregs.hh:501
ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition: miscregs.hh:171
ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition: miscregs.hh:442
ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition: miscregs.hh:460
ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition: miscregs.hh:314
ArmISA::MISCREG_CP15_UNIMPL
@ MISCREG_CP15_UNIMPL
Definition: miscregs.hh:1063
ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition: miscregs.hh:59
ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition: miscregs.hh:878
ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition: miscregs.hh:96
thread_context.hh
ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition: miscregs.hh:233
ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition: miscregs.hh:118
ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition: miscregs.hh:868
ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition: miscregs.hh:75
ArmISA::MISCREG_ICH_LR13
@ MISCREG_ICH_LR13
Definition: miscregs.hh:1025
ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition: miscregs.hh:224
ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition: miscregs.hh:119
ArmISA::MISCREG_TLBI_VAE2IS_Xt
@ MISCREG_TLBI_VAE2IS_Xt
Definition: miscregs.hh:685
ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition: miscregs.hh:148
ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition: miscregs.hh:453
ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition: miscregs.hh:834
ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition: miscregs.hh:345
ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition: miscregs.hh:220
ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition: miscregs.hh:434
ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition: miscregs.hh:590
ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition: miscregs.hh:433
ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: miscregs.hh:571
ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition: miscregs.hh:373
ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition: miscregs.hh:158
ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition: miscregs.hh:1001
ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition: miscregs.hh:188
ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition: miscregs.hh:849
ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition: miscregs.hh:290
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
Definition: miscregs.cc:1329
ArmISA::MISCREG_TLBI_ASIDE1_Xt
@ MISCREG_TLBI_ASIDE1_Xt
Definition: miscregs.hh:678
ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition: miscregs.hh:702
ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition: miscregs.hh:761
ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition: miscregs.hh:70
ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition: miscregs.hh:1035
ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition: miscregs.hh:299
ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition: miscregs.hh:806
ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition: miscregs.hh:604
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