gem5  v20.1.0.0
tlb.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * Copyright (c) 2007-2008 The Florida State University
5  * Copyright (c) 2009 The University of Edinburgh
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions are
10  * met: redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer;
12  * redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution;
15  * neither the name of the copyright holders nor the names of its
16  * contributors may be used to endorse or promote products derived from
17  * this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include "arch/power/tlb.hh"
33 
34 #include <string>
35 #include <vector>
36 
37 #include "arch/power/faults.hh"
38 #include "arch/power/pagetable.hh"
39 #include "arch/power/utility.hh"
40 #include "base/inifile.hh"
41 #include "base/str.hh"
42 #include "base/trace.hh"
43 #include "cpu/thread_context.hh"
44 #include "debug/Power.hh"
45 #include "debug/TLB.hh"
46 #include "mem/page_table.hh"
47 #include "params/PowerTLB.hh"
48 #include "sim/full_system.hh"
49 #include "sim/process.hh"
50 
51 using namespace std;
52 using namespace PowerISA;
53 
55 //
56 // POWER TLB
57 //
58 
59 #define MODE2MASK(X) (1 << (X))
60 
61 TLB::TLB(const Params *p)
62  : BaseTLB(p), size(p->size), nlu(0)
63 {
64  table = new PowerISA::PTE[size];
65  memset(table, 0, sizeof(PowerISA::PTE[size]));
66  smallPages = 0;
67 }
68 
70 {
71  if (table)
72  delete [] table;
73 }
74 
75 // look up an entry in the TLB
77 TLB::lookup(Addr vpn, uint8_t asn) const
78 {
79  // assume not found...
80  PowerISA::PTE *retval = NULL;
81  PageTable::const_iterator i = lookupTable.find(vpn);
82  if (i != lookupTable.end()) {
83  while (i->first == vpn) {
84  int index = i->second;
85  PowerISA::PTE *pte = &table[index];
86  Addr Mask = pte->Mask;
87  Addr InvMask = ~Mask;
88  Addr VPN = pte->VPN;
89  if (((vpn & InvMask) == (VPN & InvMask))
90  && (pte->G || (asn == pte->asid))) {
91 
92  // We have a VPN + ASID Match
93  retval = pte;
94  break;
95  }
96  ++i;
97  }
98  }
99 
100  DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
101  retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
102  return retval;
103 }
104 
106 TLB::getEntry(unsigned Index) const
107 {
108  // Make sure that Index is valid
109  assert(Index<size);
110  return &table[Index];
111 }
112 
113 int
114 TLB::probeEntry(Addr vpn,uint8_t asn) const
115 {
116  // assume not found...
117  int Ind = -1;
118  PageTable::const_iterator i = lookupTable.find(vpn);
119  if (i != lookupTable.end()) {
120  while (i->first == vpn) {
121  int index = i->second;
122  PowerISA::PTE *pte = &table[index];
123  Addr Mask = pte->Mask;
124  Addr InvMask = ~Mask;
125  Addr VPN = pte->VPN;
126  if (((vpn & InvMask) == (VPN & InvMask))
127  && (pte->G || (asn == pte->asid))) {
128 
129  // We have a VPN + ASID Match
130  Ind = index;
131  break;
132  }
133  ++i;
134  }
135  }
136 
137  DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
138  return Ind;
139 }
140 
141 inline Fault
143 {
144  Addr VAddrUncacheable = 0xA0000000;
145  if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
146 
147  // mark request as uncacheable
149  }
150  return NoFault;
151 }
152 
153 void
154 TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
155 {
156  smallPages=_smallPages;
157  if (Index > size){
158  warn("Attempted to write at index (%d) beyond TLB size (%d)",
159  Index, size);
160  } else {
161 
162  // Update TLB
163  if (table[Index].V0 || table[Index].V1) {
164 
165  // Previous entry is valid
166  PageTable::iterator i = lookupTable.find(table[Index].VPN);
167  lookupTable.erase(i);
168  }
169  table[Index]=pte;
170 
171  // Update fast lookup table
172  lookupTable.insert(make_pair(table[Index].VPN, Index));
173  }
174 }
175 
176 // insert a new TLB entry
177 void
179 {
180  fatal("TLB Insert not yet implemented\n");
181 }
182 
183 void
185 {
186  DPRINTF(TLB, "flushAll\n");
187  memset(table, 0, sizeof(PowerISA::PTE[size]));
188  lookupTable.clear();
189  nlu = 0;
190 }
191 
192 void
194 {
197 
198  for (int i = 0; i < size; i++) {
199  ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
200  table[i].serialize(cp);
201  }
202 }
203 
204 void
206 {
209 
210  for (int i = 0; i < size; i++) {
211  ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
212  if (table[i].V0 || table[i].V1) {
213  lookupTable.insert(make_pair(table[i].VPN, i));
214  }
215  }
216 }
217 
218 Fault
220 {
221  // Instruction accesses must be word-aligned
222  if (req->getVaddr() & 0x3) {
223  DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
224  req->getSize());
225  return std::make_shared<AlignmentFault>();
226  }
227 
228  return tc->getProcessPtr()->pTable->translate(req);
229 }
230 
231 Fault
232 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
233 {
234  return tc->getProcessPtr()->pTable->translate(req);
235 }
236 
237 Fault
239 {
241  "translateAtomic not yet implemented for full system.");
242 
243  if (mode == Execute)
244  return translateInst(req, tc);
245  else
246  return translateData(req, tc, mode == Write);
247 }
248 
249 Fault
251 {
253  "translateFunctional not implemented for full system.");
254  return tc->getProcessPtr()->pTable->translate(req);
255 }
256 
257 void
259  Translation *translation, Mode mode)
260 {
261  assert(translation);
262  translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
263 }
264 
265 Fault
267  ThreadContext *tc, Mode mode) const
268 {
269  return NoFault;
270 }
271 
273 TLB::index(bool advance)
274 {
275  PowerISA::PTE *pte = &table[nlu];
276 
277  if (advance)
278  nextnlu();
279 
280  return *pte;
281 }
282 
284 PowerTLBParams::create()
285 {
286  return new PowerISA::TLB(this);
287 }
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:183
utility.hh
BaseTLB::Translation::finish
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, Mode mode)=0
PowerISA::TLB::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tlb.cc:205
warn
#define warn(...)
Definition: logging.hh:239
PowerISA::TLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) override
Definition: tlb.cc:238
PowerISA::TLB::lookupTable
PageTable lookupTable
Definition: tlb.hh:97
PowerISA::TLB::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) override
Definition: tlb.cc:250
PowerISA::PTE::Mask
Addr Mask
Definition: pagetable.hh:46
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:797
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
PowerISA::TLB::nextnlu
void nextnlu()
Definition: tlb.hh:104
BaseTLB::Mode
Mode
Definition: tlb.hh:57
Loader::Power
@ Power
Definition: object_file.hh:54
PowerISA::TLB::size
int size
Definition: tlb.hh:100
Process::pTable
EmulationPageTable * pTable
Definition: process.hh:174
PowerISA::PTE
Definition: pagetable.hh:42
PowerISA::TLB::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tlb.cc:193
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
PowerISA::TLB::translateInst
Fault translateInst(const RequestPtr &req, ThreadContext *tc)
Definition: tlb.cc:219
BaseTLB
Definition: tlb.hh:50
pagetable.hh
PowerISA::TLB::checkCacheability
static Fault checkCacheability(const RequestPtr &req)
Definition: tlb.cc:142
PowerISA::TLB::insert
void insert(Addr vaddr, PowerISA::PTE &pte)
Definition: tlb.cc:178
PowerISA::TLB::nlu
int nlu
Definition: tlb.hh:101
PowerISA::TLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override
Definition: tlb.cc:258
PowerISA::PTE::asid
uint8_t asid
Definition: pagetable.hh:53
str.hh
faults.hh
Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:124
cp
Definition: cprintf.cc:40
PowerISA::PTE::VPN
Addr VPN
Definition: pagetable.hh:50
PowerISA::TLB::translateData
Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write)
Definition: tlb.cc:232
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
PowerISA
Definition: decoder.cc:31
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
PowerISA::TLB::smallPages
int smallPages
Definition: tlb.hh:123
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
PowerISA::TLB::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const override
Do post-translation physical address finalization.
Definition: tlb.cc:266
process.hh
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
BaseTLB::Translation
Definition: tlb.hh:59
PowerISA::PTE::PFN1
Addr PFN1
Definition: pagetable.hh:65
PowerISA::TLB::table
PowerISA::PTE * table
Definition: tlb.hh:99
Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:114
inifile.hh
PowerISA::TLB::probeEntry
int probeEntry(Addr vpn, uint8_t) const
Definition: tlb.cc:114
PowerISA::TLB::lookup
PowerISA::PTE * lookup(Addr vpn, uint8_t asn) const
Definition: tlb.cc:77
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Serializable::ScopedCheckpointSection
Definition: serialize.hh:175
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:790
PowerISA::TLB::~TLB
virtual ~TLB()
Definition: tlb.cc:69
full_system.hh
PowerISA::TLB::index
PowerISA::PTE & index(bool advance=true)
Definition: tlb.cc:273
BaseTLB::Write
@ Write
Definition: tlb.hh:57
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
PowerISA::TLB
Definition: tlb.hh:93
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
PowerISA::TLB::Params
PowerTLBParams Params
Definition: tlb.hh:114
addr
ip6_addr_t addr
Definition: inet.hh:423
tlb.hh
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
PowerISA::TLB::getEntry
PowerISA::PTE * getEntry(unsigned) const
Definition: tlb.cc:106
trace.hh
PowerISA::TLB::flushAll
void flushAll() override
Remove all entries from the TLB.
Definition: tlb.cc:184
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
page_table.hh
CheckpointIn
Definition: serialize.hh:67
PowerISA::PTE::G
bool G
Definition: pagetable.hh:56
BaseTLB::Execute
@ Execute
Definition: tlb.hh:57
EmulationPageTable::translate
bool translate(Addr vaddr, Addr &paddr)
Translate function.
Definition: page_table.cc:140
PowerISA::PTE::serialize
void serialize(CheckpointOut &cp) const
Definition: pagetable.cc:40
csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:158
thread_context.hh
PowerISA::TLB::insertAt
void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
Definition: tlb.cc:154

Generated on Wed Sep 30 2020 14:01:59 for gem5 by doxygen 1.8.17