gem5  v20.1.0.0
pseudo_inst.hh
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40 
41 #ifndef __SIM_PSEUDO_INST_HH__
42 #define __SIM_PSEUDO_INST_HH__
43 
44 #include <gem5/asm/generic/m5ops.h>
45 
46 class ThreadContext;
47 
48 #include "arch/pseudo_inst.hh"
49 #include "arch/utility.hh"
50 #include "base/types.hh" // For Tick and Addr data types.
51 #include "debug/PseudoInst.hh"
52 #include "sim/guest_abi.hh"
53 
55 {
56  using State = int;
57 };
58 
59 namespace GuestABI
60 {
61 
62 template <>
63 struct Argument<PseudoInstABI, uint64_t>
64 {
65  static uint64_t
67  {
68  uint64_t result =
69  TheISA::getArgument(tc, state, sizeof(uint64_t), false);
70  state++;
71  return result;
72  }
73 };
74 
75 } // namespace GuestABI
76 
77 namespace PseudoInst
78 {
79 
80 static inline void
81 decodeAddrOffset(Addr offset, uint8_t &func)
82 {
83  func = bits(offset, 15, 8);
84 }
85 
86 void arm(ThreadContext *tc);
87 void quiesce(ThreadContext *tc);
88 void quiesceSkip(ThreadContext *tc);
89 void quiesceNs(ThreadContext *tc, uint64_t ns);
90 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
91 uint64_t quiesceTime(ThreadContext *tc);
92 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
93  uint64_t offset);
94 uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
95  uint64_t offset, Addr filenameAddr);
96 void loadsymbol(ThreadContext *xc);
97 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
98 uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
99 uint64_t rpns(ThreadContext *tc);
100 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
101 void m5exit(ThreadContext *tc, Tick delay);
102 void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
103 uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c,
104  uint64_t d, uint64_t e, uint64_t f);
105 void resetstats(ThreadContext *tc, Tick delay, Tick period);
106 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
107 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
108 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
109 void debugbreak(ThreadContext *tc);
110 void switchcpu(ThreadContext *tc);
111 void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
112 void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
113 void m5Syscall(ThreadContext *tc);
114 void togglesync(ThreadContext *tc);
115 
129 template <typename ABI, bool store_ret>
130 bool
131 pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
132 {
133  DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i)\n", func);
134 
135  result = 0;
136 
137  switch (func) {
138  case M5OP_ARM:
139  invokeSimcall<ABI>(tc, arm);
140  return true;
141 
142  case M5OP_QUIESCE:
143  invokeSimcall<ABI>(tc, quiesce);
144  return true;
145 
146  case M5OP_QUIESCE_NS:
147  invokeSimcall<ABI>(tc, quiesceNs);
148  return true;
149 
150  case M5OP_QUIESCE_CYCLE:
151  invokeSimcall<ABI>(tc, quiesceCycles);
152  return true;
153 
154  case M5OP_QUIESCE_TIME:
155  result = invokeSimcall<ABI, store_ret>(tc, quiesceTime);
156  return true;
157 
158  case M5OP_RPNS:
159  result = invokeSimcall<ABI, store_ret>(tc, rpns);
160  return true;
161 
162  case M5OP_WAKE_CPU:
163  invokeSimcall<ABI>(tc, wakeCPU);
164  return true;
165 
166  case M5OP_EXIT:
167  invokeSimcall<ABI>(tc, m5exit);
168  return true;
169 
170  case M5OP_FAIL:
171  invokeSimcall<ABI>(tc, m5fail);
172  return true;
173 
174  // M5OP_SUM is for sanity checking the gem5 op interface.
175  case M5OP_SUM:
176  result = invokeSimcall<ABI, store_ret>(tc, m5sum);
177  return true;
178 
179  case M5OP_INIT_PARAM:
180  result = invokeSimcall<ABI, store_ret>(tc, initParam);
181  return true;
182 
183  case M5OP_LOAD_SYMBOL:
184  invokeSimcall<ABI>(tc, loadsymbol);
185  return true;
186 
187  case M5OP_RESET_STATS:
188  invokeSimcall<ABI>(tc, resetstats);
189  return true;
190 
191  case M5OP_DUMP_STATS:
192  invokeSimcall<ABI>(tc, dumpstats);
193  return true;
194 
195  case M5OP_DUMP_RESET_STATS:
196  invokeSimcall<ABI>(tc, dumpresetstats);
197  return true;
198 
199  case M5OP_CHECKPOINT:
200  invokeSimcall<ABI>(tc, m5checkpoint);
201  return true;
202 
203  case M5OP_WRITE_FILE:
204  result = invokeSimcall<ABI, store_ret>(tc, writefile);
205  return true;
206 
207  case M5OP_READ_FILE:
208  result = invokeSimcall<ABI, store_ret>(tc, readfile);
209  return true;
210 
211  case M5OP_DEBUG_BREAK:
212  invokeSimcall<ABI>(tc, debugbreak);
213  return true;
214 
215  case M5OP_SWITCH_CPU:
216  invokeSimcall<ABI>(tc, switchcpu);
217  return true;
218 
219  case M5OP_ADD_SYMBOL:
220  invokeSimcall<ABI>(tc, addsymbol);
221  return true;
222 
223  case M5OP_PANIC:
224  panic("M5 panic instruction called at %s\n", tc->pcState());
225 
226  case M5OP_WORK_BEGIN:
227  invokeSimcall<ABI>(tc, workbegin);
228  return true;
229 
230  case M5OP_WORK_END:
231  invokeSimcall<ABI>(tc, workend);
232  return true;
233 
234  case M5OP_RESERVED1:
235  case M5OP_RESERVED2:
236  case M5OP_RESERVED3:
237  case M5OP_RESERVED4:
238  case M5OP_RESERVED5:
239  warn("Unimplemented m5 op (%#x)\n", func);
240  return false;
241 
242  /* SE mode functions */
243  case M5OP_SE_SYSCALL:
244  invokeSimcall<ABI>(tc, m5Syscall);
245  return true;
246 
247  case M5OP_SE_PAGE_FAULT:
248  invokeSimcall<ABI>(tc, TheISA::m5PageFault);
249  return true;
250 
251  /* dist-gem5 functions */
252  case M5OP_DIST_TOGGLE_SYNC:
253  invokeSimcall<ABI>(tc, togglesync);
254  return true;
255 
256  default:
257  warn("Unhandled m5 op: %#x\n", func);
258  return false;
259  }
260 }
261 
262 template <typename ABI, bool store_ret=false>
263 bool
264 pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
265 {
266  return pseudoInstWork<ABI, store_ret>(tc, func, result);
267 }
268 
269 template <typename ABI, bool store_ret=true>
270 bool
271 pseudoInst(ThreadContext *tc, uint8_t func)
272 {
273  uint64_t result;
274  return pseudoInstWork<ABI, store_ret>(tc, func, result);
275 }
276 
277 } // namespace PseudoInst
278 
279 #endif // __SIM_PSEUDO_INST_HH__
PseudoInst::debugbreak
void debugbreak(ThreadContext *tc)
Definition: pseudo_inst.cc:461
ArmISA::ns
Bitfield< 0 > ns
Definition: miscregs_types.hh:328
GuestABI::Argument< PseudoInstABI, uint64_t >::get
static uint64_t get(ThreadContext *tc, PseudoInstABI::State &state)
Definition: pseudo_inst.hh:66
warn
#define warn(...)
Definition: logging.hh:239
PseudoInst::workbegin
void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid)
Definition: pseudo_inst.cc:498
MipsISA::cpuid
Bitfield< 28, 21 > cpuid
Definition: dt_constants.hh:92
ArmISA::getArgument
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
Definition: utility.cc:57
PseudoInstABI::State
int State
Definition: pseudo_inst.hh:56
PseudoInst::m5Syscall
void m5Syscall(ThreadContext *tc)
Definition: pseudo_inst.cc:479
PseudoInst::m5exit
void m5exit(ThreadContext *tc, Tick delay)
Definition: pseudo_inst.cc:183
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
PseudoInst::rpns
uint64_t rpns(ThreadContext *tc)
Definition: pseudo_inst.cc:159
PseudoInst::decodeAddrOffset
static void decodeAddrOffset(Addr offset, uint8_t &func)
Definition: pseudo_inst.hh:81
PseudoInst::quiesceTime
uint64_t quiesceTime(ThreadContext *tc)
Definition: pseudo_inst.cc:150
GenericISA::m5PageFault
void m5PageFault(ThreadContext *tc)
Definition: pseudo_inst.cc:38
PseudoInst::pseudoInst
bool pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
Definition: pseudo_inst.hh:264
PseudoInstABI
Definition: pseudo_inst.hh:54
PseudoInst
Definition: pseudo_inst.cc:76
PseudoInst::dumpstats
void dumpstats(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:332
PseudoInst::readfile
uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
Definition: pseudo_inst.cc:374
PseudoInst::switchcpu
void switchcpu(ThreadContext *tc)
Definition: pseudo_inst.cc:468
PseudoInst::togglesync
void togglesync(ThreadContext *tc)
Definition: pseudo_inst.cc:486
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
GuestABI
Definition: aapcs32.hh:66
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
PseudoInst::initParam
uint64_t initParam(ThreadContext *tc, uint64_t key_str1, uint64_t key_str2)
Definition: pseudo_inst.cc:284
PseudoInst::workend
void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid)
Definition: pseudo_inst.cc:561
ArmISA::d
Bitfield< 9 > d
Definition: miscregs_types.hh:60
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
PseudoInst::dumpresetstats
void dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:346
GuestABI::Argument
Definition: definition.hh:93
PseudoInst::quiesceSkip
void quiesceSkip(ThreadContext *tc)
Definition: pseudo_inst.cc:129
PseudoInst::m5sum
uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c, uint64_t d, uint64_t e, uint64_t f)
Definition: pseudo_inst.cc:194
PseudoInst::m5fail
void m5fail(ThreadContext *tc, Tick delay, uint64_t code)
Definition: pseudo_inst.cc:203
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
PseudoInst::writefile
uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset, Addr filename_addr)
Definition: pseudo_inst.cc:416
ArmISA::e
Bitfield< 9 > e
Definition: miscregs_types.hh:61
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
PseudoInst::quiesce
void quiesce(ThreadContext *tc)
Definition: pseudo_inst.cc:122
PseudoInst::quiesceCycles
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
Definition: pseudo_inst.cc:143
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
types.hh
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
guest_abi.hh
addr
ip6_addr_t addr
Definition: inet.hh:423
PseudoInst::wakeCPU
void wakeCPU(ThreadContext *tc, uint64_t cpuid)
Definition: pseudo_inst.cc:166
PseudoInst::arm
void arm(ThreadContext *tc)
Definition: pseudo_inst.cc:110
PseudoInst::m5checkpoint
void m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:360
ArmISA::c
Bitfield< 29 > c
Definition: miscregs_types.hh:50
PseudoInst::quiesceNs
void quiesceNs(ThreadContext *tc, uint64_t ns)
Definition: pseudo_inst.cc:136
PseudoInst::addsymbol
void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
Definition: pseudo_inst.cc:265
PseudoInst::loadsymbol
void loadsymbol(ThreadContext *tc)
Definition: pseudo_inst.cc:211
PseudoInst::resetstats
void resetstats(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:318
PseudoInst::pseudoInstWork
bool pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
Execute a decoded M5 pseudo instruction.
Definition: pseudo_inst.hh:131
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::f
Bitfield< 6 > f
Definition: miscregs_types.hh:64
ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:153
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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