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41 #ifndef __SIM_PSEUDO_INST_HH__
42 #define __SIM_PSEUDO_INST_HH__
44 #include <gem5/asm/generic/m5ops.h>
48 #include "arch/pseudo_inst.hh"
49 #include "arch/utility.hh"
51 #include "debug/PseudoInst.hh"
104 uint64_t
d, uint64_t
e, uint64_t
f);
129 template <
typename ABI,
bool store_ret>
139 invokeSimcall<ABI>(tc,
arm);
143 invokeSimcall<ABI>(tc,
quiesce);
146 case M5OP_QUIESCE_NS:
150 case M5OP_QUIESCE_CYCLE:
154 case M5OP_QUIESCE_TIME:
155 result = invokeSimcall<ABI, store_ret>(tc,
quiesceTime);
159 result = invokeSimcall<ABI, store_ret>(tc,
rpns);
163 invokeSimcall<ABI>(tc,
wakeCPU);
167 invokeSimcall<ABI>(tc,
m5exit);
171 invokeSimcall<ABI>(tc,
m5fail);
176 result = invokeSimcall<ABI, store_ret>(tc,
m5sum);
179 case M5OP_INIT_PARAM:
180 result = invokeSimcall<ABI, store_ret>(tc,
initParam);
183 case M5OP_LOAD_SYMBOL:
187 case M5OP_RESET_STATS:
191 case M5OP_DUMP_STATS:
195 case M5OP_DUMP_RESET_STATS:
199 case M5OP_CHECKPOINT:
203 case M5OP_WRITE_FILE:
204 result = invokeSimcall<ABI, store_ret>(tc,
writefile);
208 result = invokeSimcall<ABI, store_ret>(tc,
readfile);
211 case M5OP_DEBUG_BREAK:
215 case M5OP_SWITCH_CPU:
219 case M5OP_ADD_SYMBOL:
224 panic(
"M5 panic instruction called at %s\n", tc->
pcState());
226 case M5OP_WORK_BEGIN:
231 invokeSimcall<ABI>(tc,
workend);
239 warn(
"Unimplemented m5 op (%#x)\n", func);
243 case M5OP_SE_SYSCALL:
247 case M5OP_SE_PAGE_FAULT:
252 case M5OP_DIST_TOGGLE_SYNC:
257 warn(
"Unhandled m5 op: %#x\n", func);
262 template <
typename ABI,
bool store_ret=false>
266 return pseudoInstWork<ABI, store_ret>(tc, func, result);
269 template <
typename ABI,
bool store_ret=true>
274 return pseudoInstWork<ABI, store_ret>(tc, func, result);
279 #endif // __SIM_PSEUDO_INST_HH__
void debugbreak(ThreadContext *tc)
static uint64_t get(ThreadContext *tc, PseudoInstABI::State &state)
void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid)
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
void m5Syscall(ThreadContext *tc)
void m5exit(ThreadContext *tc, Tick delay)
uint64_t Tick
Tick count type.
uint64_t rpns(ThreadContext *tc)
static void decodeAddrOffset(Addr offset, uint8_t &func)
uint64_t quiesceTime(ThreadContext *tc)
void m5PageFault(ThreadContext *tc)
bool pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
void dumpstats(ThreadContext *tc, Tick delay, Tick period)
uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
void switchcpu(ThreadContext *tc)
void togglesync(ThreadContext *tc)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
uint64_t initParam(ThreadContext *tc, uint64_t key_str1, uint64_t key_str2)
void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid)
void dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
void quiesceSkip(ThreadContext *tc)
uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c, uint64_t d, uint64_t e, uint64_t f)
void m5fail(ThreadContext *tc, Tick delay, uint64_t code)
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset, Addr filename_addr)
virtual TheISA::PCState pcState() const =0
void quiesce(ThreadContext *tc)
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
void wakeCPU(ThreadContext *tc, uint64_t cpuid)
void arm(ThreadContext *tc)
void m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
void quiesceNs(ThreadContext *tc, uint64_t ns)
void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
void loadsymbol(ThreadContext *tc)
void resetstats(ThreadContext *tc, Tick delay, Tick period)
bool pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
Execute a decoded M5 pseudo instruction.
#define panic(...)
This implements a cprintf based panic() function.
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
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