gem5  v20.1.0.0
simple.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include "dev/serial/simple.hh"
39 
40 #include "mem/packet.hh"
41 #include "mem/packet_access.hh"
42 #include "params/SimpleUart.hh"
43 #include "sim/sim_exit.hh"
44 
45 SimpleUart::SimpleUart(const SimpleUartParams *p)
46  : Uart(p, p->pio_size), byteOrder(p->byte_order), endOnEOT(p->end_on_eot)
47 {
48 }
49 
50 Tick
52 {
53  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
54 
55  uint64_t data = 0;
56 
57  if (device->dataAvailable())
58  data = device->readData();
59 
60  pkt->setUintX(data, byteOrder);
61 
62  pkt->makeAtomicResponse();
63  return pioDelay;
64 }
65 
66 Tick
68 {
69 
70  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
71 
72  uint8_t data = (uint8_t)pkt->getUintX(byteOrder);
73  if (data == 0x04 && endOnEOT)
74  exitSimLoop("UART received EOT", 0);
75 
77 
78  pkt->makeAtomicResponse();
79  return pioDelay;
80 }
81 
82 SimpleUart *
83 SimpleUartParams::create()
84 {
85  return new SimpleUart(this);
86 }
Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1016
BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:154
SimpleUart::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: simple.cc:51
data
const char data[]
Definition: circlebuf.test.cc:42
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
ArmISA::byteOrder
ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:449
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
SimpleUart::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: simple.cc:67
sim_exit.hh
packet.hh
SimpleUart::endOnEOT
const bool endOnEOT
Definition: simple.hh:64
Uart
Definition: uart.hh:46
SimpleUart::byteOrder
const ByteOrder byteOrder
Definition: simple.hh:59
Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:350
SerialDevice::dataAvailable
virtual bool dataAvailable() const =0
Check if there is pending data from the serial device.
Uart::device
SerialDevice * device
Definition: uart.hh:51
exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
Packet::setUintX
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
Definition: packet.cc:367
BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:157
SerialDevice::readData
virtual uint8_t readData()=0
Read a character from the device.
packet_access.hh
SimpleUart::SimpleUart
SimpleUart(const SimpleUartParams *p)
Definition: simple.cc:45
simple.hh
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
SimpleUart
Definition: simple.hh:46
BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:160
SerialDevice::writeData
virtual void writeData(uint8_t c)=0
Transmit a character from the host interface to the device.
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323

Generated on Wed Sep 30 2020 14:02:11 for gem5 by doxygen 1.8.17