utility.hh

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/*
 * Copyright (c) 2003-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_SPARC_UTILITY_HH__
#define __ARCH_SPARC_UTILITY_HH__
 
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/tlb.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
 
namespace SparcISA
{
 
inline PCState
buildRetPC(const PCState &curPC, const PCState &callPC)
{
    PCState ret = callPC;
    ret.uEnd();
    ret.pc(curPC.npc());
    return ret;
}
 
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 
static inline bool
inUserMode(ThreadContext *tc)
{
    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
    return !(pstate.priv || hpstate.hpriv);
}
 
void copyRegs(ThreadContext *src, ThreadContext *dest);
 
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
inline void
advancePC(PCState &pc, const StaticInstPtr &inst)
{
    inst->advancePC(pc);
}
 
inline uint64_t
getExecutingAsid(ThreadContext *tc)
{
    return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
}
 
} // namespace SparcISA
 
#endif