gem5  v20.1.0.0
sve.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2017-2019 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 // TODO: add support for suffixes of register specifiers in disasm strings.
39 
40 #include "arch/arm/insts/sve.hh"
41 
42 namespace ArmISA {
43 
44 const char*
46 {
47  switch (pt) {
48  case SvePredType::MERGE:
49  return "m";
50  case SvePredType::ZERO:
51  return "z";
52  default:
53  return "";
54  }
55 }
56 
57 std::string
59  const Loader::SymbolTable *symtab) const
60 {
61  std::stringstream ss;
62  printMnemonic(ss, "", false);
64  ccprintf(ss, ", ");
66  ccprintf(ss, ", ");
68  return ss.str();
69 }
70 
71 std::string
73  Addr pc, const Loader::SymbolTable *symtab) const
74 {
75  std::stringstream ss;
76  printMnemonic(ss, "", false);
77  if (destIsVec) {
78  printVecReg(ss, dest, true);
79  } else {
81  }
82  ccprintf(ss, ", ");
83  uint8_t opWidth = 64;
85  ccprintf(ss, ", ");
86  if (srcIs32b)
87  opWidth = 32;
88  printIntReg(ss, dest, opWidth);
89  return ss.str();
90 }
91 
92 std::string
94  Addr pc, const Loader::SymbolTable *symtab) const
95 {
96  std::stringstream ss;
97  printMnemonic(ss, "", false);
98  printVecReg(ss, dest, true);
99  ccprintf(ss, ", #%d, #%d", imm1, imm2);
100  return ss.str();
101 }
102 
103 std::string
105  Addr pc, const Loader::SymbolTable *symtab) const
106 {
107  std::stringstream ss;
108  printMnemonic(ss, "", false);
109  printVecReg(ss, dest, true);
110  ccprintf(ss, ", #%d, ", imm1);
111  printIntReg(ss, op2);
112  return ss.str();
113 }
114 
115 std::string
117  Addr pc, const Loader::SymbolTable *symtab) const
118 {
119  std::stringstream ss;
120  printMnemonic(ss, "", false);
121  printVecReg(ss, dest, true);
122  ccprintf(ss, ", ");
123  printIntReg(ss, op1);
124  ccprintf(ss, ", #%d", imm2);
125  return ss.str();
126 }
127 
128 std::string
130  Addr pc, const Loader::SymbolTable *symtab) const
131 {
132  std::stringstream ss;
133  printMnemonic(ss, "", false);
134  printVecReg(ss, dest, true);
135  ccprintf(ss, ", ");
136  printIntReg(ss, op1);
137  ccprintf(ss, ", ");
138  printIntReg(ss, op2);
139  return ss.str();
140 }
141 
142 std::string
144  Addr pc, const Loader::SymbolTable *symtab) const
145 {
146  std::stringstream ss;
147  printMnemonic(ss, "", false);
149  ccprintf(ss, ", ");
150  uint8_t opWidth;
151  if (srcIs32b)
152  opWidth = 32;
153  else
154  opWidth = 64;
155  printIntReg(ss, op1, opWidth);
156  ccprintf(ss, ", ");
157  printIntReg(ss, op2, opWidth);
158  return ss.str();
159 }
160 
161 std::string
163  Addr pc, const Loader::SymbolTable *symtab) const
164 {
165  std::stringstream ss;
166  printMnemonic(ss, "", false);
167  printIntReg(ss, op1);
168  ccprintf(ss, ", ");
169  printIntReg(ss, op2);
170  return ss.str();
171 }
172 
173 std::string
175  Addr pc, const Loader::SymbolTable *symtab) const
176 {
177  std::stringstream ss;
178  printMnemonic(ss, "", false);
179  printVecReg(ss, dest, true);
180  ccprintf(ss, ", ");
182  ccprintf(ss, "/m, ");
183  printVecReg(ss, op1, true);
184  return ss.str();
185 }
186 
187 std::string
189  Addr pc, const Loader::SymbolTable *symtab) const
190 {
191  std::stringstream ss;
192  printMnemonic(ss, "", false);
193  printVecReg(ss, dest, true);
194  ccprintf(ss, ", ");
195  printVecReg(ss, op1, true);
196  return ss.str();
197 }
198 
199 std::string
201  Addr pc, const Loader::SymbolTable *symtab) const
202 {
203  std::stringstream ss;
204  printMnemonic(ss, "", false);
205  printVecReg(ss, dest, true);
206  ccprintf(ss, ", #");
207  ss << imm;
208  return ss.str();
209 }
210 
211 std::string
213  Addr pc, const Loader::SymbolTable *symtab) const
214 {
215  std::stringstream ss;
216  printMnemonic(ss, "", false);
217  printVecReg(ss, dest, true);
218  ccprintf(ss, ", ");
220  ccprintf(ss, (isMerging ? "/m" : "/z"));
221  ccprintf(ss, ", #");
222  ss << imm;
223  return ss.str();
224 }
225 
226 std::string
228  Addr pc, const Loader::SymbolTable *symtab) const
229 {
230  std::stringstream ss;
231  printMnemonic(ss, "", false);
232  printVecReg(ss, dest, true);
233  ccprintf(ss, ", ");
235  ccprintf(ss, ", #");
236  ss << imm;
237  return ss.str();
238 }
239 
240 std::string
242  Addr pc, const Loader::SymbolTable *symtab) const
243 {
244  std::stringstream ss;
245  printMnemonic(ss, "", false);
246  printVecReg(ss, dest, true);
247  ccprintf(ss, ", ");
249  ccprintf(ss, "/m, ");
250  printVecReg(ss, dest, true);
251  ccprintf(ss, ", #");
252  ss << imm;
253  return ss.str();
254 }
255 
256 std::string
258  Addr pc, const Loader::SymbolTable *symtab) const
259 {
260  std::stringstream ss;
261  printMnemonic(ss, "", false);
262  printVecReg(ss, dest, true);
263  ccprintf(ss, ", ");
264  printVecReg(ss, dest, true);
265  ccprintf(ss, ", #");
266  ss << imm;
267  return ss.str();
268 }
269 
270 std::string
272  Addr pc, const Loader::SymbolTable *symtab) const
273 {
274  std::stringstream ss;
275  printMnemonic(ss, "", false);
276  printVecReg(ss, dest, true);
277  ccprintf(ss, ", ");
279  ccprintf(ss, "/m, ");
280  printVecReg(ss, dest, true);
281  ccprintf(ss, ", ");
282  printVecReg(ss, op2, true);
283  return ss.str();
284 }
285 
286 std::string
288  Addr pc, const Loader::SymbolTable *symtab) const
289 {
290  std::stringstream ss;
291  printMnemonic(ss, "", false);
292  printVecReg(ss, dest, true);
293  ccprintf(ss, ", ");
297  }
298  ccprintf(ss, ", ");
299  printVecReg(ss, op1, true);
300  ccprintf(ss, ", ");
301  printVecReg(ss, op2, true);
302  return ss.str();
303 }
304 
305 std::string
307  Addr pc, const Loader::SymbolTable *symtab) const
308 {
309  std::stringstream ss;
310  printMnemonic(ss, "", false);
311  printVecReg(ss, dest, true);
312  ccprintf(ss, ", ");
313  printVecReg(ss, op1, true);
314  ccprintf(ss, ", ");
315  printVecReg(ss, op2, true);
316  return ss.str();
317 }
318 
319 std::string
321  Addr pc, const Loader::SymbolTable *symtab) const
322 {
323  std::stringstream ss;
324  printMnemonic(ss, "", false);
325  printVecReg(ss, dest, true);
326  ccprintf(ss, ", ");
327  printVecReg(ss, op1, true);
328  ccprintf(ss, ", ");
329  printVecReg(ss, op2, true);
330  ccprintf(ss, "[");
331  ss << (uint64_t)index;
332  ccprintf(ss, "]");
333  return ss.str();
334 }
335 
336 std::string
338  Addr pc, const Loader::SymbolTable *symtab) const
339 {
340  std::stringstream ss;
341  printMnemonic(ss, "", false);
342  printVecReg(ss, dest, true);
343  ccprintf(ss, ", ");
345  if (isSel) {
346  ccprintf(ss, ", ");
347  } else {
348  ccprintf(ss, "/z, ");
349  }
351  ccprintf(ss, ", ");
353  return ss.str();
354 }
355 
356 std::string
358  Addr pc, const Loader::SymbolTable *symtab) const
359 {
360  std::stringstream ss;
361  printMnemonic(ss, "", false);
363  ccprintf(ss, ", ");
365  ccprintf(ss, ", ");
367  return ss.str();
368 }
369 
370 std::string
372 {
373  std::stringstream ss;
374  printMnemonic(ss, "", false);
376  ccprintf(ss, ", ");
378  ccprintf(ss, "/z, ");
379  printVecReg(ss, op1, true);
380  ccprintf(ss, ", ");
381  printVecReg(ss, op2, true);
382  return ss.str();
383 }
384 
385 std::string
387  Addr pc, const Loader::SymbolTable *symtab) const
388 {
389  std::stringstream ss;
390  printMnemonic(ss, "", false);
392  ccprintf(ss, ", ");
394  ccprintf(ss, "/z, ");
395  printVecReg(ss, op1, true);
396  ccprintf(ss, ", #");
397  ss << imm;
398  return ss.str();
399 }
400 
401 std::string
403  Addr pc, const Loader::SymbolTable *symtab) const
404 {
405  std::stringstream ss;
406  printMnemonic(ss, "", false);
407  printVecReg(ss, dest, true);
408  ccprintf(ss, ", ");
410  ccprintf(ss, "/m, ");
411  printVecReg(ss, op1, true);
412  ccprintf(ss, ", ");
413  printVecReg(ss, op2, true);
414  return ss.str();
415 }
416 
417 std::string
419  Addr pc, const Loader::SymbolTable *symtab) const
420 {
421  std::stringstream ss;
422  printMnemonic(ss, "", false);
423  printVecReg(ss, dest, true);
424  ccprintf(ss, ", ");
425  printVecReg(ss, dest, true);
426  ccprintf(ss, ", ");
427  printVecReg(ss, op2, true);
428  ccprintf(ss, ", #");
429  ss << imm;
430  return ss.str();
431 }
432 
433 std::string
435  Addr pc, const Loader::SymbolTable *symtab) const
436 {
437  std::stringstream ss;
438  printMnemonic(ss, "", false);
440  ccprintf(ss, ", ");
442  ccprintf(ss, ", ");
443  printVecReg(ss, op1, true);
444  return ss.str();
445 }
446 
447 std::string
449  Addr pc, const Loader::SymbolTable *symtab) const
450 {
451  std::stringstream ss;
452  printMnemonic(ss, "", false);
454  ccprintf(ss, ", ");
456  ccprintf(ss, ", ");
458  ccprintf(ss, ", ");
459  printVecReg(ss, op1, true);
460  return ss.str();
461 }
462 
463 std::string
465  Addr pc, const Loader::SymbolTable *symtab) const
466 {
467  std::stringstream ss;
468  printMnemonic(ss, "", false);
470  if (imm != 0x1f) {
471  ccprintf(ss, ", ");
473  }
474  return ss.str();
475 }
476 
477 std::string
479  Addr pc, const Loader::SymbolTable *symtab) const
480 {
481  std::stringstream ss;
482  printMnemonic(ss, "", false);
484  ccprintf(ss, ", ");
486  ccprintf(ss, "/z, ");
487  printVecReg(ss, op1, true);
488  ccprintf(ss, ", ");
489  if (op2IsWide) {
490  printVecReg(ss, op2, true);
491  } else {
492  printVecReg(ss, op2, true);
493  }
494  return ss.str();
495 }
496 
497 std::string
499  Addr pc, const Loader::SymbolTable *symtab) const
500 {
501  std::stringstream ss;
502  printMnemonic(ss, "", false);
504  ccprintf(ss, "/z, ");
506  ccprintf(ss, ", ");
507  printVecReg(ss, op1, true);
508  ccprintf(ss, ", #");
509  ss << imm;
510  return ss.str();
511 }
512 
513 std::string
515 {
516  std::stringstream ss;
517  printMnemonic(ss, "", false);
518  printVecReg(ss, dest, true);
519  ccprintf(ss, ", [");
520  printVecReg(ss, op1, true);
521  ccprintf(ss, ", ");
522  printVecReg(ss, op2, true);
524  ccprintf(ss, ", sxtw");
526  ccprintf(ss, ", uxtw");
527  } else if (mult != 1) {
528  ccprintf(ss, ", lsl");
529  }
530  if (mult != 1) {
531  ss << __builtin_ctz(mult);
532  }
533  ccprintf(ss, "]");
534  return ss.str();
535 }
536 
537 std::string
539  Addr pc, const Loader::SymbolTable *symtab) const
540 {
541  static const char suffix[9] =
542  {'\0', 'b', 'h', '\0', 'w', '\0', '\0', '\0', 'd'};
543  std::stringstream ss;
544  ss << " " << mnemonic << suffix[esize] << " ";
545  if (dstIsVec) {
546  printVecReg(ss, dest, true);
547  } else {
548  if (dstIs32b) {
549  printIntReg(ss, dest, 32);
550  } else {
551  printIntReg(ss, dest, 64);
552  }
553  }
554  if (pattern != 0x1f) {
555  ccprintf(ss, ", ");
557  if (imm != 1) {
558  ccprintf(ss, ", mul #");
559  ss << std::to_string(imm);
560  }
561  }
562  return ss.str();
563 }
564 
565 std::string
567  Addr pc, const Loader::SymbolTable *symtab) const
568 {
569  std::stringstream ss;
570  printMnemonic(ss, "", false);
572  ccprintf(ss, ", ");
574  ccprintf(ss, isMerging ? "/m, " : "/z, ");
576  return ss.str();
577 }
578 
579 std::string
581  Addr pc, const Loader::SymbolTable *symtab) const
582 {
583  std::stringstream ss;
584  printMnemonic(ss, "", false);
586  ccprintf(ss, ", ");
588  ccprintf(ss, "/z, ");
590  ccprintf(ss, ", ");
592  return ss.str();
593 }
594 
595 std::string
597  Addr pc, const Loader::SymbolTable *symtab) const
598 {
599  std::stringstream ss;
600  printMnemonic(ss, "", false);
601  if (scalar)
603  else if (simdFp)
605  else
606  printVecReg(ss, dest, true);
607  ccprintf(ss, ", ");
609  if (conditional) {
610  ccprintf(ss, ", ");
611  if (scalar)
613  else
614  printVecReg(ss, dest, true);
615  }
616  ccprintf(ss, ", ");
617  printVecReg(ss, op1, true);
618  return ss.str();
619 }
620 
621 std::string
623  Addr pc, const Loader::SymbolTable *symtab) const
624 {
625  std::stringstream ss;
626  printMnemonic(ss, "", false);
628  ccprintf(ss, ", ");
630  ccprintf(ss, ", ");
632  return ss.str();
633 }
634 
635 std::string
637 {
638  std::stringstream ss;
639  printMnemonic(ss, "", false);
640  printVecReg(ss, dest, true);
641  ccprintf(ss, ", { ");
642  printVecReg(ss, op1, true);
643  ccprintf(ss, " }, ");
644  printVecReg(ss, op2, true);
645  return ss.str();
646 }
647 
648 std::string
650  Addr pc, const Loader::SymbolTable *symtab) const
651 {
652  std::stringstream ss;
653  printMnemonic(ss, "", false);
655  ccprintf(ss, ", ");
657  return ss.str();
658 }
659 
660 std::string
662  Addr pc, const Loader::SymbolTable *symtab) const
663 {
664  std::stringstream ss;
665  printMnemonic(ss, "", false);
667  ccprintf(ss, ", ");
669  return ss.str();
670 }
671 
672 std::string
674  Addr pc, const Loader::SymbolTable *symtab) const
675 {
676  std::stringstream ss;
677  printMnemonic(ss, "", false);
679  return ss.str();
680 }
681 
682 std::string
684  Addr pc, const Loader::SymbolTable *symtab) const
685 {
686  std::stringstream ss;
687  printMnemonic(ss, "", false);
689  ccprintf(ss, ", ");
691  ccprintf(ss, "/z, ");
692  return ss.str();
693 }
694 
695 std::string
697  Addr pc, const Loader::SymbolTable *symtab) const
698 {
699  std::stringstream ss;
700  printMnemonic(ss, "", false);
702  return ss.str();
703 }
704 
705 std::string
707  Addr pc, const Loader::SymbolTable *symtab) const
708 {
709  std::stringstream ss;
710  printMnemonic(ss, "", false);
711  return ss.str();
712 }
713 
714 std::string
716  Addr pc, const Loader::SymbolTable *symtab) const
717 {
718  std::stringstream ss;
719  printMnemonic(ss, "", false);
720  printVecReg(ss, dest, true);
721  ccprintf(ss, ", ");
722  printVecReg(ss, dest, true);
723  ccprintf(ss, ", ");
724  printVecReg(ss, op1, true);
725  ccprintf(ss, ", #");
726  ss << imm;
727  return ss.str();
728 }
729 
730 std::string
732  Addr pc, const Loader::SymbolTable *symtab) const
733 {
734  std::stringstream ss;
735  printMnemonic(ss, "", false);
736  printVecReg(ss, dest, true);
737  ccprintf(ss, ", ");
738  printVecReg(ss, op1, true);
739  ccprintf(ss, "[");
740  ss << imm;
741  ccprintf(ss, "]");
742  return ss.str();
743 }
744 
745 std::string
747  Addr pc, const Loader::SymbolTable *symtab) const
748 {
749  std::stringstream ss;
750  printMnemonic(ss, "", false);
751  printVecReg(ss, dest, true);
752  ccprintf(ss, ", ");
753  if (simdFp) {
754  printFloatReg(ss, op1);
755  } else {
756  printIntReg(ss, op1);
757  }
758  return ss.str();
759 }
760 
761 std::string
763  Addr pc, const Loader::SymbolTable *symtab) const
764 {
765  std::stringstream ss;
766  printMnemonic(ss, "", false);
767  printVecReg(ss, dest, true);
768  ccprintf(ss, ", ");
769  printVecReg(ss, op1, true);
770  ccprintf(ss, ", ");
771  printVecReg(ss, op2, true);
772  ccprintf(ss, "[");
773  ccprintf(ss, "%lu", imm);
774  ccprintf(ss, "]");
775  return ss.str();
776 }
777 
778 std::string
780  Addr pc, const Loader::SymbolTable *symtab) const
781 {
782  std::stringstream ss;
783  printMnemonic(ss, "", false);
784  printVecReg(ss, dest, true);
785  ccprintf(ss, ", ");
786  printVecReg(ss, op1, true);
787  ccprintf(ss, ", ");
788  printVecReg(ss, op2, true);
789  return ss.str();
790 }
791 
792 std::string
794  Addr pc, const Loader::SymbolTable *symtab) const
795 {
796  std::stringstream ss;
797  printMnemonic(ss, "", false);
799  ccprintf(ss, ", ");
801  ccprintf(ss, "/m, ");
803  ccprintf(ss, ", ");
805  ccprintf(ss, ", #");
806  const char* rotstr[4] = {"0", "90", "180", "270"};
807  ccprintf(ss, rotstr[rot]);
808 
809  return ss.str();
810 }
811 
812 std::string
814  Addr pc, const Loader::SymbolTable *symtab) const
815 {
816  std::stringstream ss;
817  printMnemonic(ss, "", false);
819  ccprintf(ss, ", ");
821  ccprintf(ss, ", ");
823  ccprintf(ss, "[");
824  ss << imm;
825  ccprintf(ss, "], #");
826  const char* rotstr[4] = {"0", "90", "180", "270"};
827  ccprintf(ss, rotstr[rot]);
828  return ss.str();
829 }
830 
831 std::string
833 {
834  switch (imm) {
835  case 0x0:
836  return "POW2";
837  case 0x1:
838  case 0x2:
839  case 0x3:
840  case 0x4:
841  case 0x5:
842  case 0x6:
843  case 0x7:
844  return "VL" + std::to_string(imm);
845  case 0x8:
846  case 0x9:
847  case 0xa:
848  case 0xb:
849  case 0xc:
850  case 0xd:
851  return "VL" + std::to_string(1 << ((imm & 0x7) + 3));
852  case 0x1d:
853  return "MUL4";
854  case 0x1e:
855  return "MUL3";
856  case 0x1f:
857  return "ALL";
858  default:
859  return "#" + std::to_string(imm);
860  }
861 }
862 
863 unsigned int
864 sveDecodePredCount(uint8_t imm, unsigned int num_elems)
865 {
866  assert(num_elems > 0);
867 
868  switch (imm) {
869  case 0x0:
870  // POW2
871  return 1 << (31 - __builtin_clz((uint32_t) num_elems));
872  case 0x1:
873  case 0x2:
874  case 0x3:
875  case 0x4:
876  case 0x5:
877  case 0x6:
878  case 0x7:
879  // VL1, VL2, VL3, VL4, VL5, VL6, VL7
880  return (num_elems >= imm) ? imm : 0;
881  case 0x8:
882  case 0x9:
883  case 0xa:
884  case 0xb:
885  case 0xc:
886  case 0xd:
887  // VL8, VL16, VL32, VL64, VL128, VL256
888  {
889  unsigned int pcount = 1 << ((imm & 0x7) + 3);
890  return (num_elems >= pcount) ? pcount : 0;
891  }
892  case 0x1d:
893  // MUL4
894  return num_elems - (num_elems % 4);
895  case 0x1e:
896  // MUL3
897  return num_elems - (num_elems % 3);
898  case 0x1f:
899  // ALL
900  return num_elems;
901  default:
902  return 0;
903  }
904 }
905 
906 uint64_t
907 sveExpandFpImmAddSub(uint8_t imm, uint8_t size)
908 {
909  static constexpr uint16_t fpOne16 = 0x3c00;
910  static constexpr uint16_t fpPointFive16 = 0x3800;
911  static constexpr uint32_t fpOne32 = 0x3f800000;
912  static constexpr uint32_t fpPointFive32 = 0x3f000000;
913  static constexpr uint64_t fpOne64 = 0x3ff0000000000000;
914  static constexpr uint64_t fpPointFive64 = 0x3fe0000000000000;
915 
916  switch (size) {
917  case 0x1:
918  return imm ? fpOne16 : fpPointFive16;
919  case 0x2:
920  return imm ? fpOne32 : fpPointFive32;
921  case 0x3:
922  return imm ? fpOne64 : fpPointFive64;
923  default:
924  panic("Unsupported size");
925  }
926 }
927 
928 uint64_t
929 sveExpandFpImmMaxMin(uint8_t imm, uint8_t size)
930 {
931  static constexpr uint16_t fpOne16 = 0x3c00;
932  static constexpr uint32_t fpOne32 = 0x3f800000;
933  static constexpr uint64_t fpOne64 = 0x3ff0000000000000;
934 
935  switch (size) {
936  case 0x1:
937  return imm ? fpOne16 : 0x0;
938  case 0x2:
939  return imm ? fpOne32 : 0x0;
940  case 0x3:
941  return imm ? fpOne64 : 0x0;
942  default:
943  panic("Unsupported size");
944  }
945 }
946 
947 uint64_t
948 sveExpandFpImmMul(uint8_t imm, uint8_t size)
949 {
950  static constexpr uint16_t fpTwo16 = 0x4000;
951  static constexpr uint16_t fpPointFive16 = 0x3800;
952  static constexpr uint32_t fpTwo32 = 0x40000000;
953  static constexpr uint32_t fpPointFive32 = 0x3f000000;
954  static constexpr uint64_t fpTwo64 = 0x4000000000000000;
955  static constexpr uint64_t fpPointFive64 = 0x3fe0000000000000;
956 
957  switch (size) {
958  case 0x1:
959  return imm ? fpTwo16 : fpPointFive16;
960  case 0x2:
961  return imm ? fpTwo32 : fpPointFive32;
962  case 0x3:
963  return imm ? fpTwo64 : fpPointFive64;
964  default:
965  panic("Unsupported size");
966  }
967 }
968 
969 } // namespace ArmISA
ArmISA::SvePtrueOp::imm
uint8_t imm
Definition: sve.hh:502
ArmISA::SveComplexOp::op1
IntRegIndex op1
Definition: sve.hh:866
ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:683
ArmISA::SveComplexIdxOp::op2
IntRegIndex op2
Definition: sve.hh:884
ArmISA::SvePredCountOp::gp
IntRegIndex gp
Definition: sve.hh:124
ArmISA::SveComplexOp::op2
IntRegIndex op2
Definition: sve.hh:866
ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:200
ArmISA::SvePartBrkOp::isMerging
bool isMerging
Definition: sve.hh:603
ArmISA::SveBinImmUnpredDestrOp::dest
IntRegIndex dest
Definition: sve.hh:778
ArmISA::SveIntCmpImmOp::gp
IntRegIndex gp
Definition: sve.hh:538
ArmISA::SvePredBinPermOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:357
ArmISA::SveIndexIROp::op2
IntRegIndex op2
Definition: sve.hh:76
ArmISA::SvePredLogicalOp::dest
IntRegIndex dest
Definition: sve.hh:372
ArmISA::SveUnaryWideImmPredOp::dest
IntRegIndex dest
Definition: sve.hh:236
ArmISA::SveIntCmpOp::op2
IntRegIndex op2
Definition: sve.hh:518
ArmISA::SveBinIdxUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:355
ArmISA::SveCompTermOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:162
ArmISA::SveDotProdIdxOp::imm
uint64_t imm
Definition: sve.hh:830
ArmISA::SveTerImmUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:454
ArmISA::SvePredTestOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:661
ArmISA::SvePredBinPermOp::op2
IntRegIndex op2
Definition: sve.hh:389
ArmISA::SveBinConstrPredOp::gp
IntRegIndex gp
Definition: sve.hh:322
ArmISA::SveUnaryWideImmPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:212
ArmISA::SveAdrOp::op1
IntRegIndex op1
Definition: sve.hh:560
ArmISA::SveBinWideImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:257
ArmISA::SveIntCmpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:478
ArmISA::SveBinConstrPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:287
ArmISA::SveTerPredOp::dest
IntRegIndex dest
Definition: sve.hh:438
ArmISA::SveWhileOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:143
ArmISA::SveUnaryWideImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:219
ArmISA::SveElemCountOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:538
ArmISA::SveDotProdIdxOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:762
ArmISA::SveAdrOp::offsetFormat
SveAdrOffsetFormat offsetFormat
Definition: sve.hh:562
ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:696
ArmISA::SveAdrOp::dest
IntRegIndex dest
Definition: sve.hh:560
ArmISA::SveComplexOp::dest
IntRegIndex dest
Definition: sve.hh:866
ArmISA::SveTblOp::op1
IntRegIndex op1
Definition: sve.hh:678
ArmISA::SveBinImmPredOp::dest
IntRegIndex dest
Definition: sve.hh:273
ArmISA::SvePtrueOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:464
ArmISA::SveBinDestrPredOp::gp
IntRegIndex gp
Definition: sve.hh:306
ArmISA::SveCmpOp::gp
IntRegIndex gp
Definition: sve.hh:405
ArmISA::SveUnaryWideImmPredOp::gp
IntRegIndex gp
Definition: sve.hh:238
ArmISA::SveIndexRROp::op1
IntRegIndex op1
Definition: sve.hh:107
ArmISA::SvePredLogicalOp::op2
IntRegIndex op2
Definition: sve.hh:372
ArmISA::SveAdrOp::SveAdrOffsetUnpackedSigned
@ SveAdrOffsetUnpackedSigned
Definition: sve.hh:555
ArmISA::SveIntCmpOp::op1
IntRegIndex op1
Definition: sve.hh:518
ArmISA::SveComplexIdxOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:813
ArmISA::SveSelectOp::conditional
bool conditional
Definition: sve.hh:639
ArmISA::SveAdrOp::op2
IntRegIndex op2
Definition: sve.hh:560
ArmISA::SveCmpOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:371
ArmISA::SveIndexIIOp::imm2
int8_t imm2
Definition: sve.hh:60
ArmISA::SveAdrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:514
ArmISA::SveComplexIdxOp::imm
uint8_t imm
Definition: sve.hh:885
ArmISA::SveOrdReducOp::op1
IntRegIndex op1
Definition: sve.hh:486
ArmISA::SveUnaryWideImmPredOp::isMerging
bool isMerging
Definition: sve.hh:240
ArmISA::SveBinImmUnpredConstrOp::dest
IntRegIndex dest
Definition: sve.hh:256
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
ArmISA::SvePartBrkPropOp::dest
IntRegIndex dest
Definition: sve.hh:618
ArmISA::SveElemCountOp::imm
uint8_t imm
Definition: sve.hh:581
ArmISA::SveBinIdxUnpredOp::index
uint8_t index
Definition: sve.hh:356
ArmISA::SveCompTermOp::op2
IntRegIndex op2
Definition: sve.hh:175
ArmISA::SveBinDestrPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:271
Loader::SymbolTable
Definition: symtab.hh:59
ArmISA::SveElemCountOp::dstIsVec
bool dstIsVec
Definition: sve.hh:582
ArmISA::SveReducOp::dest
IntRegIndex dest
Definition: sve.hh:471
ArmISA::sveDecodePredCount
unsigned int sveDecodePredCount(uint8_t imm, unsigned int num_elems)
Returns the actual number of elements active for PTRUE(S) instructions.
Definition: sve.cc:864
ArmISA::SveBinUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:340
ArmISA::SveBinUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:306
ArmISA::SveCmpOp::op2
IntRegIndex op2
Definition: sve.hh:405
ArmISA::SveBinImmPredOp::gp
IntRegIndex gp
Definition: sve.hh:273
ArmISA::SveDotProdOp::op1
IntRegIndex op1
Definition: sve.hh:848
ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:746
ArmISA::SveBinImmPredOp::imm
uint64_t imm
Definition: sve.hh:274
ArmISA::SveOrdReducOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:448
ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:296
ArmISA::SveBinUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:340
ArmISA::SveBinDestrPredOp::op2
IntRegIndex op2
Definition: sve.hh:306
ArmISA::SvePredCountPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:58
ArmISA::SvePredLogicalOp::op1
IntRegIndex op1
Definition: sve.hh:372
ArmISA::SvePredLogicalOp::gp
IntRegIndex gp
Definition: sve.hh:372
ArmISA::SvePredTestOp::op1
IntRegIndex op1
Definition: sve.hh:708
ArmISA::SveIndexRROp::dest
IntRegIndex dest
Definition: sve.hh:106
ArmISA::SveDotProdOp::op2
IntRegIndex op2
Definition: sve.hh:848
ArmISA::SveReducOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:434
ArmISA::SvePtrueOp::dest
IntRegIndex dest
Definition: sve.hh:501
ArmISA::SveSelectOp::op1
IntRegIndex op1
Definition: sve.hh:637
ArmISA::SveUnaryWideImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:220
ArmISA::SveIndexIROp::imm1
int8_t imm1
Definition: sve.hh:75
ArmISA::SveBinConstrPredOp::predType
SvePredType predType
Definition: sve.hh:323
ArmISA::SveComplexIdxOp::dest
IntRegIndex dest
Definition: sve.hh:884
ArmISA::SveCmpImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:386
ArmISA::SveComplexIdxOp::rot
uint8_t rot
Definition: sve.hh:885
ArmISA
Definition: ccregs.hh:41
ArmISA::SveBinImmUnpredConstrOp::op1
IntRegIndex op1
Definition: sve.hh:256
ArmISA::SvePredCountPredOp::gp
IntRegIndex gp
Definition: sve.hh:144
ArmISA::SveUnaryUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:204
ArmISA::SveIndexRIOp::op1
IntRegIndex op1
Definition: sve.hh:91
ArmISA::SvePredCountOp::srcIs32b
bool srcIs32b
Definition: sve.hh:125
ArmISA::SveSelectOp::simdFp
bool simdFp
Definition: sve.hh:641
ArmISA::SveUnarySca2VecUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:812
ArmISA::SveComplexOp::rot
uint8_t rot
Definition: sve.hh:867
ArmISA::SveBinConstrPredOp::op2
IntRegIndex op2
Definition: sve.hh:322
ArmISA::SveBinWideImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:290
ArmISA::SveBinImmIdxUnpredOp::imm
uint64_t imm
Definition: sve.hh:796
ArmISA::SveUnaryPredPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:622
ArmISA::SvePredCountOp::destIsVec
bool destIsVec
Definition: sve.hh:126
ArmISA::SveBinDestrPredOp::dest
IntRegIndex dest
Definition: sve.hh:306
sve.hh
ArmISA::SvePredType::MERGE
@ MERGE
ArmISA::SveWhileOp::srcIs32b
bool srcIs32b
Definition: sve.hh:160
ArmISA::SveCmpImmOp::imm
uint64_t imm
Definition: sve.hh:422
ArmISA::SveBinImmUnpredConstrOp::imm
uint64_t imm
Definition: sve.hh:257
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
ArmISA::SveDotProdOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:779
ArmISA::SveSelectOp::scalar
bool scalar
Definition: sve.hh:640
ArmISA::SveBinImmUnpredDestrOp::op1
IntRegIndex op1
Definition: sve.hh:779
ArmISA::SvePredCountPredOp::dest
IntRegIndex dest
Definition: sve.hh:142
ArmISA::SveIndexRIOp::imm2
int8_t imm2
Definition: sve.hh:92
ArmISA::SvePartBrkPropOp::gp
IntRegIndex gp
Definition: sve.hh:621
ArmISA::SvePredLogicalOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:337
ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:141
ArmISA::SveUnpackOp::op1
IntRegIndex op1
Definition: sve.hh:694
ArmISA::SveUnpackOp::dest
IntRegIndex dest
Definition: sve.hh:693
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::SvePredLogicalOp::isSel
bool isSel
Definition: sve.hh:373
ArmISA::SveUnpackOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:649
ArmISA::SveDotProdIdxOp::dest
IntRegIndex dest
Definition: sve.hh:829
ArmISA::SveIntCmpOp::gp
IntRegIndex gp
Definition: sve.hh:519
ArmISA::SveBinImmUnpredDestrOp::imm
uint64_t imm
Definition: sve.hh:780
ArmISA::SveIntCmpImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:498
ArmISA::sveExpandFpImmAddSub
uint64_t sveExpandFpImmAddSub(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).
Definition: sve.cc:907
ArmISA::SveTerImmUnpredOp::imm
uint64_t imm
Definition: sve.hh:455
ArmISA::SvePredType::ZERO
@ ZERO
ArmISA::svePredTypeToStr
const char * svePredTypeToStr(SvePredType pt)
Returns the specifier for the predication type pt as a string.
Definition: sve.cc:45
ArmISA::SvePartBrkPropOp::op1
IntRegIndex op1
Definition: sve.hh:619
ArmISA::SveElemCountOp::esize
uint8_t esize
Definition: sve.hh:584
ArmISA::SveElemCountOp::pattern
uint8_t pattern
Definition: sve.hh:580
ArmISA::SvePredUnaryWImplicitSrcPredOp::dest
IntRegIndex dest
Definition: sve.hh:737
ArmISA::SveReducOp::op1
IntRegIndex op1
Definition: sve.hh:471
ArmISA::SveUnaryPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:174
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:258
ArmISA::SveIntCmpImmOp::imm
int64_t imm
Definition: sve.hh:537
ArmISA::SveBinImmIdxUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:795
ArmISA::SveElemCountOp::dest
IntRegIndex dest
Definition: sve.hh:579
ArmISA::SveIndexIIOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:93
ArmISA::SveSelectOp::scalar_width
size_t scalar_width
Definition: sve.hh:642
ArmISA::SveIndexIIOp::imm1
int8_t imm1
Definition: sve.hh:59
ArmISA::sveExpandFpImmMul
uint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).
Definition: sve.cc:948
ArmISA::sveExpandFpImmMaxMin
uint64_t sveExpandFpImmMaxMin(uint8_t imm, uint8_t size)
Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).
Definition: sve.cc:929
ArmISA::SvePredType
SvePredType
Definition: sve.hh:45
ArmISA::SveTerPredOp::op2
IntRegIndex op2
Definition: sve.hh:438
ArmISA::SvePartBrkPropOp::op2
IntRegIndex op2
Definition: sve.hh:620
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::SveBinImmIdxUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:731
ArmISA::SveUnaryWideImmPredOp::imm
uint64_t imm
Definition: sve.hh:237
ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:355
ArmISA::SveCmpImmOp::op1
IntRegIndex op1
Definition: sve.hh:421
ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:348
ArmISA::SveTblOp::op2
IntRegIndex op2
Definition: sve.hh:679
ArmISA::SveUnaryPredPredOp::dest
IntRegIndex dest
Definition: sve.hh:660
ArmISA::SvePartBrkOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:566
ArmISA::SveDotProdIdxOp::op2
IntRegIndex op2
Definition: sve.hh:829
ArmISA::SveIndexRIOp::dest
IntRegIndex dest
Definition: sve.hh:90
ArmISA::SveAdrOp::SveAdrOffsetUnpackedUnsigned
@ SveAdrOffsetUnpackedUnsigned
Definition: sve.hh:556
ArmISA::SveBinImmUnpredConstrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:227
ArmISA::SveBinIdxUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:355
ArmISA::SveBinWideImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:289
ArmISA::ArmStaticInst::printFloatReg
void printFloatReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:342
ArmISA::SveUnaryPredOp::dest
IntRegIndex dest
Definition: sve.hh:189
ArmISA::sveDisasmPredCountImm
std::string sveDisasmPredCountImm(uint8_t imm)
Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.
Definition: sve.cc:832
ArmISA::SveReducOp::gp
IntRegIndex gp
Definition: sve.hh:471
ArmISA::SveOrdReducOp::gp
IntRegIndex gp
Definition: sve.hh:486
ArmISA::SveComplexIdxOp::op1
IntRegIndex op1
Definition: sve.hh:884
ArmISA::SvePartBrkPropOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:580
ArmISA::SveWhileOp::dest
IntRegIndex dest
Definition: sve.hh:159
ArmISA::SveBinImmPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:241
ArmISA::SveUnaryUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:204
ArmISA::SveIntCmpOp::op2IsWide
bool op2IsWide
Definition: sve.hh:520
ArmISA::SveUnarySca2VecUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:812
ArmISA::SvePredCountOp::dest
IntRegIndex dest
Definition: sve.hh:123
ArmISA::SveUnaryPredOp::op1
IntRegIndex op1
Definition: sve.hh:189
ArmISA::SveBinConstrPredOp::op1
IntRegIndex op1
Definition: sve.hh:322
ArmISA::SveCompTermOp::op1
IntRegIndex op1
Definition: sve.hh:175
ArmISA::SveSelectOp::dest
IntRegIndex dest
Definition: sve.hh:636
ArmISA::SveTerPredOp::gp
IntRegIndex gp
Definition: sve.hh:438
ArmISA::SveUnarySca2VecUnpredOp::simdFp
bool simdFp
Definition: sve.hh:813
ArmISA::SveTerPredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:402
ArmISA::SveSelectOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:596
ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:374
ArmISA::SveTblOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:636
ArmISA::SvePredTestOp::gp
IntRegIndex gp
Definition: sve.hh:709
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
ArmISA::SveCmpOp::op1
IntRegIndex op1
Definition: sve.hh:405
ArmISA::SveIndexRROp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:129
ArmISA::SveIndexRROp::op2
IntRegIndex op2
Definition: sve.hh:108
ArmISA::SveIndexIIOp::dest
IntRegIndex dest
Definition: sve.hh:58
ArmISA::SveIndexRIOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:116
ArmISA::SvePredCountOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:72
ArmISA::SveCmpOp::dest
IntRegIndex dest
Definition: sve.hh:405
ArmISA::SveIndexIROp::dest
IntRegIndex dest
Definition: sve.hh:74
ArmISA::SveBinIdxUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:320
ArmISA::SveDotProdOp::dest
IntRegIndex dest
Definition: sve.hh:848
ArmISA::SveTblOp::dest
IntRegIndex dest
Definition: sve.hh:677
ArmISA::SvePredUnaryWImplicitSrcPredOp::gp
IntRegIndex gp
Definition: sve.hh:738
ArmISA::SveCmpImmOp::gp
IntRegIndex gp
Definition: sve.hh:421
ArmISA::SvePredUnaryWImplicitSrcOp::dest
IntRegIndex dest
Definition: sve.hh:723
ArmISA::SveWImplicitSrcDstOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:706
ArmISA::SvePredBinPermOp::op1
IntRegIndex op1
Definition: sve.hh:389
ArmISA::SveBinImmIdxUnpredOp::op1
IntRegIndex op1
Definition: sve.hh:795
ArmISA::SveIntCmpImmOp::dest
IntRegIndex dest
Definition: sve.hh:535
ArmISA::SveBinIdxUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:355
ArmISA::SveOrdReducOp::dest
IntRegIndex dest
Definition: sve.hh:486
ArmISA::SveUnaryPredPredOp::op1
IntRegIndex op1
Definition: sve.hh:661
ArmISA::SveDotProdIdxOp::op1
IntRegIndex op1
Definition: sve.hh:829
ArmISA::SveWhileOp::op1
IntRegIndex op1
Definition: sve.hh:159
ArmISA::SveTerPredOp::op1
IntRegIndex op1
Definition: sve.hh:438
ArmISA::SveElemCountOp::dstIs32b
bool dstIs32b
Definition: sve.hh:583
ArmISA::SvePredUnaryWImplicitDstOp::op1
IntRegIndex op1
Definition: sve.hh:753
ArmISA::SveComplexOp::gp
IntRegIndex gp
Definition: sve.hh:866
ArmISA::SveIndexIROp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:104
ArmISA::SveWhileOp::op2
IntRegIndex op2
Definition: sve.hh:159
ArmISA::SveComplexOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:793
ArmISA::SveTerImmUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:418
ArmISA::SveIntCmpOp::dest
IntRegIndex dest
Definition: sve.hh:517
ArmISA::SvePartBrkOp::gp
IntRegIndex gp
Definition: sve.hh:601
ArmISA::SvePartBrkOp::dest
IntRegIndex dest
Definition: sve.hh:600
ArmISA::SveAdrOp::mult
uint8_t mult
Definition: sve.hh:561
ArmISA::SveBinUnpredOp::op2
IntRegIndex op2
Definition: sve.hh:340
ArmISA::SveCmpImmOp::dest
IntRegIndex dest
Definition: sve.hh:421
ArmISA::SvePartBrkOp::op1
IntRegIndex op1
Definition: sve.hh:602
ArmISA::SveUnaryPredOp::gp
IntRegIndex gp
Definition: sve.hh:189
ArmISA::SveUnaryPredPredOp::gp
IntRegIndex gp
Definition: sve.hh:662
ArmISA::SveBinConstrPredOp::dest
IntRegIndex dest
Definition: sve.hh:322
ArmISA::SveTerImmUnpredOp::dest
IntRegIndex dest
Definition: sve.hh:454
ArmISA::SveUnaryUnpredOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:188
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:673
ArmISA::SvePredBinPermOp::dest
IntRegIndex dest
Definition: sve.hh:389
ArmISA::SveIntCmpImmOp::op1
IntRegIndex op1
Definition: sve.hh:536
ArmISA::SveBinImmUnpredDestrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve.cc:715
ArmISA::SvePredCountPredOp::op1
IntRegIndex op1
Definition: sve.hh:143
ArmISA::SveSelectOp::gp
IntRegIndex gp
Definition: sve.hh:638

Generated on Wed Sep 30 2020 14:02:00 for gem5 by doxygen 1.8.17