gem5  v20.1.0.0
write_queue_entry.cc
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41 
48 
49 #include <cassert>
50 #include <string>
51 
52 #include "base/logging.hh"
53 #include "base/types.hh"
54 #include "mem/cache/base.hh"
55 #include "mem/request.hh"
56 
57 inline void
59  Counter order)
60 {
61  emplace_back(pkt, readyTime, order);
62 }
63 
64 bool
66 {
67  for (auto& t : *this) {
68  if (pkt->trySatisfyFunctional(t.pkt)) {
69  return true;
70  }
71  }
72 
73  return false;
74 }
75 
76 void
77 WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
78  const std::string &prefix) const
79 {
80  for (auto& t : *this) {
81  ccprintf(os, "%sFromCPU: ", prefix);
82  t.pkt->print(os, verbosity, "");
83  }
84 }
85 
86 void
87 WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
88  Tick when_ready, Counter _order)
89 {
90  blkAddr = blk_addr;
91  blkSize = blk_size;
92  isSecure = target->isSecure();
93  readyTime = when_ready;
94  order = _order;
95  assert(target);
96  _isUncacheable = target->req->isUncacheable();
97  inService = false;
98 
99  // we should never have more than a single target for cacheable
100  // writes (writebacks and clean evictions)
101  panic_if(!_isUncacheable && !targets.empty(),
102  "Write queue entry %#llx should never have more than one "
103  "cacheable target", blkAddr);
104  panic_if(!((target->isWrite() && _isUncacheable) ||
105  (target->isEviction() && !_isUncacheable) ||
106  target->cmd == MemCmd::WriteClean),
107  "Write queue entry %#llx should be an uncacheable write or "
108  "a cacheable eviction or a writeclean");
109 
110  targets.add(target, when_ready, _order);
111 
112  // All targets must refer to the same block
113  assert(target->matchBlockAddr(targets.front().pkt, blkSize));
114 }
115 
116 void
118 {
119  assert(targets.empty());
120  inService = false;
121 }
122 
123 bool
125 {
126  // For printing, we treat the WriteQueueEntry as a whole as single
127  // entity. For other requests, we iterate over the individual
128  // targets since that's where the actual data lies.
129  if (pkt->isPrint()) {
130  pkt->trySatisfyFunctional(this, blkAddr, isSecure, blkSize, nullptr);
131  return false;
132  } else {
133  return targets.trySatisfyFunctional(pkt);
134  }
135 }
136 
137 bool
139 {
140  return cache.sendWriteQueuePacket(this);
141 }
142 
143 bool
144 WriteQueueEntry::matchBlockAddr(const Addr addr, const bool is_secure) const
145 {
146  assert(hasTargets());
147  return (blkAddr == addr) && (isSecure == is_secure);
148 }
149 
150 bool
152 {
153  assert(hasTargets());
154  return pkt->matchBlockAddr(blkAddr, isSecure, blkSize);
155 }
156 
157 bool
159 {
160  assert(hasTargets());
161  return entry->matchBlockAddr(blkAddr, isSecure);
162 }
163 
164 void
165 WriteQueueEntry::print(std::ostream &os, int verbosity,
166  const std::string &prefix) const
167 {
168  ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
169  prefix, blkAddr, blkAddr + blkSize - 1,
170  isSecure ? "s" : "ns",
171  _isUncacheable ? "Unc" : "",
172  inService ? "InSvc" : "");
173 
174  ccprintf(os, "%s Targets:\n", prefix);
175  targets.print(os, verbosity, prefix + " ");
176 }
177 
178 std::string
180 {
181  std::ostringstream str;
182  print(str);
183  return str.str();
184 }
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
base.hh
QueueEntry::blkAddr
Addr blkAddr
Block aligned address.
Definition: queue_entry.hh:111
WriteQueueEntry::allocate
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order)
Allocate a miss to this entry.
Definition: write_queue_entry.cc:87
QueueEntry::matchBlockAddr
virtual bool matchBlockAddr(const Addr addr, const bool is_secure) const =0
Check if entry corresponds to the one being looked for.
WriteQueueEntry::TargetList::print
void print(std::ostream &os, int verbosity, const std::string &prefix) const
Definition: write_queue_entry.cc:77
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:340
Packet::isEviction
bool isEviction() const
Definition: packet.hh:572
Packet::matchBlockAddr
bool matchBlockAddr(const Addr addr, const bool is_secure, const int blk_size) const
Check if packet corresponds to a given block-aligned address and address space.
Definition: packet.cc:410
WriteQueueEntry::hasTargets
bool hasTargets() const
Returns true if there are targets left.
Definition: write_queue_entry.hh:144
request.hh
Packet::isSecure
bool isSecure() const
Definition: packet.hh:783
WriteQueueEntry::sendPacket
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
Definition: write_queue_entry.cc:138
WriteQueueEntry::matchBlockAddr
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
Definition: write_queue_entry.cc:144
Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:58
WriteQueueEntry::conflictAddr
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
Definition: write_queue_entry.cc:158
QueueEntry::isSecure
bool isSecure
True if the entry targets the secure memory space.
Definition: queue_entry.hh:117
QueueEntry::blkSize
unsigned blkSize
Block size of the cache.
Definition: queue_entry.hh:114
BaseCache
A basic cache interface.
Definition: base.hh:89
WriteQueueEntry::deallocate
void deallocate()
Mark this entry as free.
Definition: write_queue_entry.cc:117
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
WriteQueueEntry::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: write_queue_entry.cc:124
QueueEntry::readyTime
Tick readyTime
Tick when ready to issue.
Definition: queue_entry.hh:70
QueueEntry::order
Counter order
Order number assigned to disambiguate writes and misses.
Definition: queue_entry.hh:108
QueueEntry::_isUncacheable
bool _isUncacheable
True if the entry is uncacheable.
Definition: queue_entry.hh:73
WriteQueueEntry::print
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
Definition: write_queue_entry.cc:179
Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:335
QueueEntry::inService
bool inService
True if the entry has been sent downstream.
Definition: queue_entry.hh:105
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
BaseCache::sendWriteQueuePacket
bool sendWriteQueuePacket(WriteQueueEntry *wq_entry)
Similar to sendMSHR, but for a write-queue entry instead.
Definition: base.cc:1760
types.hh
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
addr
ip6_addr_t addr
Definition: inet.hh:423
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
logging.hh
Packet::isWrite
bool isWrite() const
Definition: packet.hh:557
WriteQueueEntry::TargetList::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr pkt)
Definition: write_queue_entry.cc:65
QueueEntry
A queue entry base class, to be used by both the MSHRs and write-queue entries.
Definition: queue_entry.hh:58
MemCmd::WriteClean
@ WriteClean
Definition: packet.hh:90
Packet::isPrint
bool isPrint() const
Definition: packet.hh:584
WriteQueueEntry::targets
TargetList targets
List of all requests that match the address.
Definition: write_queue_entry.hh:109
Packet::trySatisfyFunctional
bool trySatisfyFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition: packet.hh:1331
WriteQueueEntry::TargetList::add
void add(PacketPtr pkt, Tick readyTime, Counter order)
Definition: write_queue_entry.cc:58
write_queue_entry.hh

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