gem5  v20.1.0.0
decoder.cc
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28 
29 #include "arch/x86/decoder.hh"
30 
31 #include "arch/x86/regs/misc.hh"
32 #include "base/logging.hh"
33 #include "base/trace.hh"
34 #include "base/types.hh"
35 #include "debug/Decoder.hh"
36 
37 namespace X86ISA
38 {
39 
41 
44 {
45  origPC = basePC + offset;
46  DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
48  chunkIdx = 0;
49 
50  emi.rex = 0;
51  emi.legacy = 0;
52  emi.vex = 0;
53 
54  emi.opcode.type = BadOpcode;
55  emi.opcode.op = 0;
56 
58  emi.immediate = 0;
59  emi.displacement = 0;
60  emi.dispSize = 0;
61 
62  emi.modRM = 0;
63  emi.sib = 0;
64 
65  if (instBytes->si) {
66  return FromCacheState;
67  } else {
68  instBytes->chunks.clear();
69  return PrefixState;
70  }
71 }
72 
73 void
75 {
76  // This function drives the decoder state machine.
77 
78  // Some sanity checks. You shouldn't try to process more bytes if
79  // there aren't any, and you shouldn't overwrite an already decoded
80  // ExtMachInst.
81  assert(!outOfBytes);
82  assert(!instDone);
83 
84  if (state == ResetState)
85  state = doResetState();
86  if (state == FromCacheState) {
88  } else {
89  instBytes->chunks.push_back(fetchChunk);
90  }
91 
92  // While there's still something to do...
93  while (!instDone && !outOfBytes) {
94  uint8_t nextByte = getNextByte();
95  switch (state) {
96  case PrefixState:
97  state = doPrefixState(nextByte);
98  break;
99  case Vex2Of2State:
100  state = doVex2Of2State(nextByte);
101  break;
102  case Vex2Of3State:
103  state = doVex2Of3State(nextByte);
104  break;
105  case Vex3Of3State:
106  state = doVex3Of3State(nextByte);
107  break;
108  case VexOpcodeState:
109  state = doVexOpcodeState(nextByte);
110  break;
111  case OneByteOpcodeState:
112  state = doOneByteOpcodeState(nextByte);
113  break;
114  case TwoByteOpcodeState:
115  state = doTwoByteOpcodeState(nextByte);
116  break;
118  state = doThreeByte0F38OpcodeState(nextByte);
119  break;
121  state = doThreeByte0F3AOpcodeState(nextByte);
122  break;
123  case ModRMState:
124  state = doModRMState(nextByte);
125  break;
126  case SIBState:
127  state = doSIBState(nextByte);
128  break;
129  case DisplacementState:
131  break;
132  case ImmediateState:
134  break;
135  case ErrorState:
136  panic("Went to the error state in the decoder.\n");
137  default:
138  panic("Unrecognized state! %d\n", state);
139  }
140  }
141 }
142 
145 {
146  DPRINTF(Decoder, "Looking at cache state.\n");
147  if ((fetchChunk & instBytes->masks[chunkIdx]) !=
149  DPRINTF(Decoder, "Decode cache miss.\n");
150  // The chached chunks didn't match what was fetched. Fall back to the
151  // predecoder.
153  instBytes->chunks.resize(chunkIdx + 1);
154  instBytes->si = NULL;
155  chunkIdx = 0;
157  offset = origPC % sizeof(MachInst);
158  basePC = origPC - offset;
159  return PrefixState;
160  } else if (chunkIdx == instBytes->chunks.size() - 1) {
161  // We matched the cache, so use its value.
162  instDone = true;
164  if (offset == sizeof(MachInst))
165  outOfBytes = true;
166  return ResetState;
167  } else {
168  // We matched so far, but need to check more chunks.
169  chunkIdx++;
170  outOfBytes = true;
171  return FromCacheState;
172  }
173 }
174 
175 // Either get a prefix and record it in the ExtMachInst, or send the
176 // state machine on to get the opcode(s).
178 Decoder::doPrefixState(uint8_t nextByte)
179 {
180  uint8_t prefix = Prefixes[nextByte];
181  State nextState = PrefixState;
182  // REX prefixes are only recognized in 64 bit mode.
183  if (prefix == RexPrefix && emi.mode.submode != SixtyFourBitMode)
184  prefix = 0;
185  if (prefix)
186  consumeByte();
187  switch(prefix) {
188  // Operand size override prefixes
189  case OperandSizeOverride:
190  DPRINTF(Decoder, "Found operand size override prefix.\n");
191  emi.legacy.op = true;
192  break;
193  case AddressSizeOverride:
194  DPRINTF(Decoder, "Found address size override prefix.\n");
195  emi.legacy.addr = true;
196  break;
197  // Segment override prefixes
198  case CSOverride:
199  case DSOverride:
200  case ESOverride:
201  case FSOverride:
202  case GSOverride:
203  case SSOverride:
204  DPRINTF(Decoder, "Found segment override.\n");
205  emi.legacy.seg = prefix;
206  break;
207  case Lock:
208  DPRINTF(Decoder, "Found lock prefix.\n");
209  emi.legacy.lock = true;
210  break;
211  case Rep:
212  DPRINTF(Decoder, "Found rep prefix.\n");
213  emi.legacy.rep = true;
214  break;
215  case Repne:
216  DPRINTF(Decoder, "Found repne prefix.\n");
217  emi.legacy.repne = true;
218  break;
219  case RexPrefix:
220  DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
221  emi.rex = nextByte;
222  break;
223  case Vex2Prefix:
224  DPRINTF(Decoder, "Found VEX two-byte prefix %#x.\n", nextByte);
225  emi.vex.present = 1;
226  nextState = Vex2Of2State;
227  break;
228  case Vex3Prefix:
229  DPRINTF(Decoder, "Found VEX three-byte prefix %#x.\n", nextByte);
230  emi.vex.present = 1;
231  nextState = Vex2Of3State;
232  break;
233  case 0:
234  nextState = OneByteOpcodeState;
235  break;
236 
237  default:
238  panic("Unrecognized prefix %#x\n", nextByte);
239  }
240  return nextState;
241 }
242 
244 Decoder::doVex2Of2State(uint8_t nextByte)
245 {
246  consumeByte();
247  Vex2Of2 vex = nextByte;
248 
249  emi.rex.r = !vex.r;
250 
251  emi.vex.l = vex.l;
252  emi.vex.v = ~vex.v;
253 
254  switch (vex.p) {
255  case 0:
256  break;
257  case 1:
258  emi.legacy.op = 1;
259  break;
260  case 2:
261  emi.legacy.rep = 1;
262  break;
263  case 3:
264  emi.legacy.repne = 1;
265  break;
266  }
267 
268  emi.opcode.type = TwoByteOpcode;
269 
270  return VexOpcodeState;
271 }
272 
274 Decoder::doVex2Of3State(uint8_t nextByte)
275 {
276  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
277  // This was actually an LDS instruction. Reroute to that path.
278  emi.vex.present = 0;
279  emi.opcode.type = OneByteOpcode;
280  emi.opcode.op = 0xC4;
282  nextByte >= 0xA0 && nextByte <= 0xA3);
283  }
284 
285  consumeByte();
286  Vex2Of3 vex = nextByte;
287 
288  emi.rex.r = !vex.r;
289  emi.rex.x = !vex.x;
290  emi.rex.b = !vex.b;
291 
292  switch (vex.m) {
293  case 1:
294  emi.opcode.type = TwoByteOpcode;
295  break;
296  case 2:
297  emi.opcode.type = ThreeByte0F38Opcode;
298  break;
299  case 3:
300  emi.opcode.type = ThreeByte0F3AOpcode;
301  break;
302  default:
303  // These encodings are reserved. Pretend this was an undefined
304  // instruction so the main decoder will behave correctly, and stop
305  // trying to interpret bytes.
306  emi.opcode.type = TwoByteOpcode;
307  emi.opcode.op = 0x0B;
308  instDone = true;
309  return ResetState;
310  }
311  return Vex3Of3State;
312 }
313 
315 Decoder::doVex3Of3State(uint8_t nextByte)
316 {
317  if (emi.mode.submode != SixtyFourBitMode && bits(nextByte, 7, 6) == 0x3) {
318  // This was actually an LES instruction. Reroute to that path.
319  emi.vex.present = 0;
320  emi.opcode.type = OneByteOpcode;
321  emi.opcode.op = 0xC5;
323  nextByte >= 0xA0 && nextByte <= 0xA3);
324  }
325 
326  consumeByte();
327  Vex3Of3 vex = nextByte;
328 
329  emi.rex.w = vex.w;
330 
331  emi.vex.l = vex.l;
332  emi.vex.v = ~vex.v;
333 
334  switch (vex.p) {
335  case 0:
336  break;
337  case 1:
338  emi.legacy.op = 1;
339  break;
340  case 2:
341  emi.legacy.rep = 1;
342  break;
343  case 3:
344  emi.legacy.repne = 1;
345  break;
346  }
347 
348  return VexOpcodeState;
349 }
350 
352 Decoder::doVexOpcodeState(uint8_t nextByte)
353 {
354  DPRINTF(Decoder, "Found VEX opcode %#x.\n", nextByte);
355 
356  emi.opcode.op = nextByte;
357  consumeByte();
358 
359  switch (emi.opcode.type) {
360  case TwoByteOpcode:
362  case ThreeByte0F38Opcode:
365  case ThreeByte0F3AOpcode:
368  default:
369  panic("Unrecognized opcode type %d.\n", emi.opcode.type);
370  }
371 }
372 
373 // Load the first opcode byte. Determine if there are more opcode bytes, and
374 // if not, what immediate and/or ModRM is needed.
377 {
378  State nextState = ErrorState;
379  consumeByte();
380 
381  if (nextByte == 0x0f) {
382  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
383  nextState = TwoByteOpcodeState;
384  } else {
385  DPRINTF(Decoder, "Found one byte opcode %#x.\n", nextByte);
386  emi.opcode.type = OneByteOpcode;
387  emi.opcode.op = nextByte;
388 
390  nextByte >= 0xA0 && nextByte <= 0xA3);
391  }
392  return nextState;
393 }
394 
395 // Load the second opcode byte. Determine if there are more opcode bytes, and
396 // if not, what immediate and/or ModRM is needed.
399 {
400  State nextState = ErrorState;
401  consumeByte();
402  if (nextByte == 0x38) {
403  nextState = ThreeByte0F38OpcodeState;
404  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
405  } else if (nextByte == 0x3a) {
406  nextState = ThreeByte0F3AOpcodeState;
407  DPRINTF(Decoder, "Found opcode escape byte %#x.\n", nextByte);
408  } else {
409  DPRINTF(Decoder, "Found two byte opcode %#x.\n", nextByte);
410  emi.opcode.type = TwoByteOpcode;
411  emi.opcode.op = nextByte;
412 
414  }
415  return nextState;
416 }
417 
418 // Load the third opcode byte and determine what immediate and/or ModRM is
419 // needed.
422 {
423  consumeByte();
424 
425  DPRINTF(Decoder, "Found three byte 0F38 opcode %#x.\n", nextByte);
426  emi.opcode.type = ThreeByte0F38Opcode;
427  emi.opcode.op = nextByte;
428 
430 }
431 
432 // Load the third opcode byte and determine what immediate and/or ModRM is
433 // needed.
436 {
437  consumeByte();
438 
439  DPRINTF(Decoder, "Found three byte 0F3A opcode %#x.\n", nextByte);
440  emi.opcode.type = ThreeByte0F3AOpcode;
441  emi.opcode.op = nextByte;
442 
444 }
445 
446 // Generic opcode processing which determines the immediate size, and whether
447 // or not there's a modrm byte.
449 Decoder::processOpcode(ByteTable &immTable, ByteTable &modrmTable,
450  bool addrSizedImm)
451 {
452  State nextState = ErrorState;
453  const uint8_t opcode = emi.opcode.op;
454 
455  // Figure out the effective operand size. This can be overriden to
456  // a fixed value at the decoder level.
457  int logOpSize;
458  if (emi.rex.w)
459  logOpSize = 3; // 64 bit operand size
460  else if (emi.legacy.op)
461  logOpSize = altOp;
462  else
463  logOpSize = defOp;
464 
465  // Set the actual op size.
466  emi.opSize = 1 << logOpSize;
467 
468  // Figure out the effective address size. This can be overriden to
469  // a fixed value at the decoder level.
470  int logAddrSize;
471  if (emi.legacy.addr)
472  logAddrSize = altAddr;
473  else
474  logAddrSize = defAddr;
475 
476  // Set the actual address size.
477  emi.addrSize = 1 << logAddrSize;
478 
479  // Figure out the effective stack width. This can be overriden to
480  // a fixed value at the decoder level.
481  emi.stackSize = 1 << stack;
482 
483  // Figure out how big of an immediate we'll retreive based
484  // on the opcode.
485  int immType = immTable[opcode];
486  if (addrSizedImm)
487  immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
488  else
489  immediateSize = SizeTypeToSize[logOpSize - 1][immType];
490 
491  // Determine what to expect next.
492  if (modrmTable[opcode]) {
493  nextState = ModRMState;
494  } else {
495  if (immediateSize) {
496  nextState = ImmediateState;
497  } else {
498  instDone = true;
499  nextState = ResetState;
500  }
501  }
502  return nextState;
503 }
504 
505 // Get the ModRM byte and determine what displacement, if any, there is.
506 // Also determine whether or not to get the SIB byte, displacement, or
507 // immediate next.
509 Decoder::doModRMState(uint8_t nextByte)
510 {
511  State nextState = ErrorState;
512  ModRM modRM = nextByte;
513  DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
514  if (defOp == 1) {
515  // Figure out 16 bit displacement size.
516  if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
517  displacementSize = 2;
518  else if (modRM.mod == 1)
519  displacementSize = 1;
520  else
521  displacementSize = 0;
522  } else {
523  // Figure out 32/64 bit displacement size.
524  if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
525  displacementSize = 4;
526  else if (modRM.mod == 1)
527  displacementSize = 1;
528  else
529  displacementSize = 0;
530  }
531 
532  // The "test" instruction in group 3 needs an immediate, even though
533  // the other instructions with the same actual opcode don't.
534  if (emi.opcode.type == OneByteOpcode && (modRM.reg & 0x6) == 0) {
535  if (emi.opcode.op == 0xF6)
536  immediateSize = 1;
537  else if (emi.opcode.op == 0xF7)
538  immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
539  }
540 
541  // If there's an SIB, get that next.
542  // There is no SIB in 16 bit mode.
543  if (modRM.rm == 4 && modRM.mod != 3) {
544  // && in 32/64 bit mode)
545  nextState = SIBState;
546  } else if (displacementSize) {
547  nextState = DisplacementState;
548  } else if (immediateSize) {
549  nextState = ImmediateState;
550  } else {
551  instDone = true;
552  nextState = ResetState;
553  }
554  // The ModRM byte is consumed no matter what.
555  consumeByte();
556  emi.modRM = modRM;
557  return nextState;
558 }
559 
560 // Get the SIB byte. We don't do anything with it at this point, other
561 // than storing it in the ExtMachInst. Determine if we need to get a
562 // displacement or immediate next.
564 Decoder::doSIBState(uint8_t nextByte)
565 {
566  State nextState = ErrorState;
567  emi.sib = nextByte;
568  DPRINTF(Decoder, "Found SIB byte %#x.\n", nextByte);
569  consumeByte();
570  if (emi.modRM.mod == 0 && emi.sib.base == 5)
571  displacementSize = 4;
572  if (displacementSize) {
573  nextState = DisplacementState;
574  } else if (immediateSize) {
575  nextState = ImmediateState;
576  } else {
577  instDone = true;
578  nextState = ResetState;
579  }
580  return nextState;
581 }
582 
583 // Gather up the displacement, or at least as much of it as we can get.
586 {
587  State nextState = ErrorState;
588 
592 
593  DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
595 
597  // Reset this for other immediates.
598  immediateCollected = 0;
599  // Sign extend the displacement.
600  switch(displacementSize)
601  {
602  case 1:
603  emi.displacement = sext<8>(emi.displacement);
604  break;
605  case 2:
606  emi.displacement = sext<16>(emi.displacement);
607  break;
608  case 4:
609  emi.displacement = sext<32>(emi.displacement);
610  break;
611  default:
612  panic("Undefined displacement size!\n");
613  }
614  DPRINTF(Decoder, "Collected displacement %#x.\n",
615  emi.displacement);
616  if (immediateSize) {
617  nextState = ImmediateState;
618  } else {
619  instDone = true;
620  nextState = ResetState;
621  }
622 
624  }
625  else
626  nextState = DisplacementState;
627  return nextState;
628 }
629 
630 // Gather up the immediate, or at least as much of it as we can get.
633 {
634  State nextState = ErrorState;
635 
637 
638  DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n",
640 
642  // Reset this for other immediates.
643  immediateCollected = 0;
644 
645  //XXX Warning! The following is an observed pattern and might
646  // not always be true!
647 
648  // Instructions which use 64 bit operands but 32 bit immediates
649  // need to have the immediate sign extended to 64 bits.
650  // Instructions which use true 64 bit immediates won't be
651  // affected, and instructions that use true 32 bit immediates
652  // won't notice.
653  switch(immediateSize) {
654  case 4:
655  emi.immediate = sext<32>(emi.immediate);
656  break;
657  case 1:
658  emi.immediate = sext<8>(emi.immediate);
659  }
660 
661  DPRINTF(Decoder, "Collected immediate %#x.\n",
662  emi.immediate);
663  instDone = true;
664  nextState = ResetState;
665  } else {
666  nextState = ImmediateState;
667  }
668  return nextState;
669 }
670 
673 
676 {
677  auto iter = instMap->find(mach_inst);
678  if (iter != instMap->end())
679  return iter->second;
680 
681  StaticInstPtr si = decodeInst(mach_inst);
682  (*instMap)[mach_inst] = si;
683  return si;
684 }
685 
688 {
689  if (!instDone)
690  return NULL;
691  instDone = false;
692  updateNPC(nextPC);
693 
695  if (si)
696  return si;
697 
698  // We didn't match in the AddrMap, but we still populated an entry. Fix
699  // up its byte masks.
700  const int chunkSize = sizeof(MachInst);
701 
703 
704  Addr firstBasePC = basePC - (instBytes->chunks.size() - 1) * chunkSize;
705  Addr firstOffset = origPC - firstBasePC;
706  Addr totalSize = instBytes->lastOffset - firstOffset +
707  (instBytes->chunks.size() - 1) * chunkSize;
708  int start = firstOffset;
709  instBytes->masks.clear();
710 
711  while (totalSize) {
712  int end = start + totalSize;
713  end = (chunkSize < end) ? chunkSize : end;
714  int size = end - start;
715  int idx = instBytes->masks.size();
716 
717  MachInst maskVal = mask(size * 8) << (start * 8);
718  assert(maskVal);
719 
720  instBytes->masks.push_back(maskVal);
721  instBytes->chunks[idx] &= instBytes->masks[idx];
722  totalSize -= size;
723  start = 0;
724  }
725 
726  si = decode(emi, origPC);
727  return si;
728 }
729 
732 {
733  return microcodeRom.fetchMicroop(micropc, curMacroop);
734 }
735 
736 }
X86ISA::Decoder::UsesModRMThreeByte0F38
static ByteTable UsesModRMThreeByte0F38
Definition: decoder.hh:62
X86ISA::Rep
@ Rep
Definition: types.hh:66
X86ISA::ExtMachInst::mode
OperatingMode mode
Definition: types.hh:233
X86ISA::Decoder::updateNPC
void updateNPC(X86ISA::PCState &nextPC)
Definition: decoder.hh:317
X86ISA::Decoder::PrefixState
@ PrefixState
Definition: decoder.hh:187
X86ISA::Decoder::InstBytes::chunks
std::vector< MachInst > chunks
Definition: decoder.hh:77
X86ISA::Decoder::SIBState
@ SIBState
Definition: decoder.hh:197
X86ISA::Decoder::SizeTypeToSize
static const uint8_t SizeTypeToSize[3][10]
Definition: decoder.hh:56
X86ISA::ExtMachInst::opcode
struct X86ISA::ExtMachInst::@22 opcode
X86ISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:173
X86ISA::si
Bitfield< 15, 3 > si
Definition: misc.hh:860
X86ISA::DSOverride
@ DSOverride
Definition: types.hh:59
X86ISA::ExtMachInst::op
Opcode op
Definition: types.hh:214
X86ISA::Decoder::defAddr
uint8_t defAddr
Definition: decoder.hh:105
X86ISA::Decoder::getImmediate
void getImmediate(int &collected, uint64_t &current, int size)
Definition: decoder.hh:115
X86ISA::Decoder::UsesModRMThreeByte0F3A
static ByteTable UsesModRMThreeByte0F3A
Definition: decoder.hh:63
X86ISA::Decoder::ThreeByte0F3AOpcodeState
@ ThreeByte0F3AOpcodeState
Definition: decoder.hh:195
X86ISA::Decoder::doVex2Of3State
State doVex2Of3State(uint8_t)
Definition: decoder.cc:274
X86ISA::Decoder::doPrefixState
State doPrefixState(uint8_t)
Definition: decoder.cc:178
X86ISA::Decoder::DisplacementState
@ DisplacementState
Definition: decoder.hh:198
X86ISAInst::MicrocodeRom::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop)
Definition: microcode_rom.hh:60
X86ISA::ESOverride
@ ESOverride
Definition: types.hh:56
X86ISA::Decoder::process
void process()
Definition: decoder.cc:74
X86ISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
X86ISA::Decoder::basePC
Addr basePC
Definition: decoder.hh:92
X86ISA::Decoder::altOp
uint8_t altOp
Definition: decoder.hh:102
X86ISA::Decoder::doVex3Of3State
State doVex3Of3State(uint8_t)
Definition: decoder.cc:315
X86ISA::Decoder::doTwoByteOpcodeState
State doTwoByteOpcodeState(uint8_t)
Definition: decoder.cc:398
X86ISA::MachInst
uint64_t MachInst
Definition: types.hh:52
X86ISA::Vex2Prefix
@ Vex2Prefix
Definition: types.hh:68
X86ISA::ExtMachInst::immediate
uint64_t immediate
Definition: types.hh:220
X86ISA::Decoder::immediateSize
int immediateSize
Definition: decoder.hh:179
X86ISA::Decoder::ResetState
@ ResetState
Definition: decoder.hh:185
X86ISA::Decoder::UsesModRMTwoByte
static ByteTable UsesModRMTwoByte
Definition: decoder.hh:61
X86ISA::Decoder::VexOpcodeState
@ VexOpcodeState
Definition: decoder.hh:191
X86ISA::Decoder::Vex2Of3State
@ Vex2Of3State
Definition: decoder.hh:189
decoder.hh
X86ISA::Decoder::doSIBState
State doSIBState(uint8_t)
Definition: decoder.cc:564
X86ISA::SSOverride
@ SSOverride
Definition: types.hh:58
X86ISA::ExtMachInst::displacement
uint64_t displacement
Definition: types.hh:221
X86ISA::Decoder::ImmediateTypeThreeByte0F3A
static ByteTable ImmediateTypeThreeByte0F3A
Definition: decoder.hh:68
DecodeCache::AddrMap::lookup
Value & lookup(Addr addr)
Definition: decode_cache.hh:127
X86ISA::AddressSizeOverride
@ AddressSizeOverride
Definition: types.hh:64
X86ISA::Decoder::InstBytes::lastOffset
int lastOffset
Definition: decoder.hh:79
X86ISA::FSOverride
@ FSOverride
Definition: types.hh:60
X86ISA::Decoder::Vex3Of3State
@ Vex3Of3State
Definition: decoder.hh:190
X86ISA::Decoder::ImmediateTypeTwoByte
static ByteTable ImmediateTypeTwoByte
Definition: decoder.hh:66
X86ISA::GSOverride
@ GSOverride
Definition: types.hh:61
X86ISA::Decoder::stack
uint8_t stack
Definition: decoder.hh:106
X86ISA::ExtMachInst::opSize
uint8_t opSize
Definition: types.hh:224
X86ISA::Decoder::state
State state
Definition: decoder.hh:204
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
X86ISA::OperandSizeOverride
@ OperandSizeOverride
Definition: types.hh:63
X86ISA::Decoder::immediateCollected
int immediateCollected
Definition: decoder.hh:182
X86ISA::ExtMachInst::addrSize
uint8_t addrSize
Definition: types.hh:226
X86ISA::Decoder::processOpcode
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition: decoder.cc:449
X86ISA::Decoder::doModRMState
State doModRMState(uint8_t)
Definition: decoder.cc:509
X86ISA::PCState
Definition: types.hh:287
X86ISA::Decoder::defOp
uint8_t defOp
Definition: decoder.hh:103
X86ISA::Repne
@ Repne
Definition: types.hh:67
X86ISA::Decoder::UsesModRMOneByte
static ByteTable UsesModRMOneByte
Definition: decoder.hh:60
X86ISA::Decoder::doVexOpcodeState
State doVexOpcodeState(uint8_t)
Definition: decoder.cc:352
X86ISA::Decoder::getNextByte
uint8_t getNextByte()
Definition: decoder.hh:109
X86ISA::ExtMachInst
Definition: types.hh:198
X86ISAInst::MicrocodeRom
Definition: microcode_rom.hh:39
X86ISA::Decoder::decodePages
DecodePages * decodePages
Definition: decoder.hh:235
X86ISA::Decoder::fetchRomMicroop
StaticInstPtr fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop) override
Definition: decoder.cc:731
X86ISA::Decoder::ModRMState
@ ModRMState
Definition: decoder.hh:196
X86ISA::Decoder::instDone
bool instDone
Definition: decoder.hh:175
X86ISA::Decoder::instBytes
InstBytes * instBytes
Definition: decoder.hh:89
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86ISA::Decoder::origPC
Addr origPC
Definition: decoder.hh:94
X86ISA::Decoder::instCacheMap
static InstCacheMap instCacheMap
Definition: decoder.hh:242
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
X86ISA::Decoder::TwoByteOpcodeState
@ TwoByteOpcodeState
Definition: decoder.hh:193
X86ISA::ExtMachInst::modRM
ModRM modRM
Definition: types.hh:217
X86ISA::Vex3Prefix
@ Vex3Prefix
Definition: types.hh:69
X86ISA::Decoder::chunkIdx
int chunkIdx
Definition: decoder.hh:90
X86ISA::Decoder::ErrorState
@ ErrorState
Definition: decoder.hh:201
ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:101
X86ISA::Decoder::InstBytes
Definition: decoder.hh:74
X86ISA::Decoder::ImmediateTypeOneByte
static ByteTable ImmediateTypeOneByte
Definition: decoder.hh:65
X86ISA::Decoder::doThreeByte0F38OpcodeState
State doThreeByte0F38OpcodeState(uint8_t)
Definition: decoder.cc:421
X86ISA::Decoder::dummy
static InstBytes dummy
Definition: decoder.hh:85
X86ISA::Prefixes
Prefixes
Definition: types.hh:54
X86ISA::Decoder::ThreeByte0F38OpcodeState
@ ThreeByte0F38OpcodeState
Definition: decoder.hh:194
X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:79
X86ISA::Lock
@ Lock
Definition: types.hh:65
X86ISA::CSOverride
@ CSOverride
Definition: types.hh:57
X86ISA::Decoder::ImmediateTypeThreeByte0F38
static ByteTable ImmediateTypeThreeByte0F38
Definition: decoder.hh:67
X86ISA::Decoder::doImmediateState
State doImmediateState()
Definition: decoder.cc:632
X86ISA::ExtMachInst::stackSize
uint8_t stackSize
Definition: types.hh:228
X86ISA::Decoder::ImmediateState
@ ImmediateState
Definition: decoder.hh:199
X86ISA::Decoder::fetchChunk
MachInst fetchChunk
Definition: decoder.hh:88
X86ISA::Decoder::doResetState
State doResetState()
Definition: decoder.cc:43
types.hh
X86ISA::Decoder::doVex2Of2State
State doVex2Of2State(uint8_t)
Definition: decoder.cc:244
X86ISA::ExtMachInst::type
OpcodeType type
Definition: types.hh:212
X86ISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:675
X86ISA::Decoder::InstBytes::masks
std::vector< MachInst > masks
Definition: decoder.hh:78
X86ISA::Decoder::InstCacheMap
std::unordered_map< CacheKey, DecodeCache::InstMap< ExtMachInst > * > InstCacheMap
Definition: decoder.hh:241
X86ISA::ExtMachInst::rex
Rex rex
Definition: types.hh:206
X86ISA::Decoder::InstBytes::si
StaticInstPtr si
Definition: decoder.hh:76
X86ISA::Decoder::instMap
DecodeCache::InstMap< ExtMachInst > * instMap
Definition: decoder.hh:239
logging.hh
X86ISA::ExtMachInst::sib
Sib sib
Definition: types.hh:218
X86ISA::ExtMachInst::vex
VexInfo vex
Definition: types.hh:207
X86ISA::ExtMachInst::dispSize
uint8_t dispSize
Definition: types.hh:230
X86ISA::Decoder::doOneByteOpcodeState
State doOneByteOpcodeState(uint8_t)
Definition: decoder.cc:376
X86ISA::mask
mask
Definition: misc.hh:796
X86ISA::Decoder::FromCacheState
@ FromCacheState
Definition: decoder.hh:186
X86ISA::Decoder::doDisplacementState
State doDisplacementState()
Definition: decoder.cc:585
X86ISA::Decoder::consumeByte
void consumeByte()
Definition: decoder.hh:157
X86ISA::Decoder::doFromCacheState
State doFromCacheState()
Definition: decoder.cc:144
X86ISA::ExtMachInst::legacy
LegacyPrefixVector legacy
Definition: types.hh:205
RefCountingPtr< StaticInst >
X86ISA::Decoder::offset
int offset
Definition: decoder.hh:96
X86ISA::Decoder::doThreeByte0F3AOpcodeState
State doThreeByte0F3AOpcodeState(uint8_t)
Definition: decoder.cc:435
trace.hh
X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:190
X86ISA::Decoder::microcodeRom
static X86ISAInst::MicrocodeRom microcodeRom
Definition: decoder.hh:71
X86ISA::Decoder::OneByteOpcodeState
@ OneByteOpcodeState
Definition: decoder.hh:192
X86ISA::RexPrefix
@ RexPrefix
Definition: types.hh:62
MicroPC
uint16_t MicroPC
Definition: types.hh:144
X86ISA::Decoder::displacementSize
int displacementSize
Definition: decoder.hh:177
X86ISA::Decoder::altAddr
uint8_t altAddr
Definition: decoder.hh:104
X86ISA::Decoder::Vex2Of2State
@ Vex2Of2State
Definition: decoder.hh:188
X86ISA::Decoder
Definition: decoder.hh:52
misc.hh
X86ISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:98
X86ISA::Decoder::State
State
Definition: decoder.hh:184
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
bits
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:75

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