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47 #include "debug/Decoder.hh"
57 decoderFlavor(isa->decoderFlavor())
101 uint16_t highBits =
word & 0xF800;
102 if (highBits == 0xE800 || highBits == 0xF000 ||
103 highBits == 0xF800) {
115 "First half of 32 bit Thumb.\n");
116 emi.instBits = (uint32_t)
word << 16;
135 "IT detected, cond = %#x, mask = %#x\n",
156 offset = (fetchPC >=
pc.instAddr()) ? 0 :
pc.instAddr() - fetchPC;
157 emi.thumb =
pc.thumb();
158 emi.aarch64 =
pc.aarch64();
163 const Addr alignment(
pc.thumb() ? 0x1 : 0x3);
164 emi.decoderFault =
static_cast<uint8_t
>(
177 const int inst_size((!
emi.thumb ||
emi.bigThumb) ? 4 : 2);
180 pc.npc(
pc.pc() + inst_size);
183 this_emi.itstate =
pc.itstate();
184 this_emi.illegalExecution =
pc.illegalExec() ? 1 : 0;
185 this_emi.debugStep =
pc.debugStep() ? 1 : 0;
192 return decode(this_emi,
pc.instAddr());
void process()
Pre-decode an instruction from the current state of the decoder.
Decoder(ISA *isa=nullptr)
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
StaticInstPtr decode(ArmISA::PCState &pc)
Decode an instruction or fetch it from the code cache.
Bitfield< 41, 40 > fpscrStride
Bitfield< 39, 37 > fpscrLen
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void reset()
Reset the decoders internal state.
GenericISA::DelaySlotPCState< MachInst > PCState
@ UNALIGNED
Unaligned instruction fault.
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Feed data to the decoder.
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
unsigned getCurSveVecLenInBitsAtReset() const
Generated on Tue Mar 23 2021 19:41:18 for gem5 by doxygen 1.8.17