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cortex_r52.cc
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27 
28 #include "arch/arm/fastmodel/CortexR52/cortex_r52.hh"
29 
30 #include "arch/arm/fastmodel/iris/cpu.hh"
31 #include "base/logging.hh"
32 #include "dev/arm/base_gic.hh"
33 #include "sim/core.hh"
34 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
35 
36 namespace FastModel
37 {
38 
39 void
40 CortexR52::setCluster(CortexR52Cluster *_cluster, int _num)
41 {
42  cluster = _cluster;
43  num = _num;
44 
45  set_evs_param("CFGEND", params().CFGEND);
46  set_evs_param("CFGTE", params().CFGTE);
47  set_evs_param("RVBARADDR", params().RVBARADDR);
48  set_evs_param("ase-present", params().ase_present);
49  set_evs_param("dcache-size", params().dcache_size);
50  set_evs_param("flash.enable", params().flash_enable);
51  set_evs_param("icache-size", params().icache_size);
52  set_evs_param("llpp.base", params().llpp_base);
53  set_evs_param("llpp.size", params().llpp_size);
54  set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
55  set_evs_param("min_sync_level", params().min_sync_level);
56  set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
57  // Use uint32_t, since the model doesn't like setting these as uint8_t.
58  set_evs_param<uint32_t>("semihosting-ARM_SVC",
59  params().semihosting_ARM_SVC);
60  set_evs_param<uint32_t>("semihosting-T32_HLT",
61  params().semihosting_T32_HLT);
62  set_evs_param<uint32_t>("semihosting-Thumb_SVC",
63  params().semihosting_Thumb_SVC);
64  set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
65  set_evs_param("semihosting-cwd", params().semihosting_cwd);
66  set_evs_param("semihosting-enable", params().semihosting_enable);
67  set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
68  set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
69  set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
70  set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
71  set_evs_param("tcm.a.enable", params().tcm_a_enable);
72  set_evs_param("tcm.a.size", params().tcm_a_size);
73  set_evs_param("tcm.b.size", params().tcm_b_size);
74  set_evs_param("tcm.c.size", params().tcm_c_size);
75  set_evs_param("vfp-dp-present", params().vfp_dp_present);
76  set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
77 }
78 
79 Port &
80 CortexR52::getPort(const std::string &if_name, PortID idx)
81 {
82  if (if_name == "ppi") {
83  // Since PPIs are indexed both by core and by number, modify the name
84  // to hold the core number.
85  return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
86  } else if (if_name == "amba" || if_name == "llpp" || if_name == "flash") {
87  // Since these ports are scalar per core, use the core number as the
88  // index. Also verify that that index is not being used.
89  assert(idx == InvalidPortID);
90  return evs->gem5_getPort(if_name, num);
91  } else {
92  return SimObject::getPort(if_name, idx);
93  }
94 }
95 
96 CortexR52Cluster::CortexR52Cluster(const Params &p) :
97  SimObject(p), cores(p.cores), evs(p.evs)
98 {
99  for (int i = 0; i < p.cores.size(); i++)
100  p.cores[i]->setCluster(this, i);
101 
102  Iris::BaseCpuEvs *e = dynamic_cast<Iris::BaseCpuEvs *>(evs);
103  panic_if(!e, "EVS should be of type Iris::BaseCpuEvs");
104  e->setCluster(this);
105 
106  set_evs_param("core.CLUSTER_ID", params().CLUSTER_ID);
107  set_evs_param("core.DBGROMADDR", params().DBGROMADDR);
108  set_evs_param("core.DBGROMADDRV", params().DBGROMADDRV);
109  set_evs_param("core.PERIPHBASE", params().PERIPHBASE);
110  set_evs_param("core.cluster_utid", params().cluster_utid);
111  set_evs_param("core.cpi_div", params().cpi_div);
112  set_evs_param("core.cpi_mul", params().cpi_mul);
113  set_evs_param("core.dcache-prefetch_enabled",
114  params().dcache_prefetch_enabled);
115  set_evs_param("core.dcache-read_access_latency",
116  params().dcache_read_access_latency);
117  set_evs_param("core.dcache-state_modelled",
118  params().dcache_state_modelled);
119  set_evs_param("core.dcache-write_access_latency",
120  params().dcache_write_access_latency);
121  set_evs_param("core.flash_protection_enable_at_reset",
122  params().flash_protection_enable_at_reset);
123  set_evs_param("core.has_flash_protection", params().has_flash_protection);
124  set_evs_param("core.icache-prefetch_enabled",
125  params().icache_prefetch_enabled);
126  set_evs_param("core.icache-read_access_latency",
127  params().icache_read_access_latency);
128  set_evs_param("core.icache-state_modelled",
129  params().icache_state_modelled);
130  set_evs_param("core.memory.ext_slave_base",
131  params().memory_ext_slave_base);
132  set_evs_param("core.memory.flash_base", params().memory_flash_base);
133  set_evs_param("core.memory.flash_size", params().memory_flash_size);
134  // Use uint32_t, since the model doesn't like setting these as uint8_t.
135  set_evs_param<uint32_t>("core.num_protection_regions_s1",
136  params().num_protection_regions_s1);
137  set_evs_param<uint32_t>("core.num_protection_regions_s2",
138  params().num_protection_regions_s2);
139  set_evs_param("core.num_spi", params().num_spi);
140  set_evs_param("core.ram_protection_enable_at_reset",
141  params().ram_protection_enable_at_reset);
142  set_evs_param("core.has_export_m_port", params().has_export_m_port);
143 }
144 
145 Port &
146 CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
147 {
148  if (if_name == "spi") {
149  return evs->gem5_getPort(if_name, idx);
150  } else {
151  return SimObject::getPort(if_name, idx);
152  }
153 }
154 
155 } // namespace FastModel
FastModel::CortexR52Cluster::CortexR52Cluster
CortexR52Cluster(const Params &p)
Definition: cortex_r52.cc:96
SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:162
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:244
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
FastModel::CortexR52::cluster
CortexR52Cluster * cluster
Definition: cortex_r52.hh:57
gem5_to_tlm.hh
base_gic.hh
FastModel::CortexR52::setCluster
void setCluster(CortexR52Cluster *_cluster, int _num)
Definition: cortex_r52.cc:40
FastModel::CortexR52::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:80
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:243
cpu.hh
FastModel::CortexR52::num
int num
Definition: cortex_r52.hh:58
Iris::BaseCPU::evs
sc_core::sc_module * evs
Definition: cpu.hh:91
sc_core::sc_module::gem5_getPort
virtual ::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
FastModel::CortexR52Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_r52.cc:146
FastModel::CortexR52::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:101
SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:120
FastModel::CortexR52Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_r52.hh:84
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
cortex_r52.hh
core.hh
ArmISA::e
Bitfield< 9 > e
Definition: miscregs_types.hh:61
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
FastModel
Definition: amba_from_tlm_bridge.cc:32
logging.hh
FastModel::CortexR52Cluster
Definition: cortex_r52.hh:75
FastModel::CortexR52Cluster::evs
sc_core::sc_module * evs
Definition: cortex_r52.hh:79
SimObject::params
const Params & params() const
Definition: sim_object.hh:168
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:158
Iris::BaseCpuEvs
Definition: cpu.hh:42
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:141
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